Week 11 Revision with Answers

1. Given a 3-input NOR gate, what is the possible number of states where output is 0?
a) 8
b) 1
c) 7
d) 6
Answer: 7
NOR truth table

2. What is the output Y of the following logic circuit?

a) Y=1
b) Y=0
c) Y=X
d) Y = Not (X) + X

Answer: 1

3. The output of logic circuit given below represents ____ gate.

 a. OR
b. NOR
c. AND
d. NAND

Answer: NAND

4. ________ are examples of combinational circuits.

a. Shift registers
b. Multiplexers
c. Flip-flops
d. Decoders

Answer: multiplexers and decoders

5. Given the diagram below, A and B are the inputs, S is a control input, and Q is the
output. When S=0, then Y=A; S=1; Y=B. What is this combinational circuit called?

A Combinational Y
B circuit

a. 2-input decoder
b. 2-input multiplexer
c. 2-input full adder
d. Logical shifter
 Answer: 2-input multiplexer

6. Whose operations listed as follows is the fastest?

a. Combinational circuits
b. Sequential circuits
c. Latches
d. Flip-flops
Answer: Combinational circuits

7. Consider the circuit below, defined by OR gates, explain whether or not the circuit
has essentially the same behaviour as the RS latch we learnt in the class (made of
NOR gates), namely whether you can use it to set, reset and memorise Q.

Answer:
If either R or S is 1, then Q = Q’ = 1 and there is no way to get them back to 0.

8. In a JK flip flop, J and K inputs are set to logic 1. The current state of Q is ____ when
the next state of Q is _____ .
a. 0, 0
b. 1, 1
c. Undefined, 1
d. 1, 0
Answer: 1, 0

9. If the J-input of a J-K flip-flop is made as a single input and an inverter is connected
between J and K inputs (see the diagram below), the J-K flip-flop becomes
a) T flip-flop
b) D latch
c) R-S flip flop
d) D flip-flop
 Answer: D flip flop

if K = not(J), the next state will always be J. See the table below.
J K Qn+1
0 1 0
0 1 0
1 0 1
1 0 1
If J=D and K=not(D), then the next state will be D. This is the behaviour of the D flip flop.

10. An SRAM has address lines from A0 to A15 and data width from D0 to D7. What is
the total capacity of the SRAM?
a. 64MB
b. 32KB
c. 64KB
d. 16MB
e. 16KB
Answer: 64KB
Total capacity of memory is given by 2no. of address lines x No. of data lines.
No of address line is 16; no of data line is 8
Total capacity of memory = 216 x 23
210 x 26 x 23 = 64KB

NOTE that in COM1031: 210 = 1024 = 1KB (see page 14 of the textbook)

11. What is the highest speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory

Answer B

12. Cache Memory is implemented using the DRAM chips.

a) True
 b) False

Answer: b
The Cache memory is implemented using the SRAM chips
13. Whenever the data is found in the cache memory it is called as _________
a) HIT
b) MISS
c) FOUND
d) ERROR

Answer: a

14. Given the following table,

Operation Frequency CPI
ALU 50% 1
Load 25% 2
Store 15% 3
Branch 10% 2
Which of the following statement is true about the average of CPI of the above
table?
a) ALU takes ~30.30% of the total cycles
b) Load takes ~27.27% of the total cycles
c) Store takes ~27.27% of the total cycles
d) Branch takes ~10.10% of the total cycles

Answer: Store takes ~27.27% of the total cycles

ALU takes ~30.30% of the total cycles

Operation Frequency, f CPI CPI * f %time

ALU 50% 1 0.5 0.5/1.65 = 30.30%
Load 25% 2 0.5 30.30%
Store 15% 3 0.45 27.27%
Branch 10% 2 0.2 12.12%
100% 1.65

15. The first machine cycle of an instruction is always a

a. Memory read cycle
b. Fetch cycle
c. I/O cycle
d. Memory write cycle

Answer: Fetch cycle

16. Given the following ARM assembly code, what are the equivalent instructions of a
high-level language?
mov r3, #1
 loop:
cmp r3, #10
bge endloop
add r3, r3, #1
b loop
endloop:
…
a) b)
r3 = 1; r3 = 1;
while ( r3 <= 10 ) { while ( r3 < 10 ) {
r3 = r3 + 1; r3 = r3 + 1;
} }

c) d)
r3 = 1; r3 = 1;
while ( r3 > 10 ) { while ( r3 >= 10 ) {
r3 = r3 + 1; r3 = r3 + 1;
} }

Answer b)

17. Given the following ARM assembly code, what are the equivalent instructions in a
high-level language?

CMP R1,#1
CMPEQ R2,#2
BEQ Routine

a) IF R2=1 AND R1=2 THEN Routine

b) IF R1=1 OR R2=2 THEN Routine
c) IF R1=1 AND R2=2 THEN Routine
d) IF R2=1 OR R1=2 THEN Routine

Answer c)

18. Which one of the ARM Assembly Language instructions performs the following instruction?
R0 = R1/256

a) MOV R0, R1, LSL #8

b) MOV R0, R1, LSR #8
c) MOV R0, R1, ASR #8
d) MOV R0, R1 ASR #8
e) MOV R0, R1 LSL #8
f) MOV R0, R1 LSR #8

Answer: b) and c)

19. Which one of the ARM Assembly Language instructions performs the following instruction?
set bits 2 to 4 of R0
a) ORR R0, R0, #0000 1110
 b) ORR R0, R0, #1111 1111
c) ORR R0, #1111 1111
d) ORR R0, R0, #0x1C
e) ORR R0, R0, #0x11
f) ORR R0, #0x11

Answer: d) ORR R0, R0, #0x1C ;

0x1C = 0b11100

20. Which of the following is correct for a D latch?

a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled
Answer: b)

21. A positive edge-triggered D flip-flop will store a 1 when ________

a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH

Answer: b

22. The characteristic equation of D-flip-flop implies that ___________

a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state

Answer: d)
See the characteristics table of D Flip Flop”
D Q -- current Q(n+1) -- next
0 0 0
0 1 0
1 0 1
1 1 1

D is the input, Q is the current state, Q(n+1) is the next state output.
Q(n+1) will always be 0 when D is 0, irrespective of the current state of the flip flop
Q(n+1) will always be 1 when D is 1, irrespective of the current state of the flip flop

So , we have the characteristic equation of D flip-flop: Q(n+1) = D.

The characteristic equation of D flip-flop states that “The output of the flip flop at the next
clock cycle will be equal to the input at the current clock cycle.”
 23. Given the following circuit, Y can be expressed as:

a) Y = BC + A
b) Y=C
c) Y = AC’ + BC
d) Y=B
e) Y = BC + A’B’

Answer: Y = B
Output of 4:1 mux:
X = A• (A B) + 1 • (A’B) + 0 • (A’B’) + 0 • (AB’)
X = AB + A’B = B (A + A’) = B
Output of 2:1 mux:
Y = C’X + C•B
= C’B + C•B
= B(C + C’)
=B

24. Find the average memory access time (AMAT) for a processor with a 1 ns clock cycle time, a miss
penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access
time (including hit detection) of 1 clock cycle. Assume that the read and write
miss penalties are the same and ignore other write stalls.

Answer: The average memory access time per instruction is

AMAT = Time for a hit + Miss rate x Miss penalty
= 1 + 0.05 x 20
= 2 clock cycles
 or 2 ns.

25. Suppose a program (or a program task) takes 1 billion instructions to execute on a processor
running at 2 GHz. Suppose also that 50% of the instructions execute in 3 clock cycles, 30%
execute in 4 clock cycles, and 20% execute in 5 clock cycles. What is the execution time for the
program or task?

Answer:
We have the instruction count: 109 instructions. The clock time can be computed quickly
from the clock rate to be 0.5×10-9 seconds. So we only need to compute clocks per
instruction as an effective value:
Value Frequency Product
3 0.5 1.5
4 0.3 1.2
5 0.2 1.0
CPI = 3.7
Then we have
Execution time = 1.0×109 × 3.7 × 0.5×10-9 sec = 1.85 sec.

26. Given the input waveforms shown below, sketch the output, Q, of an D-latch.

Answer:
27. Given the input waveforms shown below, sketch the output, Q, of an D flip
flop.

Answer:
 28. Design a ‘not equal’ comparator for 32-bit numbers. Sketch the schematics.
HINT: Look at the ‘equals’ comparator.

Answer:

29. Design a 4-bit left rotator using multiplexers. Sketch a schematic of your
design.
HINT: Use the 4-bit left shifter as inspiration.

Answer:
Remember if rotamt (rotate amount) = 2, that is binary 10.
If the input A = 1100 and we rotate 2 to the left, Y = 0011.

In this solution, when rotamt = 10

the inputs (A) map to outputs (Y) as follows:

A3 -> Y1

A2 -> Y0

A1 -> Y3
 A0 -> Y2

30. Configure the ALU shown below to perform the following 8-bit operations:

a) 67 + 32
b) 0000 1010 AND 0000 0110
c) 45 < 34

In each case, give the value for each of the control bits F2:0 and the result
(Y) in binary form.
A B
N N

N
1

F2
N

Cout +
[N-1] S
Extend
Zero

N N N N
1

0
3

2 F1:0
N
Y
Answer:

a) F2:0 = 010, Y = 0110 0011

b) F2:0 = 000, Y = 0000 0010
c) F2:0 = 111, Y = 0000 0000
(45-34 results in a positive number, so sign bit S7 =0;
multiplexer selects Y = S7, zero extended)

31. Implement the following functions using a single 16x3 ROM. Use dot notation to indicate the
ROM contents:

i. X = AB + BCD + AB
ii. Y = AB + BD
iii. Z=A+B+C+D

Answer:
 4:16
Decoder
0000
0001
0010
0011
0100
0101
4 0110
A,B,C,D
0111
1000
1001
1010
1011
1100
1101
1110
1111

X Y Z