THE MICROARCHITECTURE I4GIC

FUNCTIONS AND CHARACTERISTICS OF INSTRUCTIONS

It was already mentioned that the instructions directly executable by any processor
are very primitive in nature. In general, they are as simple as: ‘copy a byte from here
to there’ or ‘add contents of these two registers’, or something similar to these.

In general instructions can be placed in 3 categories:

1. Data move type instructions
2. Arithmetic and logical instructions
3. Program ow control and machine control instructions.
DATA MOVE TYPE
These instructions are most frequently used to copy data from one place to another.
The source and destination of movements may be registers within the processor or
some external memory locations or a combination of both.
Immediate data, presented as a part of the instruction, may also be loaded to some
destination defined by these instructions.
Data is passed through the bus and note that internal CPU bus is much faster than
external bus. That’s why data movement between registers-registers or between
CPU’s components are always recommended.
To be simple, CPU prefer handling data with the same size ( 8 bits or 16 bits or …) but in real practice it can handle
different length of data. 8 bits CPU can normally handle 8 bits data, 4 bits data, 2 bits data and 1 bit data.

It is getting more complicated the more data length a CPU can handle but the possibility is there.
ARITHMETIC AND LOGICAL TYPE
Most processors offer instructions for four basic arithmetic operations (add, subtract,
multiply and divide) with signed and unsigned integers and essential logical
operations, e.g., AND, OR, XOR, NOT, with shift and rotate instructions.
These instructions normally required some status flags such as carry, signed, zero, …
PROGRAM FLOW CONTROL TYPE
Program flow control instructions form the third major group of processor instructions.
Generally, they are sub-divided as conditional and unconditional branching and
subroutine call and return.
Branching instructions act depend on the status registers (flags)

Carry and zero are most widely used branching conditions. Instructions related with
branching as per the condition of carry flag or zero condition are offered by all
processors
Common data transfer type
instructions for processors

Common arithmetic type

instructions for processors
Common logical type
instructions for processor

Common program flow control

type instructions for processors
 Schematic of a few formats of instructions

In general, an instruction is always transferred or store once together. But it is also possible to do so in different
transaction or locations. Anyway, it is going to be complicated so avoid it unless you don’t have the choices.
Register field variation for processor with (a) four and (b) sixteen registers
LET’S IMAGINE WE HAVE THE FOLLOWING COMBINATION

1. Set your expectation

2. Visualizing Data-flow and Registers

Our ALU will have two input registers and one output register. We have designated the accumulator (register A)
as one of the two input register for the ALU. Therefore, we shall need one more input register and we designate
that register as X, which would be a temporary register. To hold the output from the ALU, we include another
register in our design, say register Y. Both X as well as Y would be 4-bit registers, like all other registers in our
example case

Register organization
3. Data Path Design
The next step is to provide all necessary paths so that the data can flow properly from one register to another as
per our requirements.

Considering first two instructions, we note that we must provide a bidirectional data path between the accumulator
and all four registers, so that accumulator may be loaded from any register or may be stored in any register.

For addition and subtraction operations, apart from

accumulator, another set of data must be available in the
temporary register X, which should be copied from the
indicated register as per the instruction. Therefore, there must
be another bus connecting the temporary register X with all
four registers from R0 to R3.

This data bus would be unidirectional , from register-set (R0 –

R3) to X-register as in no case data would be copied from this
temporary register (X) to any other register (R0 – R3).

Bidirectional data path of accumulator

 To start with, note that we have not provided any mechanism of loading any immediate
data (using immediate addressing mode) to the accumulator or four other registers (R0 –
R3), for the purpose of focusing on essential issues.

Next, we have avoided indicating any flag register, which is considered to be essential for
any ALU, for keeping the problem a simple one. Furthermore, the data path, provided by us
is not an optimum one, but takes care of all necessary data flow, as per the demand of our
initial assumptions regarding the problem.

In total, we have provided six data paths. Only one of these six paths is bidirectional, and
the remaining five are unidirectional. Note that the bidirectional data path is also capable
of copying the data from any register (R0 – R3) to another register (R0 – R3), which we are
not implementing for our present example problem.

From accumulator, there are three different data paths. One is the bidirectional data path for registers R0 – R3. The
second one is from the accumulator to the ALU. The third one is to the accumulator from Y register. These last two paths
would be used only during the ALU operations.

From each of the four registers (R0 – R3), there are two data paths, one for communicating with the accumulator and
another to move the selected register’s data to X-register. The second path would be necessary before any ALU
operations.
For the X-register, two separate data path exists, one to get the data from any one of the four registers R0 – R3.
Another one is to load it within the ALU. For Y-register also there are two separate data paths, one to receive the
result from ALU and another to send the data to the accumulator. All these ensure that we have provided
adequate data paths to maintain the data ow, as per the requirement of the problem statement.

4. Control signal requirement

To make our unit a working one, we need to design all necessary control signals for data propagation or proper
sequential flow of data.

What is a control signal?

 In this case, control signal indicates those signals whose change of logic level would allow or disallow (enable
or disable) the data flow from one point (register etc.) to another.
Summary of control signals
4. Need micro instructions

 What is meant by microinstructions?

To implement any instruction, several steps would be necessary. These steps are designated as micro-steps and
the necessary instructions to generate these micro-steps are known as microinstructions.

For example, let us take the first instruction: Load accumulator by a register and assume that the instruction is
referring a general purpose register R0. We find that the following micro-steps (and sequence) are necessary to
implement the instruction Load accumulator by R0:

1. Make ENA0 as 0 to enable output of R0 to reach accumulator.

2. Latch the input from R0 to accumulator by a high to low signal at S5.

Note that the sequence is also important in this case. If we activate S5 first and then activate ENA0, we
shall not be able to receive the correct data within accumulator.
Micro-steps for Loading Accumulator

Micro-steps for saving accumulator

Micro-steps for adding
accumulator with a register

Micro-steps for subtracting a

register from accumulator