Computer Architecture

Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-8
I/P-O/P Configuration:
A computer can serve no useful purpose unless it communicates with the external environment.
Instructions and data stored in memory must come from some I/P device. Computational results must be
transmitted to the user through some O/P device. Commercial computers include many types of I/P and
O/P devices. The terminal sends and receives serial information. Each quantity of information has eight
bits of an alphanumeric code. The serial information from the keyboard is shifted into the I/P register
INPR. The serial information for the printer is stored in the O/P register OUTR. These two registers
communicate with a communication interface serially and with the AC in parallel. The I/P-O/P
configuration is shown in the figure below:

Input-Output Terminal Serial Communication Computer register and flip-flop

Interface FGO

Receiver
Printer Interface OUTR

AC

Transmitter
Keyboard Interface INPR

FGI
Input-Output configuration

The transmitter interface receives serial information from the keyboard and transmits it to INPR. The
receiver interface receives information from OUTR and sends it to the printer serially.

Input/ Output Instructions:

Input/output instructions are needed for transferring information to and from the AC register, for
checking the flag bits, and for controlling the interrupt facility input/output instructions have an opcode
1111 and are recognized by the control when D7 =1 and I=1 the remaining bits of the instruction specify
the particular operation. The control functions and microoperation for the input/output instructions are
listed in the table below. These instructions are executed with the clock transition associated with timing
signal T5. Each control function needs a Boolean relation D7IT3, which is designated for convenience by
the symbol P. The control function is distinguished by one of the bits in IR(6-11). By assigning the symbol
Bi to bits I of IR, all control functions can be denoted by PB i for i=6 through 11. The sequence counter
SC is cleared to 0 when P= D7IT3=1.

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 Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-8

D7IT3=P (Common to all input/output instruction)

IR(i)=Bi [bit in IR(6-11) that specifies the instruction]
P : SC  0 Clear SC
INP PB11 : AC(0 − 7)  INPR, FGI  0 Input Character
OUT PB10 : OUTR  AC(0 - 7), FGO  0 Output Character
SKI PB9 : If (FGI = 1) then (PC  PC + 1) Skip on input flag
SKO PB8 : If (FGO = 1) then (PC  PC + 1) Skip on output flag
ION PB7 : IEN  1 Interrupt enable on
IOF PB 6 : IEN  0 Interrupt enable off

Program Interrupt:
The interrupt enable flip-flop IEN can be set and cleared with two instructions. When IEN is
cleared to 0 (with the IOF instruction) the flags cannot interrupt the computer. When IEN is set to 1 (with
the ION instruction) the computer can be interrupted. These two instructions provide the programmer with
the capability of making a decision as to whether or not to use the interrupt facility. The way that the
interrupt is handling by the computer can be explained by means of the flowchart of figure below: An
interrupt flip-flop (R) is included in the computer. When R=0, the computer goes through an instruction
cycle.

During the execute phase of the instruction cycle, IEN is checked by the control. If it is 0, it
indicates that the programmer does not want to use the interrupt so control continues with the next
instruction cycle. If IEN is 1, the control checks the flag bits. If both flags are 0, it indicates that neither
the input nor the output registers are ready for the transfer of information. In this case, control continues
with the next instruction cycle. If either flag is set to (1) while IEN=1, flip-flop (R) is set to 1. At the end
of the execute phase, the control checks the value of R, and if is equal to 1, it goes to an interrupt cycle
instead of an instruction cycle.

The interrupt cycle is a H/W implementation of a branch and save return address operation. The
return address available in the PC is stored in a specific location where it can be found later when the
program returns to the instruction at which it was interrupted. This location may be a processor register,
a memory stack, or a specific memory location. Here we are chosen the memory location at the address.
Control then inserts address 1 into PC and clears IEN and R so that no more interruptions can occur until
the interrupt request from the flag has been serviced.

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 Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-8

Instruction Cycle 0= =1 Interrupt Cycle

R

Fetch & Decode instruction

Execute =0
IEN
Instruction

=1

FGI

=0

FGO

=0

Flowchart for interrupt cycle

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 Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-8
Example:
This example shows what happens during the interrupt cycle as shown in the figure below.
Suppose that an interrupt occurs and R is set to 1 while the control is executing the instruction at address
255. At this time, the return address 256 is on the PC. The programmer has previously placed an input-
output service program in memory starting from address 1120 and a BUN 1120 instruction at address 1.
This is shown in Figure (a).
0 0 256
1 0 BUN 1120 0 BUN 1120
255 255
Main Main
PC=256 256
Program Program

1120 1120
I/O Program I/O Program

1 BUN 0 1 BUN 0
(a): before interrupt (b): after interrupt cycle
Demonstration of the interrupt cycle
The instruction that returns the computer to the original place in the main program is a branch
indirect instruction with an address part of 0. This instruction is placed at the end of the I/O service
program. After this instruction is read from memory during the fetch phase, the control goes to the indirect
phase (because I=1) to read the effective address. The effective address is in location 0 and is the return
address that was stored there during the previous interrupt cycle. The execution of the indirect BUN
instruction results in placing into PC the return address from location 0.

Types of Interrupts:
There are three major types of interrupts that cause a break in the normal execution of a program. They
can be classified as:
1-External Interrupts:
Come from I/P-O/P (I/O) devices, from timing devices, from circuit monitoring the power supply, or from
any other external source.

2-Internal Interrupts:
Arise from illegal use of an instruction or data examples of these interrupts; attempt to divide by zero,
stack overflow, and an invalid opcode.

3- Software Interrupts:
External and internal interrupts are initiated from signals that occur in the H/W of the CPU. An S/W
interrupt is initiated by executing an instruction S/W interrupt is a special call instruction by the
programmer to initiate an interrupt procedure at any desired point in the program

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