Chapter 3

MOS Inverters:
Static Characteristics
1
MOS Inverter
• Positive logic convention
– “1” represents high voltage of VDD

– “0” represents low voltage of 0

• The inverter threshold voltage, Vth

– The input voltage,

0<Vin<Vth Doutput VDD

– The input voltage,

Vth<Vin<VDD Doutput 0

2
General circuit structure of an nMOS
inverter

• The driver transistor

– The input voltage V =V
IN GS
– The output voltage
V =V
out DS

– The source and the

substrate are ground, VSB=0

• The load device

– Terminal current IL, terminal
voltage VL

ID(Vin,Vout)=IL(VL)

3
 Voltage transfer characteristic (VTC)
• The VTC describing Vout as a function of Vin under DC condition

• Very low voltage level

– Vout=VOH (o/p high voltage)
– nMOS off, no conducting current, voltage drop across the load is very small,
the output voltage is high

• As Vin increases
– The driver transistor starts conducting, the
output voltage starts to decrease
– The critical voltage point, dVout/dVin=-1
• The input low voltage VIL
• The input high voltage VIH
• Determining the noise margins

• Further increase Vin

– Output low voltage VOL, when the input
voltage is equal to VOH
– The inverter threshold voltage Vth
• Define as the point where Vin=Vout

4
Noise immunity and noise margin
• VIL is the maximum
allowable voltage
Vin<VOL LOGIC 0
Vin>VIL as a result of noise

• VIH is the minimum

allowable voltage
Vin>VOH LOGIC 1
Vin<VIH as a result of noise

• NML=VIL-VOL
• NMH=VOH-VIH
• The transition region, uncertain
region

5
Power and area consideration

• The DC power dissipation

– The product of its power supply voltage and the amount of current
down from the power supply during steady state or in standby mode
– PDC=VDDIDC=(VDD/2)[IDC(Vin=low)+IDC(Vin=high)]
– In deep submicron technologies
• Subthreshold current more power consumption

• The chip area

– To reduce the area of the MOS transistor
• The gate area of the MOS transistor
• The product of W and L

6
 Resistive-load inverter
• Operation mode
– Vin<VT0, cut off
• No current, no voltage drop across
the load resistor
• Vout=VDD

– VT0<Vin<Vout+VT0, saturation
• Initially, VDS=VOUT, VDS>Vin-VT0
• I = kn  ( )2
R Vin −VT 0
2
• With Vin ↑, I D ↑, Vout↓
– Vin>Vout+VT0, linear
• The output voltage continues to
decrease
 
• I R = kn  2 (Vin −VT 0 )Vout −Vout2
2

7
Calculation of VOH, VOL
• Calculation of VOH
– Vout=VDD-RLIR
– When Vin is low ID=IR=0 VOH=VDD
• Calculation of VOL
– Assume the input voltage is equal to VOH
– Vin-VT0≥Vout  linear region
– VDD −Vout
IR =
RL
Using KCL for the output node, i.e. IR = ID
VDD −VOL kn
RL

=  2 (VDD −VT 0 )V0L −V0L2
2

 1  2
V0L2 − 2  VDD −VT 0 +  V0L + VDD = 0
 knR L  kn R L

1  − 2V DD
2

V0 L = VDD −VT 0 +
1
− VDD −VT 0 + 
kn RL  kn RL  kn RL

8
 Calculation of VIL, and VIH
By definition, VIL is the smaller of the two input voltage at which the slope of the
VTC becomes equal to -1. i.e. dVout /dVin = -1
Vout  Vin - VT0 , saturation region
VDD - Vout k n
=  (V−V
in T0
)2
RL 2

−
1 dVout
 = k n ( Vin−V )  − 1  (−1) = k  n (Vin−V T 0 )
T0
RL dVin RL
1
VIL = VT 0 +
k nRL

2
kn R L  1 1
Vout (Vin = VIL ) = VDD − VT 0 + −VT 0  = VDD −
2  k n RL  2k n RL

VIH is the larger of the two voltage points on the VTC at which the slope is equal
to -1 Vout  Vin - VTO , linear region
VDD-Vout kn
RL 2

=  2 (Vin −V T 0 )Vout −Vout
2

1 dVout k n  dVout dV 
−  =  2  (Vin−V )T 0 − 2Vout  out 
RL dVin 2  dVin dVin 


−  (−1) = k n (V in −VT 0) (−1)+ 2V out
1
RL

1
VIH = VT 0 + 2Vout −
k nRL
To determine the unknown variables
VDD -Vout k   1  
= n  2V T0 + 2Vout − −VT 0  Vout −Vout2 
RL 2   k nRL  
2 VDD
Vout (Vin= V IH) = 
3 k nRL

V
8 VDD
= V T 0 + 3  knRL
1
− knRL 9
VTC for different knRL
• The
10 term knRL plays an important role in determining the shape of the
voltage transfer characteristic
• knRL appears as a critical parameter in expressions for VOL, VIL, and VIH
• knRL can be adjusted by circuit designer
• VOH is determine primarily by the power supply voltage, VDD
• The adjustment of VOL receives primarily attention than VIL, VIH
• Larger knRL VOL becomes smaller, larger transition slope
 11
Power consumption
• The average power consumption
– When input low, VOL
• The driver cut-off, no steady-state current flow, DC power
consumption is zero
– When input high, VOH
• Both driver MOSFET and the load resistor conduct a
nonzero current
• The output voltage VOL, so the current ID=IR=(VDD- VOL)/RL
–P DC(average)
=
VDD VDD −VOL

2 RL
Problem-1
Problem-2
Chip area
• The
18 chip area depend on two
parameters
– The W/L ratio of the driver
transistor
• Gate area WxL
– The value of the resistor RL
• Diffused resistor
– Sheet resistance 20 to
100Ω/square
– Very large length-to-width rations
to achieve resistor values on the
order if tens to hundreds of kΩ
• Ploysilicon resistor
– Doped polysilicon (for gate of the
transistor), 20 to 40 Ω/square
– Undoped polysilicon, Rs Rs~10M
Ω/square
– The resistance value can not be
controlled very accurately Ð large
variation of the VTC
– Low power static random access
memory (SRAM)
Inverters with n-type MOSFET load
• The
19 resistive-load inverter
– The large area occupied by the load resistor
• The main advantage of using a MOSFET as
the load device
– Smaller silicon area occupied by the transistor
– Better overall performance
• Enhancement-load nMOS inverter
– The saturated enhancement-load inverter
• A single voltage supply
• A relative simple fabrication process
• VOH=VDD-VT,load
– The linear enhancement-type load
• VOH=VDD
• Higher noise margins
• Two separate power supply voltage (drawback)
– Both type suffer from relatively high stand-by
(DC) power dissipation
• Not used in any large-scale digital applications
Depletion-load nMOS inverter
• Slightly more complicated
– Channel implant to adjust the
threshold voltage
• Advantages
– Sharp VTC transition better
noise margins
– Single power supply
– Smaller overall layout area
– Reduce standby (leakage)
current
• The circuit diagram
– Consisting
• A nonlinear load resistor,
depletion MOSFET, VT0,load<0
• A nonideal switch (driver) ,
VT ,load = VT 0,load + r ( 2 F + Vout − 2F )
enhancement MOSFET, When the output voltage is small,Vout  VDD + VT,load
VT0,driver>0 The load transistor is in saturation region
– The load transistor I D,load =
k n,load
 
 VT ,load (Vout )
 −VT ,load (Vout ) =
k n,load 2 2

• VGS=0, always on 2 2
For larger output voltage level,Vout  VDD + VT,load
– The load transistor operates in the linear region

I D,load =
k n,load
2

 2VT ,load (Vout )  (VDD −Vout )− (VDD −Vout )2 
16
Cont…
Calculation of VOH, VOL, VIL, ViH
When Vin is smaller than VT 0  driver → off, load → linear region
zero drain current,VOH = VDD

I D,load =
2
k n,load

 2VT ,load (VOH )  (VDD −VOH )− (VDD −VOH )2 = 0 
To calculate the output low VOL
assume, Vin = VOH = VDD  driver → linear region, load → saturation region
k driver
2
 2  (VOH −VT 0 )VOL −VOL
2 k
2
 
= load  −V T ,load (VOL ) 2 
 
(VOH −VT 0 )2 −  kload   VT ,load (VOL )
2
VOL = VOH −VT 0 −
 kdriver 

17
 Calculation of VOH, VOL, VIL, VIH
Calculation of VIL
The driver  saturation region, the load  linear region
k driver
2
 (Vin−V )T0=
2 k load
2

 2VT ,load (Vout )  (VDD −V out )− (VDD −Vout )2 
Differential both sides with respect to Vin
  dVT ,load   dV 
 2VT ,load (Vout ) −  + 2(VDD −Vout ) − T ,load 
k load   dVout   dVout 
k driver  (Vin−V )T0=  
2  dV 
− 2(VDD −V out )− T ,load  
  dV out  

sbustitute dVout /dVin = -1
k 

VIL = VT 0 +  load   V out −VDD + VT ,load (Vout ) 
 kdriver 
Calculation of VIH
The driver  linear region, the load  saturation region


kdriver  2 (V
in −VT 0 )Vout −Vout =
2

kload
 −VT ,load (Vout )2
2 2
Differential both sides with respect toVin
  dVout   dV   dV   dV 
k driver  Vout + (Vin +VT 0 )  −Vout  out  = kload  −VT ,load (Vout )  T ,load    out 
  dVin   dVin   dVout   dVin 
sbustitute dVout /dVin =-1
k   dV 
VIH = VT 0 + 2Vout + load  −VT ,load (Vout ) T ,load 
 kdriver   dVout 
dVT ,load 
= 18
dVout 2 2F +Vout
VTC of depletion load inverters
• The
24 general shape of the
inverter VTC, and ultimately,
the noise margins, are
determined by
– The threshold voltage of the
driver and the load
• Set by the fabrication process
– The driver-to-load ratio
kR=(kdriver/kload)
• Determined by the (W/L)
ratios of the driver and the
load transistor
• One important observation
– A sharp VTC transition and
larger noise margins can be
obtained with relative small
driver-to-load ratios
• Much small area occupation
Design of depletion-load inverters
• The
25 designable parameters in the inverter circuit are
– The power supply voltage VDD
• Being determined by other external constrains
• Determining the output level high VOH=VDD
– The threshold voltages of the driver and the load
• Being determined by the fabrication process
– The (W/L) ratios of the driver and the load transistor
• W 
kn,driver   
 W
 
VT ,load (VOL )
2
k  L driver
,k R =  L driver
k R = driver = , kR =
kload 2(VOH −VT 0 )VOL −VOL
2
 W  W
kn,load     
 L load  L load

• Since the channel doping densities are not equal

– The channel electron mobilities are not equal
– K’n,load≠k’n,driver
• The actual sizes of the driver and the load transistor are
usually determined by other constrains
– The current-drive capability
– The steady state power dissipation
– The transient switching speed
Power consideration
• The
26 steady-state DC power consumption
– Input voltage low
• The driver off, Vout=VOH=VDD
• No DC power dissipation
– Input voltage high, VinVDD and Vout=VOL
•
)  −VT ,load (VOL )2
Kload
I DC (Vin = VDD =
2

= driver  2 (VOH −VT 0 )VOL −VOL2
K
2

Assume the input voltage level low 50% operation
time and high during the other 50%
VDD kload  −V (V )2
PDC =  T ,load OL
2 2
Area consideration
• Figure
27 (a)
– Sharing a common n+
diffusion region
• Saving silicon area
– Depletion mode
• Threshold voltage adjusted by
a donor implant into the
channel
– (W/L)driver>(W/L)load, ratio
about 4
• Figure (b)
– Buried contact
• Reducing area
• For connecting the gate and
the source of the load
transistor
– The polysilicon gate of the
depletion mode transistor
makes a direct ohmic with
the n+ source diffusion
– The contact window on the
intermediate diffusion area
can be omitted
Example 5.3 (1)
Example 5.3 (2)
Example 5.3
(3)
30
CMOS inverter
• Complementary push-pull
–31High input nMOS driver, pMOS load
– Low input pMOS driver, nMOS load
• Two important advantages
– Virtually negligible steady state power dissipation
– VTC exhibits a full output voltage swing between 0V and VDD, transition is very
sharp
• Latch up problem
– Formation of two parasitic bipolar transistors VGSN=Vin, Vdsn=Vout
– Preventing VSGP =Vdd-Vin, Vsdp= Vdd-Vout
• Guard rings
Circuit operation
• Region A: Vin<VT0,n
– nMOS off, pMOS on ID,n=ID,p=0,
Vout=VOH=VDD
• Region B: Vin>VT0,n
– nMOS saturation, the output
voltage decreases
– The critical voltage VIL, (dVout/dVin)=-1
is located within this region
– As the output further decreases
pMOS enter saturation, boundary
of region C
• Region C:
– If nMOS saturation VDS,nVGS,n-
VT0,n  Vout Vin-VT0,n
– If pMOS saturation VDS,nVGS,p-
VT0,p  Vout Vin-VT0,p
– Both of these conditions for device
saturation are illustrated graphically as
shaded areas
• Region D: Vout<Vin-VT0,p
– The criical point VIH
• Region E: Vin>VDD+VT0,p
– Vout=VOL=0
Circuit operation
• The
35 nMOS and the pMOS transistors an be

seen as nearly ideal switches

– The current drawn from the power supply in both
these steady state points region A and region E
• Nearly equal to zero
• The only current Ðreverse biased S, D leakage current
– The CMOS inverter can drive any load
• Interconnect capacitance
• Fan-out logic gates
• Either by supplying current to the load, or by sinking current
from the load
The steady-state input-out voltage
characteristics
36
 Calculation of VIL, VIH
nMOS saturation, pMOS linear
kn
2
 (
2
)
 (VGS ,n −VT 0,n )2 = p  2 VGS , p −VT 0, p VDS ,P −V DS
k 2

,p

kn
2
k
2
( )
 (Vin −VT 0,n )2 = p  2  Vin −V DD −VT 0, p (Vout −VDD )− (Vout −VDD )2 
  dV   dV 
( )
k n  (Vin −VT 0,n )= k p  Vin −VDD −VT 0, p   out  + (Vout −VDD )− (Vout −VDD )  out 
  dVin   dVin 
substituting Vin = VIL and (dVout /dVin ) = -1
(
k n  (VIL −VT 0.n ) = k p  2Vout −VIL + VT 0, p −VDD )
2Vout + VT 0, p −V DD + kRVT 0,n kn
VIL = wherek R
=
1+ k R kp

nMOS linear, pMOS saturation


 2 (VGS ,n −VT 0,n )VDS ,n −V DS,n = p  (V GS , p −VT 0, p )
kn 2 k 2

2 2


 2 (Vin −VT 0,n )Vout −Vout  = p  (Vin −V DD −VT 0, p )
kn 2
k 2

2 2

k n ( Vin −VT 0,n ) out  +Vout −Vout   out   = k p (Vin −VDD −VT 0, p )
  dV   dV 
  dVin   dVin 
substiting Vin = VIH and (dVout /dVin ) = -1
k n  (−VIH +VT 0,n + 2Vout )= k p  (VIH −VDD −VT 0, p )
VDD +VT 0, p + k R  (2Vout +VT 0,n ) 30
V =
Calculation of Vth
inveter th reshold voltage is defined as Vth = Vin = Vout
The38
Since the CMOS inverter exhibits large noise margins and very sharp VTC transitio n the
inverter t hreshold voltage emerges as an imporant parameter characteri zing the DC
performanc e of the inverter
For Vin = Vout , both trans istor are in saturation mode

 (VGS ,n − VT 0,n )2 = p  (V GS , p − VT 0, p )
kn k 2

2 2

 (V in − VT 0,n )2 = p  (V in − V DD −V T 0, p )
kn k 2

2 2
 kp
 (V DD + VT 0, p )
kp

Vin  1 +  = VT 0,n +
 k  k
 n  n

 (VDD + VT 0, p )
1
VT 0,n +
Vth = R
k
 1 
1 + 
 k R
If Vin = Vth , the output vol tage can actually attain any
value between (Vth -V T 0 ,n )and (Vth -V T 0,p )
Threshold voltage
• The
39 Region C of VTC
– Completely vertical
• If the channel length modulation effect is neglected, i.e. if =0
– Exhibits a finite slope
• If >0
• Fig 5.22 shows the variation of the inversion (switching) threshold
voltage Vth as function of the transconductance ratio kR
VTC and power supply current
• If40input voltage is either
smaller than VT0,n, or
larger than VDD+VT0,p
– Does not draw any
significant current from the
power supply
– Except for small leakage
current and subthreshold
currents
• During low-to-high and
high-to-low transitions
– Regions B, C, and D
– The current being drawn
from the power source
– Reaching its peak value
when Vin=Vth (both
saturation mode)
 Design of CMOS inverters
V DD +VT 0, p +Vth 
2
1 th VT 0,n−V k 
= k = n= 
k R VDD +VT 0, p −Vth k p  Vth−V T 0,n 
R

1
The switching threshold voltage of an ideal inverter is defined as V th,ideal = VDD s
2

2
k   0.5 +V
substituting 5.74 in 5.73   n  =  VDD T 0, p 
   
 k p ideal  0.5VDD +VT 0,n 
k 
we can achieve complely symmetric input - output characteristics by setting VT 0 = VT 0,n = VT 0,p   n  =1
 k symmertric
 p
inverter

nC OX    n W 

W
kn L  n  L n
= =
 pC OX    p  W 
kp W
 L p  L p
assume tox, Cox have the same value for nMOS and pMOS
 W
 
 L  n p 230cm2 /V  s W   W
=      2.5 
W  n 580cm /V  s  L  p
2
 L n
 
Lp
For a symmetric CMOS inverter with VT 0,n = VT 0,p and kR = 1

VIL =  (3VDD + 2VT 0,n ),VIH =  (5VDD − 2VT 0,n )

1 1
8 8
VIL + VIH = VDD , NM L = VIL −VOL = VIL , NM H = VOH −VIH = VDD −VIH NM
L = NMH = VIL 34
Example 5.4
42
 Supply voltage scaling in CMOS inverters
The static
43 characteristics of the CMOS inverter allow
significant variation of supply voltage without affecting
the functionality of the basic inverter
The CMOS inverter will continue to operate correctly
with a supply voltage limit value

– min
VDD = V T 0,n + VT 0, p
– Correct inverter operation will be sustained if
at least one of the transistors remains in
conduction, for any given voltage
– The exact shape of the VTC near e limit
value is essentially determined by
subthreshold conduction properties
• If the power supply voltage is reduced
below the sum of the two threshold
– The VTC will contain a region in which none
of the transistors is conducting
– The output voltage level is determine by the
previous state of the output
– The VTC exhibits a hysteresis behavior
Power and area consideration
• Power consideration
44
– DC power dissipation of the circuit is almost negligible
– The drain current
• Source and drain pn junction reverse leakage current
• In short channel leakage current
• Subthreshold current
– However, that the CMOS inverter does conduct a significant amount of current
during a switching event
• Area consideration
Basic CMOS NOR and NAND Gates

(a) Two-input CMOS NOR logic circuit and (b) truth

table
Cont….

(a) Two-input CMOS NAND logic circuit

and (b) truth table
Problem
 Design 2 input CMOS NOR gate and NAND gate
circuits to give following parameters.

 NML = 1.65 V, NMH = 2.4V,

 VDD = 5 V,

 VT0,n = |VT0,p| = 0.7 V

 µnCOX = 40 µA/V2

 µpCOX = 20 µA/V2