Practical and Efficient Approaches to Device

Modeling and Power Amplifier Module Design

2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) | 979-8-3503-0764-1/23/$31.00 ©2023 IEEE | DOI: 10.1109/BCICTS54660.2023.10310879

Hans Rohdin*, Bart Jansen, William Snodgrass, J. Stephen Kofol, Sonja Nedeljkovic, Ziad El Chami, Will Sutton and
Tom Dungan

Wireless Semiconductor Division, Broadcom Inc. *[email protected]

Abstract—A ‘best-practices’ approach to device modeling and standard way, most are reluctant to take the plunge. In fact, to
power amplifier (PA) module design optimization is described. It take full advantage of the design approach requires a somewhat
was developed to help designers go from the arrival of footprint atypical mindset. You should realize the benefits of physically
and electrical specs to samples-out as fast and accurately as pos- based, and physically scalable, active device modeling. You
sible. It uses the same modulation signals and average output benefit from being patient (even with fast workstations), and
powers as on the lab measurement benches, properly averages organized enough to work on parallel designs and projects.
the spec’d quantities (Gain, ACPR, EVM, PAE, IRL,..), and co- One particularly effective designer worked on 10 design opti-
vers the full frequency band. Designing the module involves or- mizations in parallel (while on vacation, no less). You should
ganizing the simulation output into a single weighted and nor-
have a vigilance for accuracy, tempered by the reality of the
malized figure of merit that the optimizer can use as its one-goal
error function. This FOM also serves as a meaningful progress
complexities involved. You should realize that modeling of a
monitor, and design-review quality measure. Waveform engi- complex PA module is like a chain, where each link has to be
neering and gain curve shaping are not explicitly part of the pro- strong enough. There is no point perfecting one (e.g. the active
cess, but happen ‘under the hood’, automatically, in a properly device model), if, for instance, the SMD (Surface-Mounted
weighted and averaged way. Physically based and physically Devices: L’s and C’s) models are flawed, or if the electromag-
scalable (geometrically and thermally) active device models netic (EM) modeling is not accurate enough, or not done with
(GaAs HBT and PHEMT) serve as the foundation of the ap- enough properly distributed ports. You should be willing to
proach, with more emphasis on adherence to known and man- address the full complexity (all modes, output power set points,
ageable temperature-dependent device physics than perfect snap- signals, bands, specs, etc.) simultaneously. If you do this, it
shot model-measurement agreement. Such models are not subor- pays off: In one of the first applications of the approach sam-
dinates to the semiconductor fabrication process and measured ples of a high-band multi-mode PA module went from specs
data, but can help improve the former and monitor the latter. It received to samples out in 10 weeks.
allows for meaningful investigations of device structure varia- Standard approaches to PA design still work, just not as ef-
tions and product yield, and promotes accuracy in circuit enve- ficiently, rationally, and documentably as the approach de-
lope (CE) and electrothermal (ETh) simulations. The optimiza- scribed here. In our view, designing today’s complex PA mod-
tion is done with harmonic balance (HB) and S-parameter (SP) ule products is beyond what a human brain can and should
simulation data. The setup incorporates envelope tracking (ET) handle, and should not critically rely on historically- and text-
and digital predistortion (DPD) in an efficient way.
book-based gut feelings and ‘insights’. These do, however,
Keywords—Power amplifier, HBT, HEMT, simulation, optimi-
typically serve as good starting points for the optimizer.
zation, ACPR, EVM, PAE, physical device model, model extraction, After this somewhat philosophical introduction follows in
scaling, thermal resistance, envelop tracking, predistortion, FEM Sec. II a discussion on how layout, thermal and process scaling
was added to the ADSHBT model [1], available in Keysight’s
I. INTRODUCTION Advanced Design System (ADS) [2]. We refer to this extended
We describe design and modeling approaches that we con- model as SAHBTM, with S for Scalable. Section III outlines
sider best-practices and somewhat obvious nose-to-the- how the model parameters are extracted using DC, SP and LP
grindstone ‘real-world’ engineering. It has been developed in (load pull) data on up to 28 devices of various sizes, orienta-
continuously improving and unpublished form since 2003. It is tions and base-emitter configurations. It includes several mod-
not focused on producing perfect agreement between simula- el-measurement comparisons. Section IV outlines the all-specs
tion and measurement, nor on standard PA classification (typi- full-bandwidth PA optimization approach. It includes an early
cally not constant over the band anyway), unweighted snapshot application, one that efficiently helped us make informed deci-
quantities and gain curves. Instead it focuses on the bottom- sions on technology alternatives. It also includes optimized
line, properly averaged, spec’d quantities measured on the spec’d quantities of a full-complexity n79 (4.4-5.0 GHz) PA
bench. No matter how good the modeling, the bench is where module, measured and simulated.
the final tweaks are made, and the more the bench-work can be II. SAHBTM: ADSHBT MODEL WITH SCALING ADDED
supported by simulation the better. Based on interactions with
incoming engineers over many years, the approach may actual- The ADSHBT model [1,2] captures the device physics well,
ly not be entirely obvious. Having been taught the standard and allows accurate simulation of complex, highly non-linear
curricula, and often having spent years doing PA design the HBT circuits. There are not enough internal nodes to get fmax

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 exactly right [3], but this is a small-signal narrow-band quanti- is process dependent. Intensive parameters (delay parameters,
ty under ideal matching that is non-critical for our large-signal temperature exponents, ideality factors, built-in voltages, ..) are
wide-band case. With the many collector delay model parame- left independent of HBT dimensions.
ters, fT can be modeled very well over bias and temperature, as The thermal resistance model in Fig. 2 is a key component
can the DC characteristics. The convergence properties in in SAHBTM. It allows for an accurate and unique determina-
large-signal operation are excellent, something very important tion of the model parameters, in particular the many tempera-
in optimization. One potential weakness is the one-parameter, ture coefficients/exponents (TC’s). This is important for the
voltage- and temperature-independent model for reverse transit physical integrity of the model, and particularly benefits the
time (Tr). This turned out to be relatively non-critical, with a accuracy of ETh simulations. The wide array of devices used in
rather interesting result. model extraction are laid out so as to allow using just one
In a sub-circuit - and ultimately in a PDK (process design RTH,up in the extraction. The thermal model is simple but accu-
kit) that ties model to layout - were added scaling equations for rate enough, with fringing flows inspired by analogy to electro-
all ADSHBT’s extensive parameters. Fig. 1 illustrates a general statics. It was checked against 3D thermal simulations. The
HBT layout, with the lateral geometry parameters that define it. topology allows straightforward application to a flip-chip cop-
For the emitter (E) and base-collector (BC) mesa dimensions, per pillar (CuP) situation.
we allow for known and unknown offsets. The latter are ex- Most scaling laws are self-evident, typically areal with ad-
tracted from wide-ranging DC and AC data (Sec. III). A few justable offsets and electrostatic fringing. The internal base and
subtle effects, such as a periphery/area (P/A) induced effect on collector resistances (i.e. those associated with the “GOOD
the characteristic Kirk current (Ikrk), to model the effect of current” area in Fig. 2) utilize Anholt’s expression for 4-sided
electron spread at high injection, are included, as are DC pa- feeding [4]. The external base resistance is straight-forward to
rameters to model the effects on the knee region (low VC, high calculate from the layout, and the metal, contact and sheet re-
JC) of emitter proximity to BC mesa walls. The latter repre- sistances (separately measured on metal meander and TLM
sents one of the few dispersive anomalies in GaAs HBTs, and structures). Similarly for the external collector resistance, alt-
hough this is not quite as straightforward. However, with the
low subcollector sheet resistance of a well-designed process,
non-exactness here is not consequential.
To allow simulation experiments, ‘top-level’ knobs for
threshold voltages (VBE0 and VBC0), high- and low-current ’s,
emitter resistance, and base sheet resistance, are included. In
addition, and alternatively, there are knobs for underlying
physical quantities like base and emitter doping, and base and
collector thicknesses (WB and WC). These collectively affect a
wide range of device behavior. They require accurate enough
models for transport and recombination parameters. Due to the
complexity of charge and transport in the collector the effect on
fT of varying WC is the least well modeled.
ADSHBT’s delay formalisms are by necessity rather com-
plex. The many expressions appear correctly documented in
[2]. For increased clarity SAHBTM reformulates the collector
Fig. 1. Parameters defining the lateral HBT dimensions in SAHBTM. These delay with parameters that we have physically based estimates
also cover BEB..EB, EBE…BE and BE structures. for, such as fully, and optimally (for fT), depleted collector
thicknesses, saturated velocity, overshoot velocities at low
VCB’s, flat-band voltage corresponding to zero delay, etc.
The ADSHBT model has 110 non-noise parameters [2], of
which our HBTs and simulations require all but 7 (Vaf, Var,
Abex, Tnf, Tnr, Cth1 and Cth2), and we are primarily only in-
terested in the total thermal resistance (Rth1+Rth2, Xth1). Of
the 101 parameters SAHBTM uses 96 in their original intensive
form, or in normalized form. The features in SAHBTM add a
net ~41 adjustable parameters resulting primarily from:
 ΔL and ΔW offsets for DC currents, capacitances and Re
 Rbi, Rbx, Rci and Rcx being calculated from process con-
trol monitor data, with adjustable borderline shifts, and an
internal effective/average vertical Rc component
 Abcx calculated with an adjustable borderline shift
 Two parameters (one per orientation) for shifts in emitter-
edge proximity to the BC mesa edge. These affect the DC
knee through a third DC knee parameter
 Seven parameters for the Rth1+Rth2 model (Fig. 2)
Fig. 2. Scalable thermal resistance model in SAHBTM .

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  Two parameters to model PE/AE dependence of Ikrk. adjustment to bias. The number of parameters can also be
 Eight parameters added (two WC’s fixed to known/esti- smaller if, for instance, a reduced set of devices is used. The
mated values) to allow a more transparent collector delay. number of data points is largely proportional to the number of
In return, four ADSHBT parameters are calculated (Tcmin, devices. The numbers shown (real numbers, not bytes) are for
Tfc0, Vtc0Inv and VtcminInv) 28 devices. The ~41% increase in the number of parameters
 A separate - recombination-like - Tr (TrX) for the external over the single-device extraction is negligible compared to the
area (“BAD current” in Fig. 2) ~28x increase in data used for the fits. With such a large da-
 Parasitic CBE from M1 running off the emitters on Si3N4 ta/parameter ratio, the fit quality will obviously be reduced to
 Base delay typically estimated analytically, and fixed some degree. However, it comes with a much stronger tie to
device physics, allowing sound wide-range scaling. This is
 Tkrk=1 ps and Xikrk=0 to avoid numerical degeneracy
particularly important for ETh simulations of PA modules,
III. MODEL EXTRACTION AND VALIDATION which rely on accurate T-dependences in the various-size de-
vices. An extraction on 20+ devices typically takes 2-4 weeks.
We are left with having to determine ~142 parameters. AD- Fig. 3 shows measured and model common-emitter DC
SHBT‘s ~101 parameters are typically extracted on individual characteristics for a smallest and a largest device. This illus-
devices using Keysight software [5]. For SAHBTM we have trates the benefit of including very small devices: It exposes IV
since its 2006 inception gone about it differently. With the regions affected by DC (and AC) parameters that otherwise
scaling described in Sec. II, we extract the single set of ~142 would not be properly fitted. The same cannot be accomplished
parameters on a multitude of devices (up to 28 presently), at 25 with pulsed measurements. The large uncertainty in associated
and 85 °C chuck temperature. Additional self-heating is key to junction temperature for such measurements prevents the ex-
extracting the RTH parameters, as well as - self-consistently traction accuracy we are targeting.
with the junction temperatures - the full parameter set. It is a Being able, in Fig. 3, to go to 0.5 V higher VC for the large
multi-step process (Table I) where all devices, and both base
device reflects the positive TC of the avalanche breakdown
temperatures are present (except in step #8). Each step involves
field in GaAs. We have a Verilog-A version of ADSHBT that
an ADS optimization where the |model-measurement| errors
are minimized. The ~28 HBTs vary primarily in includes breakdown, However, with the typical dominance of
thermal breakdown/runaway in GaAs HBTs we only occa-
 Emitter size (and P/A): 4-240 μm2 (occasionally 360 μm2)
sionally extract it. Here pulsed data could be helpful.
 Emitter width (1.6-6.0 μm) and number (1-4) Fig. 4 shows fT at the swept and stepped biases in Fig. 3.
 BC mesa shape: Notch and trapezoidal (from wet-etch and The significantly lower fT for the smallest device is due to (1)
two orientations) larger relative and absolute parasitic BE capacitance internal to
 Configurations: BEB, EBE, EB, BEBEB, EBEBE, …. the BC mesa due to an M1 design rule; and (2) larger relative
 BC mesa extension beyond emitter or base contact effect of the global (i.e. same on all devices) BE and BC offset
The HBTs are biased up to near-BVCE0, and to ~1.3-2 capacitances determined during extraction steps 3 and 4. These
mA/m2, with a T<190 oC constraint. The latter is enforced are small capacitances that despite our best efforts don’t get
using earlier (and quite stable) RTH parameters. The total num- deembedded out. That’s a minor example of an issue that a
ber of parameters in Table I can be larger than 142 for three physical and scalable model can reveal and correct/avoid.
reasons: (1) some parameters are adjusted in later steps; (2) we Extraction step #8 is a relatively recent addition to mini-
allow some external L/C parasitics to depend on chuck temper- mize the error in saturated output power (Psat). We managed to
ature and orientation; and (3) in step #8 we may allow minor do that (Fig. 5a), and in the process noticed something interest-
Table I: Typical model extraction flow, measured data items, and associated model parameters
Number of
Parameters and parameter categories
# Measurement data Params Data
ADSHBT SAHBTM
Low-V Forward & Forward & reverse E-C inj. E mesa size offsets
1 14 6.6k
Reverse Gummel Ideal & nonideal IBE
2 Reverse Gummel Ideal & nonideal IBC BC mesa size offsets 9 4.0k
2-4 GHz SP  CBE(VBE) BE capacitance E mesa size offsets
3 14-18 7.3k
Global offset capacitances Metallization capacitance
2-4 GHz SP  CBC(VBC) BC capacitance BC mesa size offsets
4 12 5.9k
Global offset capacitances Metallization capacitance
Full Forward & Reverse Gummel DC TC’s (temperature coef- RTH: Scalable model (7 parameters; Fig. 2)
T-limited (T<~190 oC) IC(IB,VC) ficients)RE: normalized value & size offsets
Ideal IBE RC: 5-parameter scalable model
5 32-43 21.9k
Beta & knee compression BC mesa walls: Proximity shifts & knee sensitivity coefficient
Heterojunction parameters Fudge factor for internal metallization resistance
Internal-external shifts for the BC region
~12-20 GHz SP  Z  L External parasitic inductance Allow for different values at 25 and 85 oC
6 6 0.5k
Fudge factor for internal scaling inductance model
1.5-5.9 GHz SP  fT, Y11, Y12 Delay (including TC’s) Delay: 6 physically-based parameters
7 Cemax & Ccmax (per um2) Ikrk: 2 parameters for behavioral P/A-dependent model 35 175k
BC charge fractions (Fex’s)
1-5.5V LP (max Psat); 240 m2, 25 oC Cemax & Ccmax (per um2) TrX, typically some of the shift and fudge parameters listed
8 ~10 3k
above that don’t affect on-state fT

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 ing. ADSHBT model’s reverse transit time (Tr) has a default
value of 1 ns. Our historical median value is ~3 ns. Neither
represents an expected transit time. After the introduction of
step #8, not only is Psat better predicted, but Tr is taking on
values in line with transit times (<1 ps), while TrX is in line
with base recombination times (~1 ns). Fig. 5b-d shows 4.7-
GHz modeled (blue) and measured (red) sweeps of other key
large-signal quantities for a 240 m2 HBT with load chosen for
maximum Psat to maximally expose any issues with the diffi-
cult knee region.
Another result interesting from a device physics perspective
is that the electron velocities in the partially reformulated col-
lector delay settle near values produced by more direct meth-
ods. The high-field (saturated) velocity is consistently ~9x106
cm/s, well in line with long-established experimental and theo-
retical ranges. The maximum velocity (near maximum fT) is
consistently 4-6x107 cm/s. This is a very large value, but is in
line with what is predicted with non-stationary transport [6].
The extraction procedure does not rely on standard methods
for measuring parameters like Re and Rth1+Rth2 on individual
devices. With one occasional exception: We sometimes extract
Xre on a mid-sized device with the method in [7]. This because
Xth can trade off degenerately with Xre.
Load pull data, like those in Fig. 5, are typically used solely
for model validation. Since we use them in extraction (step #8),
Fig. 3. Measured (red) and model (blue) common-emitter DC characteristics their use is somewhat dual. For occasional further validation
of the smallest and largest device in a 28-device SAHBTM extraction. we significantly increase the complexity. Fig. 6 shows a one-
The non-uniformly stepped variable is base current. stage n79 PA mounted in flip-chip CuP configuration on a
PCB (printed circuit board). Input match is on chip. The stage
consists of 10 parallel 2x2.7x39 m2 HBT units. The output is
tuned off-chip with load pull to the 3rd harmonic; in Fig. 7 for
maximum Psat at VCC=5.5V. This tuning has the largest meas-
urement-simulation discrepancy. We determined that the im-
perfect agreement is unlikely to be due to EM (3D ADS FEM)
or thermal issues. It may be due to residual incompleteness of
the device model (likely then associated with the knee region),
something being off in the thermal modeling of the CuP+PCB,
measurement issues (e.g. a small resistance or a bias offset not
accounted for), flip-chip related strain, or some combination of
issues. Nevertheless, we consider the results a validation of the
modeling, and consistent with the philosophy outlined in the
abstract and introduction. Just to re-emphasize: The HBT mod-
el is a single, physically based, and physically scalable one. As
such it has also served to expose issues with processes, design
rules and measurements. Other groups have pursued scalable
approaches to HBT modeling (e.g. [8]).
IV. ALL-SPECS FULL-BANDWIDTH PA DESIGN OPTIMIZATION
Beyond being useful for visual/gut-feel validation, the top
‘waterfall’ curves, and the other plots in Fig. 7, are of limited
importance and use. For instance, Psat is rarely visited under
normal modulated operation, and then under much cooler con-
ditions. Likewise, under ET operation, only a small subset of
the waterfall points is in play, and (contrary to popular belief) a
design optimum is not fundamentally defined by some magical
level of compression or constant power gain. For these and
other reasons, key features of our PA module optimization are:
 Proper averaging (as required by FCC and customer specs)
at the various output power set points, using the appropriate
Fig. 4. fT at the swept and stepped biases in Fig. 3 power distribution functions (PDF)

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 Fig. 6. Die+PCB for EM simulation of a one-stage flip-chip n79 PA
.

Fig. 7. Swept and stepped (VCC: 1.0-5.5V) characteristics of the PA in Fig. 6 at

Fig. 5. Measured (red) and simulated (blue) 4.7-GHz max-Psat load pull data
4.7 GHz with output tuned for maximum Psat at 5.5V. Simulated
on a 3x2x40 μm2 HBT. VCC=5 V
(blue) and measured (red).

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  The same signals that are used on the lab measurement
benches are used in simulation and optimization
 All major specs are worked on simultaneously
 A properly normalized and weighted real scalar measure is
used as the one-goal error function for the optimizer, and as
a figure of merit for the design
 A ~5th order HB simulation is swept over input power, and
stepped in fundamental frequency over the full band
 An SP simulation is swept at a bias point from near DC to
near the 5th harmonic frequency
 Multi-sweep curves (Fig. 7) are replaced by one sweep that
incorporates in VCC the optimizable ET shaping function
 Optimizable DPD is included in the input source
The simulation/optimization setup is built up link-by-link as
accurately as possible, while adhering to known and managea-
ble physics. Nevertheless, it will never provide an exact predic-
tion of reality. We have found over the years, however, even
with increasing modulation bandwidths, that the simulations
are sound and accurate enough to drive the design towards an
optimum. So, the approach should continue to be helpful for Fig. 8. Linearity-efficiency tradeoff lines for a few technologies available to
us in 2012. Simulation of optimized 2-stage B38 LTE SandBox PA’s.
design, and for final tuning on the bench.
The design FOM, referred to as REOAWN (for Weighed
and Normalized OverAll Relative Error) involves sums over all
specs:
∑𝑖 𝑊𝑖 𝑅𝐸𝑖2
𝑅𝐸𝑂𝐴𝑊𝑁 = √ ∑𝑖 𝑊𝑖
, (1)
where 𝑅𝐸𝑖 = 0 if spec i is met, and
(𝑠𝑖𝑚) (𝑠𝑝𝑒𝑐)
𝑋𝑖 −𝑋𝑖
𝑅𝐸𝑖 = (2)
𝑆𝐷𝑖
if it is not. Here Xi is the i:th spec’d quantity (Gain, ACPR,
EVM, PAE, IRL,..), and SDi is what’s considered to be a Sig-
nificant Deviation from the spec. For instance, we consider 2
dB to be a significant deviation in ACPR, and 1-2% a signifi-
cant deviation in PAE. Wi is the weight (relative importance)
the designer or design team assigns to the quantity. For yield
purposes - since yield optimization is impractical for PA’s of
any complexity - specs used in the optimization should have
reasonable margins added to regulatory and customer values.
In (1), HB REi’s are averaged over the band.
To the right hand side of (1), under the square root, we add
- without the normalizing ∑𝑖 𝑊𝑖 denominator - a term for sta-
bility factor (kstab). This is evaluated over the wide and rather Fig. 9. Device-level BV-fT tradeoff for technologies of interest to us in 2012.
dense range of small-signal frequencies at the bias point, and linearity-efficiency trade-off. Other similar exercises produced
remains surprisingly important even with the advent of more a more ‘ideal’ ~-1 dB/% linearity-efficiency slope. These, and
sophisticated probing of stability [9]. In particular, keeping other considerations, led the division to stick with GaAs.
kstab>1 has proved to significantly help HB convergence during Within GaAs, the choice is between HBT and PHEMT.
long optimizations. Without normalization, and with a large The two (E-mode) PHEMT lines differ in gate length (0.5 and
weight, kstab>1 is a self-imposed spec that is not traded off 0.25 m), and fall around the purple HBT line to form the dis-
against another. In the end, it is always satisfied, with zero con-
tinct GaAs group in Fig. 8. The HEMT model used [11] was
tribution to REOAWN, and without the normalizing denomina-
developed in Verilog-A with the same philosophy as SAHBTM.
tor artificially reducing REOAWN.
Basic performance of our HBTs and PHEMTs were similar,
In contrast, ACPR and PAE are tradeoff specs that, with
but HBT was preferred for the fewer anomalies, better VTH
spec margins, are not intended to be met. By varying their
uniformity and better yield; at the price of reduced intrinsic
weights you move up and down a tradeoff curve. Fig. 8 is an
ruggedness. Figs. 8-9 suggest that the natural next technology
example of such an exercise from 2012 when alternatives to
is GaN, with HEMTs presently the only alternative. Perfor-
GaAs technologies were considered. We found that the classi-
mance and ruggedness should be excellent. Trap-induced
cal fT.BV=EBD.vsat/2 device/material-level FOM and tradeoff anomalies will need to be sufficiently minimal.
([10] & Fig. 9) translate (at least for those non-DPD/ET PA’s)
roughly into a PAE(%)-ACPR(dB) FOM, with a ~-0.5 dB/%

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 The ‘SandBox’ PA (SBPA) used to produce Fig. 8 is also
useful when evaluating proposed changes in topology, design
rules, epi, and other ideas. Rather than relying on (1) hand-
waving and gut feel, on one end of the spectrum, and (2) gobs
of multi-quantity, multi-load, multi-frequency, non-averaged,
non-weighted LP data on individual devices, on the other end,
it allows you to relatively quickly make informed dispassionate
decisions, based largely on a single, properly averaged, nor-
malized and weighted FOM that is derived from a near-full
complexity PA. An SBPA, like the one in Fig. 10:
 Simulates fast due to the relatively few nodes, and absence
of a complex PCB
 Includes PCB-like ground paths, losses and phase shifts
 Has the full nonlinear behavior of the active devices Fig. 11. SMC characteristics. Solid lines: vendor model; Green line: vendor’s
maximum valid frequency; Dashed lines: our scalable model.
 Accounts for nonlinearity cancelation in multi-stage PA’s
applied to every device (i.e. on the production line).
 Naturally constrains load and source harmonic impedances
SMD models are links in the modeling chain. Fig. 11 illus-
to what is practically implementable in a product
trates a weak (solid lines) and a strong (dashed lines) version. It
 Includes optimizable DPD and ET can be quite insidious: While the vendor’s model (solid lines)
 Includes switch+filter SnP (n-port S-parameter) models is reasonable up to the high end of its range (green vertical
 Includes continuously scalable SMD models, with ground- line), it fails in regions important to our highly nonlinear PA’s
proximity correction for the SMC’s (well beyond the green line). Our scalable SMD models use
 Covers the full band physical topologies for the SMC’s, and behavioral expressions
 Uses the full REOAWN optimization setup, including, in for the SML’s. Model parameters are fitted to the full range of
particular, the PDF-based averaging vendor models. The resulting continuously scalable models
REOAWN and all other interesting (typically spec’d) output extrapolate gracefully to high frequencies. Solutions to such
quantities are calculated from the HB and SP simulation output problems are also commercially available [14].
using a function created in ADS’s Application Extension Lan- A full-complexity PA module with switches and filters on a
guage (AEL). Among many tasks, the function generates gain, complex PCB is optimized the same way as an SBPA, and here
ACPR, EVM, and PAE, all averaged at spec’d output power the benefit of patience and multi-tasking comes in. The hun-
set points. The signals used are segments of those used on the dreds of EM ports involved, with proper distribution of the
lab measurement benches. This is particularly important for HBT unit cells, slow down the optimization’s rate of progress.
full-complexity product modules. In the HB+SP optimization Not to a point where shot-gun approaches are preferable, how-
setup, only the PDFs matter. In post-optimization (partially ever, given that teams that do final tuning typically don’t have
time-domain) Circuit Envelope (CE) simulations, EVM is time to evaluate more than a couple of chip alternatives.
waveform-based (no receiver involved) using a recently devel- Staying with band n79, a full-complexity 3-stage version is
oped formalism [12] available as a function in ADS. This illustrated in Fig. 12. As in Fig. 6, the chip, including (in post-
largely agrees with our own earlier method (still used in the optimization simulation) the MIM capacitors, is part of the 3D
HB+SP setup), but being calculated solely in the frequency EM modeling (ADS FEM). All matching networks are part of
domain, is much faster, and presumably more accurate. the setup. SMD components are modeled as just discussed,
With ET, the setup uses a behavioral ICC and slew-rate de- with their solder terminals part of the EM setup. Switches and
pendent model for tracker efficiency, fitted to tracker data, and filters are included as SnP components with measured 25 oC
applied post-simulation (in the AEL function) to PAE. With data. ET biasing is used, and the input phase is predistorted.
regards to ET and DPD, we have suggested that the required Table II shows key parameters, measured and simulated at 25.7
calibration procedure could be made more optimal and with dBm average output power with 5G 60-MHz modulation. Elec-
less risk of damage to the module if our optimization approach trothermal CE simulation may yield the overall most accurate
were adapted to the measurement bench [13]. The use of meas- agreement with measurement, but is very slow (~2.5 days), and
ured data would be massively faster than what designers deal its result not all that different from CE alone, or for that matter
with in simulation, although presumably not fast enough to be HB in this case. Harmonic balance is certainly accurate enough
to be used in the optimization done prior to this end result.
This, and other links, like variable MIM capacitors, are weaker
during optimization, but are strong enough to drive the design
towards an optimum. Referring back to the abstract and intro-
duction, it is this process that we are primarily interested in, not
exact final simulation-measurement agreement. The latter is,
for instance, typically (and in this case) affected by not ac-
counting for the temperature rise in filters and switches. In
addition to sound modeling, what helps the agreement in Table
II is the PDF-based averaging. This reduces moderate single-
point discrepancies (e.g. Psat) to near-irrelevance.
Fig. 10. Birdseye overview of a 2-stage SandBox PA in ADS.

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 tive, rational and documentable. The methods may appear
unduly complicated, but from our real-world product perspec-
tive, we consider them to be as simple as possible. But not
simpler, as the saying goes. With all links strong enough, the
modeling chain has consistently proved to help design and
final bench tuning. As modulation bandwidths increase, the
discrepancies between HB and CE simulation results, and be-
tween HB simulations and measurements, will likely increase.
But we should still be closer to an optimum than we would
with other methods, resulting in fewer required design ver-
sions and iterations. We have used the approach up to 500
Fig. 12. EM setup for a full-complexity 3-stage flip-chip n79 PA module. MHz modulation bandwidth (on a 12 GHz carrier), with quite
reasonable CE-HB agreement.
TABLE II: FULL-COMPLEXITY N79 POWER AMPLIFIER MODULE. ET+DPD. CP
OFDM QPSK 60 MHZ CF=7DB. POUT=25.7 DBM. HEAT-SINK: 25C
ACKNOWLEDGMENT
Freq Simulation
Quantity
(GHz)
Measured
HB CE CE+ETh
Many thanks to (1) Broadcom colleagues: Dan Stoneking,
Marty Shipley, Forest Dixon, Eshar Ben-Dor, Jeongsoo Lee,
4.43 31.2 29.7 29.5
Andy Weilert, Ike Choi, Chris Billingsley, Diego Guerra and
4.60 30.3 29.6 29.4 29.7
Gain (dB) Dave Feld; (2) Keysight folks: Andy Howard, Nilesh Kamdar,
4.80 30.9 29.8 29.6
Masaya Iwamoto, Jan Verspecht, Maziar Farahmand, Cindy
4.97 29.2 29.5 29.3
4.43 20.6 21.4 21.6
Cui, Jon Tseng, Matt Ozalas, Wenlei Lian, Lisa Xie, Wenyan
4.60 22.3 21.2 21.6 23.3
Ding, Edwin Yeung, Nacim Bravo, Wilfredo Rivas-Torres,
PAE (%)
4.80 21.4 21.9 21.8
Lihua Wang, Bruce Fisher, David Spinner and others; and (3)
4.97 19.5 21.4 21.8
Verilog-A experts: Marek Mierzwinski, Boris Troyanovsky,
4.43 -39.0 -41.0 -39.0
Patrick O’Halloran and Jim McMahon.
4.60 -38.8 -40.9 -39.6 -38.0
ACPR (dB) REFERENCES
4.80 -38.9 -40.7 -38.8
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EVM (%)
Meas: Demodulated IQ 4.60 1
1.9 0.63 0.93 1.1 [2] Circuit Components Nonlinear Devices: ADSHBT Model, Keysight
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We have found these approaches to scalable device model-
ing and PA module design to be maximally physical, effec-

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