Timing - Hazard

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Outline

• Performance Limits of Synchronous Systems

• Delay in logic gates
• Delay in wires
• Delay in combinational networks
• Clock Skew
• Delay in flip-flops
• Glitches

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 Recall: General Model of Synchronous Circuit

clock input

input CL reg CL reg output

option feedback

output
• All wires, except clock, may • Combinational Logic Blocks (CL)
be multiple bits wide. – no internal state
• Registers (reg) – output only a function of inputs
– collections of flip-flops • Particular inputs/outputs are
• clock optional
– distributed to all flip-flops • Optional Feedback
– typical rate?
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General Model of Synchronous Circuit
clock input

input CL reg CL reg output

option feedback

output

• How do we measure performance?

– operations/sec?
– cycles/sec?
• What limits the clock rate?
• What happens as we increase the clock rate?
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 Limitations on Clock Rate
1 Logic Gate Delay 2 Delays in flip-flops

input
D
output
clk
t Q
• What are typical delay
values? setup time clock to Q delay

• Both times contribute to

limiting the clock period.

• What must happen in one clock cycle for correct

operation?
• Assuming perfect clock distribution (all flip-flops see the
clock at the same time):
– All signals must be ready and “setup” before rising edge of clock.
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 Example: Parallel-Serial Converter
T  time(clk→Q) + time(mux) + time(setup)
T  clk→Q + mux + setup

clk

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General Model of Synchronous Circuit
clock input

input CL reg CL reg output

option feedback

output
• In general, for correct operation:
T  time(clk→Q) + time(CL) + time(setup)
T  clk→Q + CL + setup
for all paths.
• How do we enumerate all paths?
– Any circuit input or register output to any register input or circuit output.
– “setup time” for circuit outputs depends on what it connects to
– “clk-Q time” for circuit inputs depends on from where it comes.

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 Gate Switching Behavior
s
g

• Inverter: d

• NAND gate:

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Delays in a series of gates
• Cascaded gates:

Vout

Vin

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 Gate Delay due to fan out
• Fan-out:
2
1
3

• The delay of a gate is proportional to its output capacitance.

Because, gates #2 and 3 turn on/off at a later time. (It takes
longer for the output of gate #1 to reach the switching
threshold of gates #2 and 3 as we add more output
capacitance.)

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Gate Delay with a general circuit
• “Fan-in”
– Does it affect the delay of the individual gate?
– When does the gate begin its transition?

• What is the delay in this circuit?

• Critical Path: the path with the maximum delay, from any
input to any output.
– In general, we include register set-up and clk-to-Q times in critical
path calculation.
• Why do we care about the critical path?
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Delay in Flip-flops
• Setup time results from
delay through first latch.
D clk

clk clk
clk’
Q
clk’

setup time clock to Q delay • Clock to Q delay results

from delay through second
latch.
clk’

clk’
clk

clk

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Wire Delay
• In general, wire behave as
“transmission lines”:
– signal wave-front moves close to
the speed of light
» ~1ft/ns
– Time from source to destination is
called the “transit time”.
– In ICs most wires are short, and the
transit times are relatively short
compared to the clock period and
can be ignored.
t – Not so on PC boards.

– ...Or long wires on fast chips

» Busses
» Global Control signals
» Clock
• Rule of thumb: wire must be
x treated as a transmission line if
its length exceed l/100.
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Architectural Level Delay

Data busses

datapath Controller

clock

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 Wire Delay
• Even in those cases where the • For short wires on ICs,
transmission line effect is resistance is insignificant
negligible: (relative to effective R of
– Wires posses distributed transistors), but C is
resistance and capacitance important.
v1 v2 v3 v4
– Typically around half of C of
gate load is in the wires.
• For long wires on ICs:
– Time constant associated with
– busses, clock lines, global
distributed RC is proportional to
control signal, etc.
the square of the wire length
– Resistance is significant,
therefore distributed RC
effect dominates.
v1
v2
v3
– signals are typically
v4 “rebuffered” to reduce delay:

time

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Modern rule of thumb
• Transistors are cheap
– And their local wires
• Wire is what counts

• Often pays to do extra local computation (gates)

to reduce wire delay

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Clock Skew
• Unequal delay in distribution of the clock signal to various
parts of a circuit:
– if not accounted for, can lead to erroneous behavior. (see next)
– Comes about because:
» clock wires have delay,
» circuit is designed with a different number of clock buffers from
the clock source to the various clock loads, or
» buffers have unequal delay.
– All synchronous circuits experience some clock skew:
» more of an issue for high-performance designs operating with
very little extra time per clock cycle.

clock skew, delay in distribution

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Clock Skew Constraints
CLK’ CLK

CLK

CL CLK’

clock skew, delay in distribution

• If clock period T = TCL+Tsetup+Tclk→Q, circuit will fail

– Delay relative to CLK = Tskew + TCL+Tsetup+Tclk→Q
• Therefore:
1. Control clock skew
a) Careful clock distribution. Equalize path delay from clock source to
all clock loads by controlling wires delay and buffer delay.
b) don’t “gate” clocks.
2. T  TCL+Tsetup+Tclk→Q + worst case skew.
• Most modern large high-performance chips
(microprocessors) control end to end clock skew to a few
tenths of a nanosecond.
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 Gate Delays and Timing Diagrams (1)

⚫ Output of a gate changes after delay from the input changes

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 Gate Delays and Timing Diagrams (2)

⚫ A circuit with two gates:

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 Hazard

haz-ard (noun) A chance of being injured or harmed; danger:

Space travel is full of hazards. A possible chance
of danger: fire hazard. (tr.v.) To expose to danger
or harm. (Middle English hasard), dice game, from
Old French, possibly from Old Spanish azar, possibly
Arabic az-zahr, the gaming die : al-, the + zahr,
gaming die.]

CMPUT 329 - Computer

Organization and
Architecture II 28
 Circuit’s Behavior

The steady-state behavior of a circuit is the value of the

output after the inputs have been stable for a long time.

The transient behavior of a circuit is the value of the

output while (or soon after) the inputs change.

The glitch is a (often undesirable) short pulse produced

in the output during a transient phase.

If a circuit has the possibility of producing a glitch,

the circuit has a hazard.

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 Hazards/Glitches

• Hazards/glitches: unwanted switching at the outputs

– Occur when different paths through circuit have different propagation
delays
» As in pulse shaping circuits we just analyzed
– Dangerous if logic causes an action while output is unstable
» May need to guarantee absence of glitches
• Usual solutions
– 1) Wait until signals are stable (by using a clock): preferable (easiest to
design when there is a clock – synchronous design)
– 2) Design hazard-free circuits: sometimes necessary (clock not used –
asynchronous design)

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Types of Hazards
• Static 1-hazard
– Input change causes output to go from 1 to 0 to 1
1 1
0
• Static 0-hazard
– INput change causes output to go from 0 to 1 to 0
1
0 0
• Dynamic hazards
– Input change causes a double change
from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0
1 1
0 0

1 1
0 0
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 Static-1 Hazard

A static-1 hazard is a set of two input combinations Xa and Xb

such that:

(i) Xa and Xb differ in only one input variable;

(ii) both Xa and Xb produce a 1 output;

but it is possible for a momentary 0 to appear in the

output when the input transits from Xa to Xb or from
Xb to Xa

i.e., a static-1 hazard is a possibility of a 0 glitch when

we expect a steady 1 output.
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 Static-0 Hazard

A static-0 hazard is a set of two input combinations Xa and Xb

such that:

(i) Xa and Xb differ in only one input variable;

(ii) both Xa and Xb produce a 0 output;

but it is possible for a momentary 1 to appear in the

output when the input transits from Xa to Xb or from
Xb to Xa

i.e., a static-0 is a possibility of a 1 glitch when we expect

a steady 0 output.
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 Example
1 Does this circuit have a hazard?
X XZ’ If so, of what kind?
Z’ 0→1
1→0
Z
0 →1 F
1→0 →1
YZ
1 1 →0
Y The hazard occurs in the transition
from X,Y,Z = 111 to X,Y,Z = 110

Z
Z’
YZ
XZ’
F

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 Static Hazards in
Karnaugh Maps
X

Z F

F = X•Z’ + Y•Z
X
How can we identify a static-1 hazard
1 1 in this Karnaugh map?

Z 1 1 Two adjacent 1’s that are not in the

same term cause a static-1 hazard.
Y

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 Static Hazards in
Karnaugh Maps
X

Z F

F = X•Z’ + Y•Z
X
How can we eliminate the hazard?
1 1
Z 1 1 We can add one extra term to F.

Y F = X•Z’ + Y•Z + X•Y

X•Y

Consensus Term
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 Static Hazards in
Karnaugh Maps
X

Z F

X F = X•Z’ + Y•Z
X
How can we eliminate the hazard?
1 1
Z 1 1 We can add one extra term to F.

Y F = X•Z’ + Y•Z + X•Y

X•Y

Consensus Term
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Static Hazards
• Due to a literal and its complement momentarily
taking on the same value
– Thru different paths with different delays and converging
• May cause an output that should have stayed at
the same value to momentarily take on the wrong
value
• Example:
A
A
S B
F
S

B S'

F
S'
hazard
static-0 hazard static-1 hazard
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 Another Example
W W

1 11 1 1 1 1
1 1 1 1 1 1
Z Z
1 1 1 1 1 1
Y Y
1 1 1 1 1 1

X X
F = W’•Z + X•Z’ + X’•W F = W’•Z + X•Z’ + X’•W

1. Write minimal form for F

2. Identify static-1 hazards
3. Eliminate static-1 hazards

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 Another Example
W W

1 1 1 1 1 1
1 1 1 1 1 1
Z Z
1 1 1 1 1 1
Y Y
1 1 1 1 1 1

X X
F = W’•Z + X•Z’ + X’•W F = W’•Z + X•Z’ + X’•W + X•W’

1. Write minimal form for F

2. Identify static-1 hazards
3. Eliminate static-1 hazards

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 Another Example
W W

1 11 1 1 1 1
1 1 1 1 1 1
Z Z
1 1 1 1 1 1
Y Y
1 1 1 1 1 1

X X
F = W’•Z + X•Z’ + X’•W F = W’•Z + X•Z’ + X’•W + X•W’ + W•Z’

1. Write minimal form for F

2. Identify static-1 hazards
3. Eliminate static-1 hazards

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 Another Example
W W

1 1 1 1 1 1
1 1 1 1 1 1
Z Z
1 1 1 1 1 1
Y Y
1 1 1 1 1 1

X X
F = W’•Z + X•Z’ + X’•W F = W’•Z + X•Z’ + X’•W + X•W’ + W•Z’ + X’•Z

1. Write minimal form for F

2. Identify static-1 hazards
3. Eliminate static-1 hazards

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 Dynamic Hazards

A dynamic hazard is the possibility of an output

changing more than once as the result of a single
transition.

Dynamic hazards exist when there are multiple paths

with different delays from the changing input to the
changing output.

Dynamic hazards do not occur in properly designed

two level AND-OR or OR-AND circuits.

PS: A two level AND-OR or OR-AND circuit is

properly design if a variable and its complement are
never input to the same first level gate.
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Dynamic Hazard Example

0
W 0
0 slow
X

0 0
Y 1 1
1 1

1
1
1 1
Z

slower

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Dynamic Hazard Example

0
W 0 →1
0 →1 slow
X

0 0 →1→0
Y 1→0 1 →0 →1
1→0 1 →0 →0

1→0
1
1 1
Z

slower A dynamic hazard occurs when

oscilation may occur when a single
transition is expected.
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Dynamic Hazards
• Due to the same versions of a literal taking on
opposite values
– Thru different paths with different delays and reconverging
• May cause an output that was to change value to
change 3 times instead of once
• Example:
A

C
A
F B1
3
B 2
B2
1
B3
C
F

hazard
dynamic hazards
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Dynamic Hazards
u
A F
B
t v w

B
C

w
 Eliminating Static Hazards

• Following 2-level logic function has a hazard, e.g.,

when inputs change from ABCD = 0101 to 1101
A
AB
CD 00 01 11 10 A 1 A
1
1
G1 1 G1
\C \C 1
00 0 0 1 1 1 1 1
G3 F G3 F
\A 0 \A 0
G2 G2
D 0 D 0
01 1 1 1 1 0 0
D ABCD = 1100 ABCD = 1101
11 1 1 0 0
No Glitch in this case
C
10 0 0 0 0 This is the fix
B Glitch in this case
1 0 0
A 1 A 0 A 0
G1 G1 G1
\C \C 0 \C 1
1 1 1 1
G3 F G3 F G3 F
\A 0 \A 0 \A 1
G2 G2 G2
D 0 D 0 D 1
1 1 1
ABCD = 1101 ABCD = 0101 (A is still 0) ABCD = 0101 (A is 1)
 Eliminating Dynamic Hazards

• Very difficult!
• A circuit that is
static hazard free
1 01
\A
G1 can still have
B
01 dynamic hazards
Slow G3
1 01
\B 1 0
1 01 0
• Best approach:
\C G2
1 10 G5 F – Design critical
circuits to be two
0
A 10 level and eliminate all
\B G4
static hazards
10
V ery slow – OR, use good
clocked synchronous
design style

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Our old friend…
• Parallel to Serial Converter

• No “protocol” between FF’s

• Every cycle they all move together
• Delays, rates, communication all designed together.

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Summary
• All gates have delays
– RC delay in driving the output
• Wires are distributed RCs
– Delays goes with the square of the length
• Source circuits determines strength
– Serial vs parallel
• Delays in combinational logic determine by
– Input delay
– Path length
– Delay of each gate along the path
– Worst case over all possible input-outputs
• Setup and CLK-Q determined by the two latches in flipflop
• Clock cycle : Tcycle  TCL+Tsetup+Tclk→Q + worst case skew

• Delays can introduce glitches in combinational logic

• Subsystems glued together via protocols
– Delays, rates, design partitioning

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