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CPE304 ComputerArchitecture 1

The document discusses the topics of computer architecture including digital logic circuits, virtual circuit simulators, registers, memory, data transfer, operations, and basic computer design. It provides details on logic gates, Boolean algebra, decoders, encoders, multiplexers, comparators and their workings.

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0% found this document useful (0 votes)
23 views38 pages

CPE304 ComputerArchitecture 1

The document discusses the topics of computer architecture including digital logic circuits, virtual circuit simulators, registers, memory, data transfer, operations, and basic computer design. It provides details on logic gates, Boolean algebra, decoders, encoders, multiplexers, comparators and their workings.

Uploaded by

Hasbiy Robbiy
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CPE304 Computer Architecture

Asst. Prof. Mehmet Zahid YILDIRIM


Topics

 Digital Logic Circuits


 Virtual Circuit Simulators (Logisim)
 Register Structure
 Memory Structure
 Data Transfer Between Registers
 Memory, Arithmetic, Logic and Shift Operations
 Input/Output and Interrupt Operations
 Basic Computer Design
 Basic Computer Programming
Introduction

 Microcomputer is a structure consisting of microprocessor, memory and input/output


elements. The microprocessor works as the central processing unit of the microcomputer.
The microprocessor performs the function of decoding the program instruction codes by
fetching them from the memory and reflecting them to the input/output units by running
them.
Introduction

 The architectural structure of a microprocessor


in its simplest form;

Registers
Arithmetic-Logic Unit (ALU)
Timing and Control Unit
Introduction

 Registers: These are the units where the data is kept temporarily during
the processing of the raw information coming into the processor.

 Arithmetic-Logic Unit: ALU is the unit in the microprocessor where


numerical operations are performed. All Arithmetic (Addition,
Subtraction, Multiplication and Division) and Logical (And, Or, Exor, Not
etc.) operations are performed within this unit and under the control of
the control unit.

 Timing and Control Unit: This unit consists of two parts.

Timing Control: The processor receives input from an external clock signal
generating unit and converts this signal into time signals to create the time
signals necessary for the system to work.

Control Unit: In this section, the code coming into the processor is decoded
and control signals are generated for the necessary operations. Then, with
these signals, it is provided to be operated in the specified order according to
the instruction set. This is the part where the operation of the system is
controlled.
Introduction

 Computer architecture deals with the design of units such as memory, ALU, registers, I/O
unit, bus interface, control unit, learning the working principles, how operations such as
moving data between these units and programming these units.
Virtual Circuit Simulators
 Digital circuit simulators are used to learn
computer architecture. These simulators allow
us to simulate down to the smallest elements
of the basic microprocessor structure. Thanks
to these simulations, great savings are
achieved both in cost and time in the
formation of new designs. There are also
difficulties in finding faults and malfunctions in
systems created without simulation. By
simulating the system design, necessary
changes are easily made.
 Logisim will be used as a virtual circuit
simulator in the course. Logisim is an
educational tool for designing and simulating
digital logic circuits. With its simple toolbar
interface and simulation of the circuits you
build, it's simple enough to make it easy to
learn the most basic concepts connected to
logic circuits.
Digital Logic Circuits
Logic Gates

 The smallest units that make up digital


logic circuits are Logic Gates. These
gates are produced using electronic
elements such as resistors, transistors,
and diodes. In the market, these gate
circuits are produced as integrated.
Digital Logic Circuits
Boolean Algebra

 Boolean algebra is important in the


design of digital circuits. Circuit
diagrams of functions expressed in
Boolean algebra can be drawn using
logic gates.
Digital Logic Circuits
Features of Boolean Algebra

• X+0=X • X.0=0
• X+1=1 • X.1=X
• X+X=X • X.X=X
• X + X’ = 1 • X . X’ = 0
• X+Y=Y+X • XY = YX
• X + (Y + Z) = (X + Y) + Z • X (YZ) = (XY) Z
• X (Y + Z) = XY + XZ • X+YZ = (X + Y) + (X + Z)
• (X + Y)’ = X’Y’ • (XY)’ = X’ + Y’
• (X’)’ = X
Digital Logic Circuits
Boolean Algebra

 Samples
F = ABC + ABC’ + A’C (1)
= AB(C + C’) + A’C (2)
= AB • 1 + A’C
= AB + A’C (3)
 Example of a logic problem

The key to a bank's safe is held by the manager, the cashier and the assistant.
In order for the safe to be opened, at least one of the manager, the cashier and
the assistant must be present. Design the necessary logic circuit.
Digital Logic Circuits
Decoders

 In digital systems, information is defined by binary codes. Up to 2n different states can be


defined with an n-bit binary code. A decoder is a combined circuit that converts binary
information from n input lines into a maximum of 2n different output lines. If a decoder
has n inputs, it has as many as 2n outputs. The decoder output will be less than 2n if there
are unused or ignored situations.
 A two-bit decoder has 2 inputs and 4 outputs. For such a circuit, only one output will be
correct, depending on the state of the inputs. Below are the truth table, Logic diagram
and symbol of the 2x4 Decoder.
Digital Logic Circuits
Decoders

 In a three-bit decoder, three inputs are


decoded to produce eight outputs. Each
output is defined by a minimum term of
these three input variables. Only one output
is correct, depending on the state of the
inputs
Digital Logic Circuits
Decoders with Enable

 Most, if not all, of decoders contain one or


more enable entries. The decoder performs
the decoding process only when it is
authorized (Logic-1 or Logic-0 coming to the
enable input). In all other cases, the decoder
outputs are either Logic-1 or Logic-0.
 Note: Authorization can also be Logic-1 or
Logic-0 depending on the decoder feature
being worked on. The truth table of the 3x8
Decoder authorized in Logic-0 is given in the
figure.
Digital Logic Circuits
Decoders with Enable

 The truth table and logic symbol of 4514 integrated 4x16 Decoder with authorization input are given
below. Inhibit (INH) is the authorization entry for the Decoder. If this input is not pulled to Logic-1,
decoding is not performed, and all outputs become Logic-0. An external input, Strobe (ST), commands
a Latch (Latch-Data holder) in the circuit. If this input is not pulled to Logic-1, the old state will be
preserved regardless of the change in other inputs (D, C, B, A).
Digital Logic Circuits
BCD to Decimal Decoders
 The BCD code is a code defined by writing the 4-Bit Binary
equivalents of the Decimal numbers between 0 and 9. In this case,
the decoder to be designed should have 4 input lines and 10 output
lines since the BCD code is defined between 0-9 Decimal numbers.
The remaining cases will be defined as don't care.
Digital Logic Circuits
BCD to Seven Segment Decoders

 With the proper connection of seven separate


LEDs, we can display the numbers 0-9. The circuit
element that performs this operation is called a
seven-segment display. It can be common anode
or common cathode according to display led
connections.
Digital Logic Circuits
Encoders

 Encoders do the reverse operation of the decoder circuit. These circuits transform
information in decimal or known classical shapes into a form that digital circuits can
operate. An encoder produces 2n (or less) input lines and n output lines.
Digital Logic Circuits
Decimal to BCD Encoder

 Decimal to BCD encodes the decimal information in the encoder input and displays the
BCD code equivalent on four outputs. The 10x4 encoder logic symbol and truth table
are given below.
Digital Logic Circuits
Decimal to BCD Encoder

 If we want to write the outputs from the logic expression truth table;
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
Digital Logic Circuits
Multiplexers

 Multiplexing means that a large number of information is transmitted over a smaller number of
channels or lines. A digital multiplexer is a combined circuit that selects binary information from
one of many input lines and routes it to a single output line. Selection of a particular input is
controlled by a series of select lines. If there are 2n input lines for a multiplexer, there are n select
lines that determine which input is selected.
Digital Logic Circuits
Multiplexers

 In some cases, as with decoders, multiplexers may have an enable entry that controls operation.
Multiplexers perform multiplexing only when authorized. The authorization input is used to
combine two or more Multiplexes to obtain a digital multiplexer with more inputs. The truth
table and logic symbol of the 4051, which is a Multilexer with authorization input, are given
below. The authorization entry is named Inhibit (INH).
Digital Logic Circuits
Demultiplexers

 Demultiplexers (Information Distributor) is a circuit that receives information from a single line
and transmits this information over one of the possible 2n output lines. The selection of a
particular output line is controlled by the states of up to n output lines.

 Below is the truth table and logic symbol of a DEMUX with two select lines and four output lines.
Digital Logic Circuits
Comparators

 The comparison process is the determination of whether one of the numerical information in the input
is greater, less than or equal to the other.

 The most basic comparator circuits are Exclusive-Or (Xor) gates. When the inputs of a Xor gate are
different, the output is Logic-1, while the inputs are the same, the output is Logic-0. The figure shows
the basic comparison process with the Xor gate.

 With the Xor gate, it is seen whether the two bits of information in its inputs are equal. However, a
comparator is expected to show the case of equality as well as the case of small or large information.
Digital Logic Circuits
Comparators

 Example: At the end of this comparison, which compares one bit of A and B data, design the
circuit that shows the states A > B, A = B, A < B.

 The truth table for the circuit will be as follows. If the outputs are written with the help of the
truth table;

 With such a circuit, two one-bit data A > B, A = B, A < B states will be determined.
Digital Logic Circuits
Comparators

 The Logic diagram and symbol of the one-bit comparator are given below.
Digital Logic Circuits
Arithmetic Units

 Digital circuits that perform arithmetic operations such as addition, subtraction, multiplication
and division are called arithmetic circuits. The basic arithmetic operations in numerical systems
are addition and subtraction. Multiplication is defined by repeated addition, and division by
repeated subtraction.
Digital Logic Circuits
Adders

 Circuits that perform addition for digital circuits are called adders. Below are the basic rules for
the sum of binary numbers.

Note: It should be noted that the carry formed at the end of the addition operation is the highest
value digit of the transaction result.
Digital Logic Circuits
Half Adder

 Circuits that add two bits of data are called half adders. A half adder has two inputs for two one-
bit data inputs and two outputs for displaying the sum and the carry hand.

 If we name two one-bit data with P and Q, the circuit to be designed is requested to perform the
addition of two binary numbers. For the representation of the addition operation, there must be
two outputs, the result (Sum -S) and the carry (Carry -C).
Digital Logic Circuits
Half Adder

 If we write the outputs with the help of the truth table;

Note: When obtaining the Logic expression for the outputs, it should be seen that the minimum term
for each output is written.

 The logic diagram and symbol of a half adder are given below.
Digital Logic Circuits
Full Adder

 The second basic type of adder circuits is called full adder. They are circuits that perform the
collection of three-bit data. The circuit has three inputs for addition and two outputs for the
display of the result. Two of the entries show the two data to be added, while the other entry is
for the hand entry consisting of low-value digits. The truth table of a full adder is given below;

In the truth table;

 Cin – carry from previous operation.


 Cout – shows the carry that occurs after
the collection process.
Digital Logic Circuits
Full Adder
 The logic diagram and symbol of a full adder is given below;

 A full adder circuit using two half adders and an external OR gate;
Digital Logic Circuits
Parallel Adders

 An n-bit parallel adder can be obtained by connecting n full adders in parallel. The carry output
(Cout) of each full adder is connected to the carry input of the higher value adder. Thus, the next
sum of the carry (Cout) consisting of the sum of the low-order digits will affect the digits to be
made.
Digital Logic Circuits
2-bit Parallel Adders

 With such a circuit, two-bit data add up. Two full adders are needed to add two bits of data. The
sum operation will start with the sum of the low-order bits. The carry consisting of this sum (0 or
1) must be added to the next addition. Let's explain the process with the collection of two-bit P
and Q data;

 The two-bit parallel adder circuit and its symbol obtained by connecting two full adders in parallel
are given below. The highest digit of the carry addition result, which is the sum of the highest-
order bits.
Digital Logic Circuits
2-bit Parallel Adders

 Block diagram of the circuit;


Digital Logic Circuits
4-bit Parallel Adders

 The block diagram and symbol of a four-bit parallel adder are given below. For addition, the
lowest-order bits are applied to the rightmost full adder inputs first. The carry outputs (Cout) of
all full adders are connected to the carry inputs (Cin) of the full adder on which the next addition
will be made.
Digital Logic Circuits
4-bit Parallel Adders

 Example:

Use two 7482 Two-bit parallel adders to obtain a Four-bit parallel adder. Solution: Obtaining a four-
bit parallel adder using two 7482s is shown in the figure. The two low-order bits are collected at the
first parallel adder inputs. The sum of the two high-order bits is performed in the second parallel
adder. The carry consisting of this sum becomes the highest digit of the addition.

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