Serial Communication

Basics of serial communication

Parallel: expensive - short distance – fast
Serial :cheaper– long (two different cities by modem)-slow
Basics of serial communication
 Start and stop bits
When there is no transfer the signal is high
Transmission begins with a start (low) bit
LSB first
Finally 1 stop bit (high)
Data transfer rate (baud rate) is stated in bps
bps: bit per second
 Errors During Data Transmission
Types of Errors
The two or more bits are
changed from 0 to 1 or
from 1 to 0 is known as
Burst Error.

The only one bit of a given data unit is

changed from 1 to 0 or from 0 to 1.
 Error Detecting Techniques:

The most popular Error Detecting Techniques are:

•Single parity check
•Two-dimensional parity check
•Checksum
•Cyclic redundancy check
 Single Parity Check
•Single Parity checking is the simple mechanism and inexpensive to detect the errors.
• A parity bit which is appended at the end of the data unit so that the number of 1s becomes even. Therefore,
the total number of transmitted bits would be 9 bits.
•At the receiving end, the parity bit is calculated from the received data bits and compared with the received
parity bit.
•This technique generates the total number of 1s even, so it is known as even-parity checking.

Drawbacks Of Single Parity Checking

•It can only detect single-bit errors which are very
rare.
•If two bits are interchanged, then it cannot detect
the errors.
 Two-Dimensional Parity Check

•Performance can be improved by using Two-

Dimensional Parity Check which organizes
the data in the form of a table.
•Parity check bits are computed for each row,
which is equivalent to the single-parity check.
•In Two-Dimensional Parity check, a block of
bits is divided into rows, and the redundant
row of bits is added to the whole block.
•At the receiving end, the parity bits are
compared with the parity bits computed from
the received data.

Drawbacks Of 2D Parity Check

•If two bits in one data unit are corrupted and two bits exactly the same position in another
data unit are also corrupted, then 2D Parity checker will not be able to detect the error.
•This technique cannot be used to detect the 4-bit errors or more in some cases.
 Checksum
A Checksum is an error detection technique based on the concept of redundancy.
It is divided into two parts:
Checksum Generator and Checker
A Checksum is generated at the sending side. Checksum generator subdivides the data into equal
segments of n bits each, and all these segments are added together by using one's complement
arithmetic. The sum is complemented and appended to the original data, known as checksum field.
The extended data is transmitted across the network.
 The Sender follows the given steps:
1. The block unit is divided into k sections, and each of n bits.
2. All the k sections are added together by using one's complement to get the sum.
3. The sum is complemented and it becomes the checksum field.
4. The original data and checksum field are sent across the network.

Checksum Checker
A Checksum is verified at the receiving side. The receiver subdivides the incoming data
into equal segments of n bits each, and all these segments are added together, and then
this sum is complemented. If the complement of the sum is zero, then the data is
accepted otherwise data is rejected.

The Receiver follows the given steps:

1. The block unit is divided into k sections and each of n bits.
2. All the k sections are added together by using one's complement algorithm to get the sum.
3. The sum is complemented.
4. If the result of the sum is zero, then the data is accepted otherwise the data is discarded.
 Cyclic Redundancy Check (CRC)
CRC is a redundancy error technique used to determine the error.
 Following are the steps used in CRC for error detection:
•In CRC technique, a string of n 0s is appended to the data unit, and this
n number is less than the number of bits in a predetermined number,
known as division which is n+1 bits.
•Secondly, the newly extended data is divided by a divisor using a process
is known as binary division. The remainder generated from this division
is known as CRC remainder.
•Thirdly, the CRC remainder replaces the appended 0s at the end of the
original data. This newly generated unit is sent to the receiver.
•The receiver receives the data followed by the CRC remainder. The
receiver will treat this whole unit as a single unit, and it is divided by the
same divisor that was used to find the CRC remainder.
If the resultant of this division is zero which means that it has no error,
and the data is accepted.
If the resultant of this division is not zero which means that the data
consists of an error. Therefore, the data is discarded.
Serial port block diagram
Parallel in Serial Out (Transmitter)
Serial in Parallel Out (Receiver)
 Serial control (SCON) Register

SM0 SM1 SM2 REN TB8 RB8 TI RI

SM0 (SCON.7) : mode specifier

SM1 (SCON.6) : mode specifier
SM2 (SCON.5) : used for multi processor communication
REN (SCON.4) : receive enable (by software enable/disable)
TB8 (SCON.3) : transmit bit8
RB8 (SCON.2) : receive bit 8
TI (SCON.1) : transmit interrupt flag set by HW clear by SW
RI (SCON.0) : receive interrupt flag set by HW clear by SW
 Mode of operation

SM0 SM1 MODE Operation Transmit rate

0 0 0 shift register fixed (xtal/12)
0 1 1 8 bit UART variable (timer1)
1 0 2 9 bit UART fixed (xtal/32 or xtal/64)
1 1 3 9 bit UART variable (timer1)
 Mode of operation
• Mode 0 :
• Serial data enters and exits through RxD
• TxD outputs the shift clock.
• 8 bits are transmitted/received(LSB first)
• The baud rate is fixed a 1/12 the oscillator
frequency.

8051
• Application
TXD clk
• Port expansion RXD data
Shift register
 Mode of operation
• Mode 1
• Ten bits are transmitted (through TxD) or received (through RxD)
• A start bit (0), 8 data bits (LSB first), and a stop bit (1)
• On receive, the stop bit goes into RB8 in SCON
• the baud rate is determined by the Timer 1 overflow rate.
• Timer1 clock is 1/32 machine cycle (MC=1/12 XTAL)
• Timer clock can be programmed as 1/16 of machine cycle
• Transmission is initiated by any instruction that uses SBUF as a
destination register.
Mode of operation
 Mode of operation
• Mode 2 :
• Eleven bits are transmitted (through TxD), received (through RxD)
• A start bit (0)
• 8 data bits (LSB first)
• A programmable 9th data bit
• and a stop bit (1)
• On transmit, the 9th bit (TB8) can be assigned 0 or 1.
• On receive, the 9the data bit goes into RB8 in SCON.
• the 9th can be parity bit
• The baud rate is programmable to 1/32 or 1/64 the oscillator frequency in
Mode 2 by SMOD bit in PCON register

• Mode 3
• Same as mode 2
• But may have a variable baud rate generated from Timer 1.
What is SMOD
 Bit 7 of PCON register
 If SMOD=1 double baud rate
 PCON is not bit addressable
 How to set SMOD
MOV A, PCON
SETB A.7
MOV PCON,A
 How to communicate 8051 to PC
 Connect TXD to RXD and RXD to TXD from pc to 8051
 Use max232 to transform signal from TTL level to RS232 level
 The baud rate of the 8051 must matched the baud rate of the pc
 PC standard baud rate
 2400-4800-9600-14400-19200-28800-33600-57600
 Serial mode 1 is used
 Timer 1 is used
 The 8051 UART divides the machine cycle frequency by 32
 Machine cycle is 1/12 XTAL frequency
 We use timer1 in mode 2 (auto reload)
 See example 10-1
 RxD and TxD pins in the 8051
• TxD pin 11 of the 8051 (P3.1)
• RxD pin 10 of the 8051 (P3.0)

SBUF register
MOV SBUF,#’D’ ;load SBUF=44H, ASCII for ‘D’
MOV SBUF,A ;copy accumulator into SBUF
MOV A,SBUF ;copy SBUF into accumulator
MAX232
 Power control
• Controlling Power Consumption
• Two power reducing modes Power control register PCON
 Idle
 Power down
 Idle mode
• An instruction that sets PCON.0 causes Idle mode
Last instruction executed before going into the Idle mode
the internal CPU clock is gated off
Interrupt, Timer, and Serial Port functions act normally.
All of registers, ports and internal RAM maintain their data during
Idle
ALE and PSEN hold at logic high levels
• Any interrupt
• will cause PCON.0 to be cleared by HW (terminate Idle mode)
• then execute ISR
• with RETI return and execute next instruction after Idle instruction.
• RST signal clears the IDL bit directly
 Power-Down Mode
An instruction that sets PCON.1 causes power-dowm mode

Last instruction executed before going into the power down mode

the on-chip oscillator is stopped.

all functions are stopped, the contents of the on-chip RAM and
Special Function Registers are maintained.

The ALE and PSEN output are held low

The reset that terminates Power Down

 Power control example

Org 0000h
Ljmp main

Org 0003h
Orl pcon,#02h ;power down mode
Reti

Org 0030h
Main:
……
……
……
Orl pcon,#01h ;Idle mode
end