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Sequential Function Chart to Function Block Diagram Transformation with

Explicit State Representation

Chapter · January 2020

DOI: 10.1007/978-3-030-30604-5_10

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 Sequential Function Chart to Function Block
Diagram Transformation With Explicit State
Representation

Maciej Hojda, Grzegorz Filcek, and Grzegorz Popek

Faculty of Computer Science and Management,

Wroclaw University of Science and Technology,
Ignacego Lukasiewicza 5, 50-371 Wroclaw, Poland
{maciej.hojda,grzegorz.filcek,grzegorz.popek}@pwr.edu.pl

Abstract. This paper presents a method and a tool for converting Se-
quential Function Charts into Function Block Diagrams in a manner that
models states with the use of flip-flops. Order of evaluation is enforced
through the use of explicit delays. Presented approach can be used when
SFC programming is not directly available but the developer wants to
use advantages of SFC modeling such as robust analysis tools.

Keywords: Sequential Function Chart, Function Block Diagram, Pro-

grammable Logic Controller

1 Introduction

Programmable Logic Controllers (PLCs) are microcontroller-based devices used

predominantly in industrial applications. PLCs serve to execute control algo-
rithms by providing current, either directly or indirectly, to the machines of the
floor shop. Distinct advantage of PLCs over hard-wired circuits is their pro-
grammability. Control algorithms can be modified as needed and feedback from
the PLC to the supervisory workstation permits on-the-fly adjustments. Com-
pared to the other types of digital controllers, PLCs are also lauded as more
suited to working in harsh environmental conditions such as high humidity, ex-
treme temperatures and harmful vibrations. Use of PLCs has steadily grown
over the past few decades as hardware solutions and programming practices
developed side by side. Presently, standard PLC programming languages are
formalized in the IEC 61131-3 norm [9]. Of the five languages defined therein,
the Sequential Function Chart (SFC) is the one best suited for high-level design
and analysis [6, 18, 11].
SFC retains structural similarity to its originator (through Grafcet), the Petri
net. Consequently, a Petri net structure can be transformed, with some effort,
into a corresponding SFC [5, 15]. The inverse transformation is also possible [7].
The ability to alternate between the two representations makes it possible for
SFC programmers to benefit from the methods of analysis and design common
2 Maciej Hojda, Grzegorz Filcek, Grzegorz Popek

to Petri nets. Additional modeling facilities are available through the application
of Timed Automata [13], Symbolic Model Verifiers [3] and others [2].
Typically, SFC is used in conjunction with supplementary languages defined
in IEC 61131-3 such as Structured Text (ST) or Function Block Diagram (FBD).
The more complex the supplementary constructs are, the less descriptive power
does the SFC itself have. To efficiently use the design and analysis tools limited
to SFCs, it is crucial to keep the charts as pure as possible. To accomplish that,
one should use SFC as the primary programming methodology and transform
it to other languages as necessary. However, direct SFC programming might be
unavailable on the given platform. A method for conversion to other languages is
then invaluable. This paper introduces a method of transforming SFC into FBD
and a software implementing it. The main idea of the method is to represent
states defined by SFC with the use of flip-flops and to enforce the order of
block evaluation with the use of explicit delays. Specific conversion methods are
provided for all the common structures defined within the SFC language.
The paper is divided into five sections. This introduction is followed by a
description of ST, FBD and SFC in the second section. Related works and mo-
tivation are presented shortly after. The transformation method is described in
the third section and the software in the fourth one. The paper is then concluded
in the final section.

2 PLC programming – IEC 61131-3

In 1993, the International Electrotechnical Commission developed a set of guide-

lines for PLC programming [8, 11]. This document, named IEC 61131-3, has been
steadily updated (version 3 is now available [9]) and is a de-facto standard of
PLC programming that the majority of PLC producing companies adhere to, in
some measure at least.
The document defines, amongst others, programming languages available to
a PLC programmer. They are: Instruction List (IL), Structured Text (ST), Lad-
der Diagram (LD), Function Block Diagram (FBD) and Sequential Function
Chart (SFC). Of the five, the SFC is the most general, providing tools for or-
ganizing large portions of code into smaller, possibly nested parts. The FBD
provides an input-output based control logic. Finally, ST provides convenient
textual representation of common operations such as variable modification or
expression evaluation. Three of the five languages – ST, FBD and SFC – are
briefly explained.

2.1 Structured Text

Typical Structured Text program consists of statements such as variable as-

signments or variable evaluations (Fig. 1). The statements also include common
programming structures including function calls, selections, loops and logic or
arithmetic expressions.
 Sequential Function Chart to Function Block Diagram ... 3

V := A + (B * C) MOD 5;
W := A_FUNCTION(1, 2, 3) + V;

Fig. 1: Structured Text example – an arithmetic expression is assigned to variable V

then added to the result of a function and assigned to W

2.2 Function Block Diagram

As a legacy of signal processing, Function Block Diagrams are best suited to

represent input-output operations where signals, either binary or analog, traverse
across the FBD structure (Fig. 2). The elements of an FBD diagram are input-
output blocks and connections between them.

Fig. 2: Function Block Diagram example – binary output Q1 is set if A1 > A2 and an
RS flip-flop is set (input I1 sets, I2 resets)

2.3 Sequential Function Chart

The concept behind Sequential Function Charts is to permit simplifying com-

plex programs through decomposition into smaller parts. SFC contains four main
types of elements: states, transitions, actions and parallel branches (Fig. 3). A
state is given by its name and connected to some (or all, or none) other states
with the use of transitions. A single state is selected as the starting state. Some
states are connected to underlying actions. Actions can range from setting out-
puts, through making calculations, to executing large portions of the program.
Transitions connecting states have conditions assigned to them. The conditions
have the form of expressions combining logical values of inputs, outputs or struc-
tures in another PLC language.
Each action has a qualifier that determines the conditions of its execution. By
default, a Non-stored (N) action guarantees continuous execution of the action,
as long as the state is active. Other qualifiers affect the execution time or the
permanency of the action, ex. Pulse (P) executes the action once, while Delay
(D#t10s) delays the activation (here by 10 seconds). Finally, parallel indicators
mark concurrent execution.
Execution of an SFC application can be simulated by placing a single token
in the starting state. Tokens represent the states which are active, i.e. actions
connected to the states are under execution. When a condition of a transition
leaving an active state is satisfied, the state becomes inactive and another state,
one indicated by this transition, becomes active instead. Token is then moved to
the new active state. Parallel branches multiply tokens and parallel convergences
4 Maciej Hojda, Grzegorz Filcek, Grzegorz Popek

merge them. If one enters a parallel block, all the states following the block are
executed concurrently.

Fig. 3: Sequential Function Chart elements: a) initial state, b) state, c) transition,

d) action (q – qualifier), e) parallel branch

In Fig. 4 we have a sample SFC with two states and three actions. Signal
Execute.X is the step flag, set only when the step is active. All the common
SFC structures are provided in Fig. 5 and they are the subject of conversion.

Fig. 4: Sequential Function Chart example

Fig. 5: Sequential Function Chart strucutres: a) sequence, b) divergence with mutual

exclusion, c) divergence with priority, d) convergence of sequences, e) simultaneous
divergence, f) simultaneous convergence
 Sequential Function Chart to Function Block Diagram ... 5

A sequence represents a situation in which activation of transition X changes

the active state from A to B. While in state A, actions a are performed (b in
state B). In case of divergence with mutual exclusion, if state A is active, then
transition X enables state B while transition Y enables state C. SFC designer is
responsible for ensuring that X and Y are mutually exclusive. Divergence with
priority does not have this requirement and in the case both transitions are
active, the leftmost one is executed. Opposite of divergence is the convergence
of sequences, where C is the resulting state no matter if A or B was the originally
active state.
Last two structures provide means of concurrent execution. For the simul-
taneous divergence, if state A is active, then transition X activates both B and
C. In case of convergence, to activate state C, both A and C have to be active,
and transition X has to be enabled. All of the structures can be extended with
new states, i.e. sequence can be longer, divergences can split into more than two
states, convergences can join more than two states.

2.4 Related Work and Motivation

For many PLCs, all of the languages described in IEC 61131-3 are available.
However, there exists a numerous class of controllers for which that is not the
case. Software for the so-called Programmable Logic Relays (PLRs) – a variant
of PLCs with a small number of inputs and outputs – rarely permit direct use
of SFC diagrams, opting for the more basic choices such as FBD or LD. Ex-
amples of such PLRs (also called nano/pico-PLCs) and their programming soft-
ware include: Siemens LOGO! – LOGO! SoftComfort, Akytec PR200 – Akytec
ALP and Eaton easyE4 – EasySoft. Although simpler than many of their PLC
counterparts, PLRs see widespread use in domestic automation [10], industrial
automation [17] and other control tasks [1].
To facilitate the use of languages that are not directly available, various
methods of conversion were developed. Transformation between SFC and LD has
been documented in [19], whereas an algorithm for the inverse transformation
can be found in [14]. Multiple transformations: SFC to ST, FBD to IL and LD to
IL are presented in [4]. Other conversion methods, including those for languages
outside of the scope of IEC 61131-3, are also available [12].
A method converting SFC to FBD was presented by Wciślik in [20]. The
authors useflip-flops to represent SFC states in FBD diagrams. Change of state
is performed by setting and resetting selected flip-flops. The result is a single-
network FBD representing the original SFC. While this method can be applied
to many SFC diagrams, it does not specify the order of block evaluation of the
resulting FBD. This can lead to issues that require additional work to ensure
the resulting FBD provides results as desired.
The conversion method presented in this paper is closely related to the one
presented by Wciślik. To represent states, we also use S-dominant flip-flops. Our
approach forces the order of evaluation through the use of delays. Namely, if a
state is active and an outgoing transition is enabled, then the change of state
will occur after a short, typically single-cycle, delay.
6 Maciej Hojda, Grzegorz Filcek, Grzegorz Popek

Without the delay, ambiguity can occur in situations when a block is simulta-
neously set and reset such as is the case when a convergence of sequences occurs
for two different branches of a simultaneous divergence (Fig. 6a). Explicit delays
are also necessary in some of the PLC programming software such as LOGO!
SoftComfort (single-cycle delaying flags needed for recursion).

Fig. 6: SFC artifacts: a) convergence of sequences in a simultaneous divergence,

b) self-loop

IEC 6113-3 states that ”clearing time of a transition [...] cannot be zero”.
To reflect this ambiguity, in our transformations we also provide two methods
of dealing with self-loops (Fig. 6b): with or without enforcing resetting of action
controller timers. Finally, our approach removes the need for a synchronization
block. This takes out the need to modify the SFC diagram in simultaneous
convergence (esp. in simultaneous convergence with a sequence selection) and
permits the use of any outgoing transition condition.

3 SFC to FBD conversion rules

The general idea of the method of conversion is to represent states as S-dominant

flip-flops. When the state becomes active, a Set operation is performed on the
flip-flop. When the state becomes inactive, a Reset operation follows. Transfor-
mation of actions is done with the use of a standard action controller (Fig. 7).
We assume that all the actions that are not already in the FBD form, can be
transformed into FBD. In the upcoming examples we give actions in ST.

Fig. 7: Action controller and the corresponding flip-flop for the Execute state in Fig. 4

Furthermore, we consider a single-network FBD where recurrence order is

enforced with the use of explicit delays (such as flags in LOGO!). Those blocks
serve as a memory between each evaluation – they delay their output (prefer-
 Sequential Function Chart to Function Block Diagram ... 7

ably by one cycle). Transition conditions and actions are given symbolically.
Flip-flops (RS) are named after the state they represent. Delay is given by δ.
Transformations of structures in Fig. 5 are shown in Fig. 8.

Fig. 8: FBD after conversion from SFC: a) sequence, b) divergence with mutual
exclusion, c) divergence with priority, d) convergence of sequences, e) simultaneous
divergence, f) simultaneous convergence, g) self-loop with timer reset
8 Maciej Hojda, Grzegorz Filcek, Grzegorz Popek

In the case of sequence, for each SFC state A and B a single flip-flop is created
RS(A) and RS(B) respectively. Action controllers a and b are connected directly
to flip-flops. Change of state occurs when both, RS(A) and X evaluate to truth,
then the delaying block δ is activated. After the delay, RS(A) is reset and RS(B)
is set. This concludes the change of state.
Divergence is converted with the use of one delay for every possible destina-
tion state. If RS(A) is set and either of the conditions X or Y is satisfied, then
the corresponding delay δ is activated. This, in turn, sets RS(B) or RS(C) and
resets RS(A). Divergence with priority ensures that transition to RS(B) executes
over transition to RS(C) if both transitions, X and Y are enabled. Convergence
to state C occurs when either RS(A) is set and X is enabled, or RS(B) is set and
Y is enabled.
Simultaneous divergence results in two enabled flip-flops. If RS(A) is set and
X is enabled then, after a short delay δ, RS(B) and RS(C) are set and RS(A) is
reset. Simultaneous convergence can only happen if all three: RS(A), RS(B) and
X are set.
Finally, we provide transformation conditions for a self-loop from Fig. 6b
when action controller timers require resetting. This is accomplished by using
two delays δ. First is used to reset RS(A) the second is used to set it again. For
a self-loop without timer reset, both delays are merged.

4 S2FC – a tool for automatic conversion

Prototype of the software for automatic conversion uses textual representation of

the SFC and FBD diagrams (see [11, 9]). The input file defines steps, transitions,
actions, while the output file contains function blocks. The software is written
in Python 3.6 with the use of standard Python libraries.
An example of conversion is given for a 3-step system presented in Fig. 9.
The system represents a control loop with a fixed number of iterations. After
initialization, the output q1 is set, for a period of time, whenever the user ac-
tivates the input i1. Fig. 10 shows the output FBD obtained with the use of
transformation rules.

Fig. 9: Control loop example SFC

 Sequential Function Chart to Function Block Diagram ... 9

Fig. 10: Control loop example FBD

5 Conclusions
Ability to quickly perform conversions of SFC into FBD allows for more control
over programming of PLCs. Presented transformation methodology allows for
easy flow control, and analysis of a program under execution. On-the-fly ad-
justments can be performed in order to modify the controller operation or to
eliminate design mistakes. Presented methodology is accessible to future exten-
sions such as multi-network FBDs. Included example illustrates the ease of use
of presented conversion rules. Further works will focus on including other PLC
programming languages in the conversion methodology.

References
1. Alnaib A., Altaee O., Al-jawady N.: PLC Controlled Multiple Stepper Motor Us-
ing Various Excitation Methods. In: proceedings of ICETA, 2018 International
Conference on Engineering Technologies and their Applications, pp. 54–59 (2018).
2. Bauer, N., et al.: Verification of PLC Programs Given as Sequential Function
Charts. In: Ehrig H. et al. (eds) Integration of Software Specification Techniques
for Applications in Engineering. Lecture Notes in Computer Science, vol 3147, pp.
517-540. Springer, Berlin, Heidelberg (2004).
3. Bornot, S., et al.: Verication of sequential function charts using SMV. In: pro-
ceedings of PDPTA, 2000 International Conference on Parallel and Distributed
Processing Techniques and Applications, pp. 2987-2993 (2000).
4. Darvas D., Majzik I., Viñuela E.: PLC Program Translation for Verification Pur-
poses. Periodica Polytechnia Electrical Engineering and Computer Science, vol.
62(2), pp. 151–165 (2017).
5. Dideban, A., Mohsen, K., Alla H.: Implementation of Petri Nets Based Controller
using SFC. Control Engineering and Applied Informatics, vol. 13(4), pp. 82-92
(2011).
 10 Maciej Hojda, Grzegorz Filcek, Grzegorz Popek

6. Fengyun H., Hao P., Ruifeng G.: Design of PLC Sequential Function Chart based
on IEC61131-3 standard. Applied Mechanics and Materials, vol. 325, pp. 1130-1134
(2013).
7. Fujino, K., et al.: Design and verification of the SFC program for sequential control.
Computers and Chemical Engineering, vol. 24, pp. 303-308 (2000).
8. International Electrotechnical Commision: IEC 61131-3 First edition. International
Standard. Programmable controllers – Part 3: Programming languages (1993).
http://www.iec.ch
9. International Electrotechnical Commision: IEC 61131-3 Edition 3.0. International
Standard. Programmable controllers – Part 3: Programming languages (2013).
http://www.iec.ch
10. Jarmuda T: A computer system for controlling temperature in a two-state mode
and by means of a PI controller in an “intelligent building”. Computer Applications
in Electrical Engineering, vol. 10, pp. 372–385 (2012).
11. Karl-Heinz, J., Tiegelkamp, M.: IEC 61131-3: Programming Industrial Automation
Systems. Springer, Berlin, Heidelberg (2001).
12. Kim H., Kwon W., Chang N.: Translation method for ladder diagram with applica-
tion to a manufacturing process. In proceedings of ICRA, 1999 IEEE International
Conference on Robotics and Automation, vol. 1, pp. 793-798 (1999).
13. L’Her, P. et al.: Proving sequential function chart programs using automata. LNCS,
vol. 1660, pp. 149-163 (1998).
14. Lopes V., Sousa M.: Algorithm and tool for LD to SFC conversion with state-space
method. In: proceedings of INDIN, 2017 IEEE 15th International Conference on
Industrial Informatics, pp. 565–570 (2017).
15. Mello, A., et al.: A Transcription Tool From Petri Net To Clp Programming Lan-
guages. ABCM Symposium Series in Mechatronics, vol. 5, pp. 781-790 (2012).
16. Peng, S., Zhou, M.: Design and Analysis of Sequential Function Charts Using
Sensor-Based Stage Petri Nets. In: proceedings of SMC, 2003 IEEE International
Conference on Systems, Man and Cybernetics. Conference Theme - System Secu-
rity and Assurance, pp. 4748-4753 (2003).
17. Sarac V.: Application of PLC Programming in Cost Efficient Industrial Process.
International Journal on Information Technologies & Security, vol. 1, pp. 69–78
(2016).
18. Tsukamoto T., Takahashi K.: Modeling of Elevator Control Logic Based on Mark
Flow Graph and Its Implementation on Programmable Logic Controller. In: pro-
ceedings of GCCE, 2014 IEEE 3rd Global Conference on Consumer Electronics,
pp. 599–600 (2014).
19. Wciślik M.: Programming of Sequential System in Ladder Diagram Language.
IFAC Proceedings Volumes, vol. 36(1), pp. 37-40 (2003).
20. Wciślik M., Suchenia K., askawski M.: Programming of sequential control systems
using functional block diagram language. IFAC-PapersOnLine, vol. 48(4), pp. 330-
335 (2015).

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