High Performance CMOS Buffer Amplifier with

Offset Cancellation
Fathi A. Farag
Electronics and Communications Dept., Faculty of Engineering,
Zagazig University, Zagazig. Egypt
[email protected]

Abstract--High performance CMOS buffer amplifier with offset should also provide low output impedance to increase the
cancellation is proposed. The new cell is based on negative bandwidth and minimize the losses in passband. The key
feedback technique; therefore it improves the proposed cell parameter here is the transconductance which should be
performance. The employed feedback enhances the overall increased to satisfy these requirements for the buffer. gm1 of
transconductance while minimizing the loading effect on the
the MOS transistor in saturation can be written as:
driving stage. The proposed cell can be used as a very high
bandwidth buffer with resistive and capacitive load. The offset
cancellation technique is achieved using level shifter based on
(2)
current process. The proposed approach can be easily using for
offset cancellation of the main analog blocks, such as operational
amplifier, Variable Gain Amplifier (VGA), ….etc. The proposed Where (W/L) is the aspect ratio of M1, IDQ is the DC
circuit is designed and simulated using 0.13µm CMOS process biasing current, and kn (µnCox)is the process parameter.
from IBM. The simulation results show bandwidth of 1.6GHz for
a 3pF capacitor and 50Ω resistor. The consumed power was GBW in Mhz

4.5mW which is reasonable for such large load comparing to a VDD 10

2

conventional source follower buffer and other approaches. M1

Key words: Buffer Amplifier, CMOS Analog Integrated Circuits, Low

Vin 1
10

Voltage, Wide Bandwidth. Vo

I. INTRODUCTION M2
10
0

CL
Recently, the deep submicron CMOS technology causing VB2

the capacitive load becomes highly significant in very large 10

-1

scale integration (VLSI) CMOS systems. Such a large

-2 -1 0 1 2
10 10 10 10 10
(W/L) 1

capacitive, the loading effect will be limiting the overall

bandwidth of the system. Therefore, the buffer circuit, driving (a).Circuit schematic. (b). GBW variation against (W/L)1.
this large capacitance, becomes a design issue due to the large Fig. 1. The conventional source follower buffer.
transconductance required. Moreover, in some situations,
circuits should have large fan-out. For these reasons, buffers In order to obtain large gm, it is required to increase the
are frequently used in analog and mixed signal circuits. Well- aspect ratio, and so the area, of the driving transistor M1.
designed buffers should drive large capacitive load with wide Consequently, the driving stage will be loaded by such
bandwidth, minimum power consumption, low distortion, and capacitance (CL=CLo+W1C'ox) of M1 and M2 lowering the
low loading effect with driving current capability. overall gain bandwidth product (GBW) of the circuit as shown
in Fig. 1(b). Alternatively, biasing current (VB2) can be
Basically, the source-follower buffer is shown in Fig.1(a). increased which will impact the power consumption as can be
The input/output relation is concluded from Fig. 1(b). Also, the increasing of IDQ effects on
the output dynamic range.
(1)
Many techniques have been published for the buffer
behaviour enhancement. The Flipped Voltage Follower
Where, and β = µCoxW/L. Also, vTM1, technique [1] had improved the total transconductance due to
the unity feedback as shown in Fig. 2(a). Also, the negative
µ, W, and L are the threshold voltage, mobility, width, and
feedback method has been employed [2] and the constant
length of M1, respectively. Then, , as long as the current driven with negative feedback technique [3, 4] for this
current in M1 is constant. The limited transconductance and reason. At low supply voltages, buffers lose their driving
output impedance effects on the bandwidth and the low capability, which degrades the overall circuit performance.
frequency gain. Therefore, transistor M1 should have large The floating gate transistor [5] has been used for the low
aspect ratio in order to provide the required gm of the buffer. It supply voltage ability.

978-1-4673-6195-8/13/$31.00 ©2013 IEEE

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 This paper proposes a new buffer circuit which improves increased, the output resistance becomes very small which
the transconductance without increasing the aspect ratio of the improves the CMOS buffer performance. Moreover, the
basic transistors. Alternatively, a negative feedback technique feedback helps to keep the current through M1 constant,
is employed to enhance gm and minimize the output resulting in voltage gain that can be expressed as:
impedance. In section II, the voltage gain buffer with current
driving capability is explained. Section III, the offset (4)
cancellation technique is proposed and realized. The
simulated results and the comparing to other approaches are
demonstrated in section IV. Finally, conclusions are reported Where, C2 is gate to drain capacitor of M2, goi is (1/rdsi) of
in section V. transistor Mi, (i=1,2,3) and CL is capacitive load at RL is
infinity. Assume, gm1>>go4 and C2 is very small, equation 4,
can be written as:

(5)

Where, Avo=(gm2rds3+1) is enhancement transconductance

factor due to the feedback. Then, the proposed buffer circuit
shown in Fig. 3 has achieved large transconductance without
increasing the aspect ratio of the main transistor M1. The
effective transconductance can be represented as in Eq. 6.
(a). (b).
Fig. 2 (a). Flipped voltage follower [1]. (b). CMOS buffer proposed in [ 3,4]. (6)
II. PROPOSED FEEDBACK BUFFER
Then, the overall transconductance is approximately
Traditionally, the buffer circuit achieves unity voltage improved. The overall bandwidth of the proposed circuit can
gain and drives required current to the load. Fig. 3(a), shows be approximately defined by,
two cells of the electronic circuits. One of these circuits is to
satisfy the voltage gain (M1, M3 and M4), and other is driving (7)
the required load current (M2 and M5). The original of this
buffer circuit [2], shown in Figure 3(b), is a source follower III. OFFSET CANCELLATION TECHNIQUE
employing a negative feedback to reduce the output resistance The offset voltage von (Eq. 1), is the DC level shift between
of the circuit. output and input voltages. The floating-gate [4] has been
employed for offset cancellation. In this technique the second
VDD VDD gate is used to compensate the offset. This method needs high
M3 M3
voltage to program the floating gate (up to 14 V). The concept
VB1
VB1 proposed in this work is shown in Fig. 4. The relaxed CMOS
M2 M2
buffer (MS1 and Ms3) is used as level shifter [6]. The PMOS
M1

Vin
M1
Source Follower (PSF) [7] is used to rise up the source
Vin
Vo
Io+IL
Vo Vo
IL potential of MS1 by the von value of M1 in the main buffer. The
Vo drain current of MS3 is trimmed to adjust each of input and
output at the same DC level. Either, the bias voltage VB1, or
Io IL
M4 M5
M4
VB2 VB2
CL//RL
VB2
CL
transistors size (MS1 and MS3) is used for the offset overcame.
The offset voltage trimming can be employed to improve the
Voltage buffer Current driver
dynamic range consequence, the total harmonic distortion and
IP3 of the buffer amplifier. The proposed approach can be
(a). Basic concept. (b). CMOS buffer amplifier. easier employed for offset cancellation of the main analog
Fig. 3. The negative feedback CMOS buffer. blocks which are suffer from the offset such as operational
amplifier, variable gain amplifier (VGA), ….etc.
In case of the rds1 is large enough, the output resistance of
this circuit can be approximated as As mention above, the transistor's area can be used as
trimming parameter. The systematic offset cancellation
condition can be calculated as in:
(3)
Vgss1=Vgs1 (8)
Where gm1 and gm2 are the transconductance of M1 and
M2; rds3 and rds4 are the output resistance of M3 and M4, Where, Vgss1 and Vgs1, are gat-source voltage of MS1 and
respectively. As the feedback gain, gm1gm2(rds3rds4), is M1, respectively. As shown in Fig 4, the circuit is biased by

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 two pairs of current mirrors (M5-4 and M6-3). M3 saves the Moreover, the offset is tuned using VB1 (Fig.4). The
drain current of M1 constant to satisfy the unity gain of proposed CMOS buffer amplifier is examined at different
voltage. The feedback is accomplished through M2 which is values of VB1 as simulation parameter. The simulation result is
used to enhance the required current needed for driving large shown in Fig. 6.
capacitive/resistive load. Also, the gate-source voltage of M2 1.2V

controls the output voltage swing since; it’s the AC drain Vo

voltage of M1. The Maximum current deliver to the load 1.0V

"current swing" can be approximated as the different between 0.8V

(IDS4-IDS3). MS1 is employed as the level shifter as long as the
MS3 is work in saturation. This level shifting is used to 0.6V

increase the swing headroom for M1 in the main buffer, and

consequently the linearity. 0.4V

0.2V

0V
0.15V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V
MS3 M3
M6 Vin
VB1 M2

Fig. 6. Offset cancellation in proposed buffer.

To compare between our proposed amplifier and other

M1
IB
techniques at [3,4] 3pF capacitor for RF applications. The
Vin
proposed cell has been loaded with a 50Ω resistive load. The
MS1
Voltage down
simulation result is shown in Fig. 7. The simulation shows the
Vo proposed circuit has been achieved phase shift 45o at 1.6GHz
(ω45) and cut off frequency 2.77GHz with 83o phase shift.
M5
Table 2 illustrates the simulation result with comparing by
CL M4
other techniques. The proposed offset trimming buffer
RL
amplifier is simulated at 0.16Vp-p voltage signal and 80 Ω
Level shift The main buffer Bias circuit resistive load. The time response of the amplifier at different
vB2 is shown in Fig .8.
Fig. 4. The proposed CMOS Buffer with offset cancellation 0
Vo(dB
-5

IV. SIMULATION RESULTS -10

The CMOS buffer was implemented in 0.13-µm IBM -15

CMOS process. Table 1 shows transistors’ size for the -20

proposed buffer circuit. The CMOS buffer amplifier with

-25

negative feedback is simulated with 30pF capacitive load -30

which equivalent to oscilloscope probe for out of chip

-35

measurements. The simulation result is shown in Fig. 5. The

-40

enhancement of overall buffer transconductace is tested as

-45

shown in Fig. 5. The simulation is done without feedback

-50
1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz
Frequency

affect (IDs3=IDs4 thus, gm2=0) by adjusting the aspect ratio of

Fig. 7. Frequency response of the proposed buffer (50 Ω, 3pF).
M4 and M5. As shown from the simulation, the second order
system has been emphasized with respect to the basic buffer. 700mV

Moreover, the output impedance has been reduced thanking

for the feedback affect. The bandwidth is enhanced without
650mV

changing of M1 size. 600mV

Vo(dB 550mV

-10

500mV

-20

450mV

-30

400mV
10.0ns 10.5ns 11.0ns 11.5ns 12.0ns 12.5ns 13.0ns 13.5ns 14.0ns 14.5ns 15.0ns 15.5ns 16.0ns 16.5ns 17.0ns 17.5ns 18.0ns 18.5ns 19.0ns 19.5ns 20.0ns

Time
-40

1.0MH 3.0MH 10MH 30MH 100MH 300MH 1.0GH 3.0GH 10GH

-50
Frequenc
Fig. 8. Transient time response of the proposed buffer.
Fig. 5, Frequency response of the proposed amplifier @30pF.

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 Table 1. Transistors’ sizes of the proposed buffer circuit. [3] I. L. Abdel-Hafez "Design of RF-CMOS IC" Ms. Thesis, Zagzig
University, Egypt, 2009.
Transistor W/L [μm/μm] [4] I. L. Abdel-Hafez, Y. A. Khalaf, and F. A. Farag, “CMOS Buffer
Amplifier for Wide Bandwidth Applications,“ IEEE International
Conference on Design and Technology of Integrated Systems in
M1 80/0.2
NanoScale Era (DTIS’7), pp. 56-59, September 2007.
[5] E. Ozalevli, M. S. Qureshi and P. E. Hasler “ Low-Voltage
M2 100/0.2
Floating-Gate CMOS Buffer” IEEE Proceeding of ISCAS pp.
M3 200/1.5 1872-1875, 2006.
[6] W. S. Hassaneina,I. A. Awadb, and A. M. Soliman, " New High
M4 200/0.2 Accuracy CMOS Current Conveyors" Int. J. Electron. Commun.
(AEÜ) 59, pp.384 – 391, 2005.
Ms1 150/1 [7] X. Fan and P. K. Chan, "Analysis and Design of Low-Distortion
CMOS Source Followers" IEEE Transaction on Circuits and
Ms3 10/1 Systems-I, Vol. 52, No.8 August 2005.
M5 50/0.2

M6 100/1.5

IB 600μA

Table 1. The simulation results.

FVF Ref. [2,3] Proposed
Parameter
( 3pF) ( 3pF) (50 Ω, 3pF)
Power dissipation(mW) 2.5 12 4.5
Bandwidth (MHz) 95 1500 1600
Av(dB) -8 -1.34 -0.63
Phase Margin (Degree) 91 43.2 45o

v. CONCLUSION
This paper has presented a low-power and low-voltage
CMOS buffer amplifier. It achieves high bandwidth since
transcounductance has been enhanced due to employing the
feedback. Offset cancellation technique has been proposed and
tested. The proposed buffer has the benefits offset cancellation
of the analog blocks. Our architecture has manifested the
upper hand with respect to the traditional methods. The
proposed circuit has been simulated with 0.13µm CMOS
process parameters from IBM. The simulation result has
illustrated a good agreement with theoretical analysis. The
proposed cell has consumed 4.5mW from 1.5V supply at 50 Ω
and 3pF Load. The cell has achieved 1.6GHz bandwidth at 45o
phase shift.
ACKNOWLEDGMENTS
The author gratefully acknowledges the financial support
of the MOSIS Company for their support and provision of the
device models.
REFERENCES
[1] R. G. Carvajal, J. Ramírez-Angulo, A. J. López-Martín, A.
Torralba, J. A. Galán, A. Carlosena, and F. M. Chavero,” The
Flipped Voltage Follower: a Useful Cell for Low-Voltage Low-
Power Circuit Design,” IEEE Transactions on Circuits and
Systems I: Vol. 52, NO. 7, JULY 2005.
[2] T. L. Viswanathan, “CMOS Transconductance Element,”
Proceeding of IEEE, Vol. 74, pp. 222–224, 1986.

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