ECEN474/704: (Analog) VLSI Circuit Design

Spring 2018

Lecture 1: Introduction

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• Turn in your 0.18um NDA form by Tuesday Jan 23
• No Lab this week
• Lab 1 starts Jan 31

• Lab requires a Linux account

• Go to CVLB 324 to see if you can login
• Same Login ID and Password as the HOWDY portal
• Contact Omar Valenzuela ([email protected]) in
WEB 076 if any issues

• Current Reading
• Razavi Chapters 2 & 17
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Analog Circuit Sequence

326

474/704

720

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Why is Analog Important?
[Silva]

• Naturally occurring signals are analog

• Analog circuits are required to amplify and condition the signal for
further processing
• Performance of analog circuits often determine whether the chip
works or not
• Examples
• Sensors and actuators (imagers, MEMS)
• RF transceivers
• Microprocessor circuits (PLL, high-speed I/O, thermal sensor)
4
Integrated Circuits
[Bohr ISSCC 2009] • 4-core Microprocessor (45nm CMOS)
• Mostly Digital
• Noteable analog blocks
• PLL, I/O circuits, thermal sensor

[Sowlati ISSCC 2009]

• Cellular Transceiver [Pertijs ISSCC 2009]

(0.13m CMOS)
• Considerable analog &
digital
• Instrumentation Amplifier (0.5m CMOS)
• Mostly Analog
• Some Digital Control Logic
5
The Power of CMOS Scaling
[Bohr ISSCC 2009]

• Scaling transistor dimensions allows for improved

performance, reduced power, and reduced cost/transistor
• Assuming you can afford to build the fab
• 32nm CMOS fab ~3-4 BILLION dollars
6
Course Topics
• CMOS technology
• Active and passive devices
• Layout techniques

• MOS circuit building blocks

• Single-stage amplifiers, current mirrors,
differential pairs

• Amplifiers and advanced circuit techiques

7
Course Goals
• Learn analog CMOS design approaches
• Specification  Circuit Topology  Circuit Simulation 
Layout  Fabrication

• Understand CMOS technology from a design

perspective
• Device modeling and layout techniques

• Use circuit building blocks to construct moderately

complex analog circuits
• Multi-stage amplifiers, filters, simple data converters, …

8
Administrative
• Instructor:
• Sam Palermo
• 315E WERC Bldg., 845-4114, [email protected]
• Office hours: T 2:30pm-4:00pm, W 8:30AM-10:00AM
• Distance learning office hours will be held via Zoom (similar to
WebEx) at the same time. Email me if you want to meet and I will
set up the session.
• Lectures: TR 11:00am-12:25pm, WEB 049
• Distance learning lecture recordings will be posted online
on same day at ~4PM
• Class web page
• http://www.ece.tamu.edu/~spalermo/ecen474.html
• We will also use eCampus, but the above will be the main site
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Class Material
• Textbook: Design of Analog CMOS Integrated Circuits, B.
Razavi, McGraw-Hill, 2nd Edition, 2017.
• References
• Analog Integrated Circuit Design, T. Chan Carusone, D. Johns and
K. Martin, John Wiley & Sons, 2nd Edition, 2011.
• Analysis and Design of Analog Integrated Circuits, P. Gray, P.
Hurst, S. Lewis, and R. Meyer, John Wiley and Sons, 5th Edition,
2009.
• Microelectronic Circuits, A. Sedra and K. Smith, Oxford University
Press, 7th Edition, 2014.
• Technical Papers

• Class notes
• Posted on the web
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Grading
• Exams (60%)
• Three midterm exams in class (20% each)
• For distance learning students, you should have your manager
proctor the exam
• Homework (10%)
• Collaboration is allowed, but independent simulations and write-ups
• Need to setup CADENCE simulation environment
• No late homework will be graded
• Laboratory (20%)
• Lab will start on the third week (Jan. 31)
• Need to complete NDA for 180nm process access
• Final Project (10%)
• Groups of 1-3 students
• Report and PowerPoint presentation required
11
Preliminary Schedule

• Dates may change with reasonable notice

12
CMOS Technology Overview
• MOS Transistors
• Interconnect
• Diodes
• Resistors
• Capacitors
• Inductors
• Bipolar Transistors

13
CMOS Technology
[Razavi]

NMOS PMOS

• Why p-substrate?
• Easier to build n-wells vs p-wells
• Allows for overall reduced doping levels 14
 NMOS Transistor
CVD Oxide [Silva]
Source
Metal 1
Drain NMOS Symbols
Poly Gate

n+ n+ Cross Section
Gate Oxide

p substrate

Bulk

Gate

Source Drain Circuit Symbol

Bulk

n+ Poly n+
Top View
W

15
PMOS Transistor
CVD Oxide [Silva]
Drain Metal 1 Source PMOS Symbols
Poly Gate

p+ Gate Oxide p+ Cross Section

n-well Bulk
p substrate

Bulk

Gate

Drain Source
Circuit Symbol
Bulk

Top View

16
Today’s Planar CMOS Transistors
[Bohr ISSCC 2009]

• Today’s transistors have advanced device structures

• Modern transistors are moving from poly-gates back to
metal-gates
• Allows for High-K gate dielectric and reduced gate leakage current
17
FinFET Transistors [Bohr 2011]

32nm Planar Transistors 22nm FinFET Transistors

[Nowak IEEE 2004]

• Introducing a vertical 3rd-
dimension allows for better
gate control and superior
device performance
• The most advanced CMOS
processes are based on
these FinFET devices In the graphs above “Double-Gate”
means the FinFET transistor 18
Interconnect (Wires)

[Bohr ISSCC 2009]

19
 Diodes
[Silva]
Anode Cathode

Typical values:

P+=1017-1019 acceptors /cm3

P=1015-1017 acceptors /cm3
A C
N=1016-1018 donors/cm3
SiO2
N+=1017-1019 donors/cm3
P+ N+
N Metal  5x1022 electrons/cm3
Diode Contact
Bulk (substrate) P-type

20
Resistors
Poly Resistor Nwell Resistor
[Razavi]

• Different resistor types have varying levels of

accuracy and temperature and voltage sensitivities
21
 Capacitors
Poly - Diffusion Poly - Poly Metal1 - Poly

[Razavi]
Vertical Metal “Sandwich” Lateral Metal-Oxide-Metal (MOM)

[Wang]

[Ho]

22
 Inductors
[Silva/Park]

• Inductors are generally too big for widespread use in analog IC design
• Can fit thousands of transistors in a typical inductor area (100m x 100m)

• Useful to extend amplifier bandwidth at zero power cost (but significant

area cost)
23
 Bipolar Transistors – Vertical PNP
[Johns] Vertical PNP Bandgap Reference

• Useful in a precise voltage reference circuit commonly

implemented in ICs (Bandgap Reference)

24
 Bipolar Transistors – Latchup
Equivalent Circuit
[Razavi]

• Potential for parasitic BJTs (Vertical PNP and Lateral NPN) to form a
positive feedback loop circuit
• If circuit is triggered, due to current injected into substrate, then a
large current can be drawn through the circuit and cause damage
• Important to minimize substrate and well resistance with many
contacts/guard rings
25
Next Time
• MOS Transistor Modeling
• DC I-V Equations
• Small-Signal Model

26