Micro Processor Basics

1. A Micro processor is _____

a. Multi purpose b. Clock driven c. Register based d. All *

2. The physical components of the system is ______

a. Software b. Hardware* c. Firmware d. None

3. A set of instructions are called ______

a. Software b. Hardware c. Program* d. None

4. A group of programs are called ______

a. Software* b. Hardware c. Firmware d. None

5. Microprocessor Applications are

a. Re-programmable b. Embedded system c. Both A & B * d. None

6. The first microprocessor introduced by ______

a. Intel 1970 b. Intel 1971* c. Intel 1972 d. None

7. The first microprocessor is ______

a. Intel 404* b. Intel 406 c. Intel 504 d. None

8. 4-bit microprocessor introduced were

a. Rockwell pps4 b. Toshiba’s T 3472 c. Both a & b* d. None

9. 8-bit microprocessor was _____

a. Motorola’s M 6800* b. Rockwell c. Zilog d. All

10. The 16 microprocessor is ______

a. Rockwell b. Motorola’s c. Zilog* d. All

11. The heart of the microcomputer is _____

a. Microprocessor* b. Hardware c. Software d. None

12. To send and receive the data using with ____

a. Control bus b. Data bus* c. Both d. None

13. The address bus is

a. Un-directional* b. Bi-directional c. Both d. None

14. The data bus is

a. Un-directional b. Bi-directional* c. Both d. None

15. Instruction can be referred to by abbreviated codes known

a. Program b. Mnemonic* c. Both d. None
16. A machine language program is in ______

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

a. Binary code * b. octal c. decimal d. All

17. High level language is ______

a. C b. Pascal c. Cobol d. All*

18. Pin diagram having ____ pins

a. 10 b. 20 c. 30 d. 40*

19. Pin 3 used for _____

a. Read b. write c. Reset* d. Selection

20. For status signals ______

a. Pin 29 b. Pin 33 c. Both * d. None

21. Commonly used to connect the output devices to micro process

a. Interrupts b. Latch* c. Both d. None

22. _____ pin used for CLK out

a. 37* b. 38 c. 39 d. None

23. _____ pin used for HOLD

a. 37 b. 38* c. 39 d. None

24. _____ pin used for Vec

a. 37 b. 38 c. 39 d. None*

25. A very small storage Area is called _____

a. Register* b. Program c. Keyboard d. None

26. An accumulator is ______

a. A* b. B c. C d. D

27. Instruction fetch time +Instruction execution time = ______

a. Fetch cycle b. execution cycle c. Instruction cycle d. All

28. First clock cycle is denoted by ______

a. T1* b. T2 c. T3 d. T4

PART - B

Two Marks
1. A typical programmable machine can have ____ components
i. Microprocessor ii. Memory iii. Input/Output device
a. Only I b. Only ii c. Only iii d. All*

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

2. Match the following.

1. 4-bit processor i. 4004
2. 8-bit ii. 8008
3. 16-bit iii. 8088
a. (1,i), (2,ii), (3,iii)* b. (1,iii), (2,ii), (3,i) c. Both d. None

3. Input devices are

i. Keyboard ii. Mouse iii. Toggle switch
a. Only I b. Both I & ii c. Only iii d. All*

4. Pin diagram have ______

i. +5 volts power supply ii. Clock frequency is 3.125 MHz
iii. At least frequency is 1.0 MHz
a. Only I b. Only ii c. Only iii d. All*

5. ALU perform _____

i. Addition, subtraction, multiplication, division ii. AND, OR, NOT iii. Any operation
a. Only I* b. Only ii c. Both I & ii only d. All
PART –C (4 MARKS)
1. Arrange the following data
1. Displaying the data 2. Perform the data 3. Receiving the data 4. Storing the data
a. 1,2,3,4 b.4,3,2,1 C. 2,3,1,4 D. 3,2,4,1*

2. Match the following.

1. pin 6 to pin 10 i. Data bus or Multi plexed add
2. pin 21 to pin 28 ii. Status signals
3. pin 12 to pin 19 iii. Interrupts
4. pin 29 and pin 33 iv. Address bus
a. (1,i), (2,ii), (3,iii), (4,iv) b. (1,iv), (2,iii), (3,ii), (4,i)
c. (I ,iii), (2,iv), (3,i), (4,ii)* d. None

3.Match the following

1. Carry flag i. Do
2. Parity flag ii. D1
3. Auxiliary flag iii. D2
4. Zero flag iv. D3
5. Sign flag v. D4
Vi. D5
vii. D6
viii. D7
a. (1,I), (2,iii), (3,v), (4,vii), (5, viii)* b. (I,I), (2,ii), (3,iii), (4,iv), (5,v)
c. (1,ii), (2,iii), (3,vii), (4,v), (5,I) d. None

4. Match the following data

1. General purpose Registers i. A,B,C,D,E,H and L

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

2. Special purpose Registers ii. Ac, pc, sp, and states flag
a. (I, i), (2,ii)* b. (1,ii), (2,i) c. Both a & b d. All

2. Programming 8085
PART – A (1 MARK)
1. The 8085 has _____ addressing modes
a. 2 b. 4 c. 5* d. 6

2. In ____ mode, the data is available after the opcode

a. Immediate* b. Direct c. Register d. Implied

3. _____ address pointed by the register pair

a. Actual b. Effective c. Both a & b* d. None

4. Instruction format having ____ field

a. 1 b. 2* c. 4 d. 8

5. The fields are _____

a. Opcode b. Address or data c. Both* d. None

6. The data word formal having ____ bits

a. 4 b. 8* c. 16 d. 32

7. MSB refers to _____

a. Most Significant Bit* b. Least Significant Bit c. Both d. None

8. The single byte instruction has only one field called _____
a. Opcode* b. data c. both a & b d. none

9. The 2 bytes instruction has only 2 fields called ____

a. Opcode b. data c. both a & b* d. none

10. The instruction set can be divided into _____

a. 1 b. 3 c. 5* d. None

11. MOV is the _____ operation

a. Data transfer* b. Arithmetic c. Logical d. Branching

12. LDA, STA is the ____ operations

a. Data transfer* b. Arithmetic c. Logical d. Branching

13. Arithmetic operations are _____ (Logical operations also)

a. ADD, SUB, MUL, DIV b. AND, ON c. NOT, EX-OR d. All*

14. Branching, we have ____

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

a. Unconditional Jump b. Unconditional c. Both * d. None

15. The group of memory location is called ____

a. Stack* b. Sub-routine c. Both d. None

16. On stacks, we can perform ____ operations

a. PUSH, POP* b. CALL, RET c. Both a & b d. None

17. On subroutine, we can perform _____ operation

a. PUSH, POP b. CALL, RET* c. Both a & b d. None

18. To leave the main program for _____

a. Call the subroutine* b. Returning the subroutine c. Both d. None

19. CNZ is
a. Conditional call* b. Conditional return c. Both d. None

20. RNC is _____

a. Conditional call b. Conditional return* c. Both d. None

21. To develop software for a particular _____

a. Microprocessor* b. Micro computer c. Both d. None

22. The system is managed by a program called _____

a. Program b. Hardware c. Operating system* d. None

23. The 8085 mnemonic but operate under the 8088 microprocessor
a. Assembler b. Cross assembler* c. Both d. None
PART – B ( 2 MARKS)

1. 8-bits is called _____

I. nibble ii. Byte iii. Byte iv. Mega byte v. Giga byte
a. Only ii* b. All c. Both I & ii d. Only i

2.A/C to following diagram, match the data _____

D7 D6 D5 D4 D3 D2 D1 D0
1. LSB i. D6
2. MSB ii. D7
a. (1,ii), (2,i) b. (1,i), (2, ii)* c. Both d. None

3. What are storage peripheral devices

i. Floppy disk ii. Hard disk iii. CD-ROM
a. Only I b. Only ii c. Only iii d. All*

4. Match the following.

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

i. Line editor 1. MS-DOS

ii. Full screen editor 2.MS-WORD
a. (I,1), (ii,2) * b. (I,2), (ii, 1) c. Both d. None
5. What are the tools for developing the assembly language
i. Editor ii. Assembler iii. Loader iv. Debugger
a. Only I b. Only ii c. Only I & ii d. All*

6. The binary code file is called

i. COM file ii. EXE file iii. Data file
a. Only I b. Only iii c. both I & ii* d. None

PART –C (4 MARKS)
1. Arrange the following data in order – (A/c to developer)
1. Windows 95/98 2. Unix operating system 3. MS-DOS d. os/2
a. 1,2,3,4 b. 4,3,2,1 c. 2,3,1,4 d. 3,4,1,2*

2. From which address is subroutine in the following program

6000 L x 1 sp 3000
6003 _____
___ ____
____ ____
6010 CALL DELAY (6500)
6013 _____
6500 DELAY
_____ _____
_____ _____
_____ _____
6506 RET
a. 6010 b. 6500* c. 6506 d. None

3. Match the following.

1. colon i. After label
2. space ii. Between an opcode & an operands
3. comma iii. Between two operands
4. semi colon iv. Before the beginning of a comment
a. (1,i), (2,ii), (3,iii), (4,iv)* b. (1,iv), (2,iii), (3,i), (4,i)
c. (1,i), (2,iii), (3,ii), (4,iv) d. None

PART-A (1 MARK)

1. The word “micro face” means

a. link * b. input c. output d. None

2. The process of exchange the control signals is called _____

a. Transfer b. Change c. Hand shaking* d. None

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

3. A group of input/output is also known as _____

a. port* b. input c. output d. None

4. The I/O port having ____ bits

a. 4 b. 8* c.16 d. 62

5. To recognize its own address on the address bus is called ______

a. Address decoder* b.Decoder c. Multiplexer d. all

6. ____ is essentially a collection of switches

a. Keyboard* b. Mouse c. Printer d. All

7. In keyboard, each key requires _____ bit location at the input port
a. 1* b. 2 c. 3 d.4

8. The debouncing of the closed key is achieved by waiting _____

a. 1 to 10 mille sec b. 10 to 20* c. 20 to 30 d. 30 to 40

9. In keyboard, the encoding of row and column is in

a. Hexadecimal b. ASCIT c. Both a& b* d. None

10_____ to seven segment code convert in is done using a software

a. ASCIT b. EBCD c. BCD* All

11. _____ is an integral part of microprocessor system

a. Memory* b. Keyboard c. Microprocessor d. Mouse

12. EPROM stands for _____

a. Electrical Process Read Only Memory b. Erasable Process Read Only Memory
c. Erasable Programmable Random Only Memory
d. Erasable Programmable Read Only Memory*

13. Microprocessor can communicate with ____ device at a time

a. 1* b. 2 c. 3 d. 4

14. _____ are common for all devices

a. data bus b. address bus c. control bus d. All*

15. _____ are decoded to select the memory chip

a. Lower Address lines b. Higher address lines* c. both d. None

16. The selection of memory chip is called _____

a. Linear decoding* b. Absolute c. both d. None

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

17. The input/output accomplished by _____

a. I/o port* b. Keyboard c. Monitor d. None

18. The input port is a _____

a. buffer* b. latch c. both d. None
19. The output port is _____
a. buffer b. latch * c. both d. None

20. The input port is also called as _____

a. Single buffer b. Bi-state c. Tri-state buffer* d. All

21.Most of the microprocessors are supported _____

a. isolated I/o* b. I/o system c. Memory d. All

22 The I/o operations are _____

a. IN b. OUT c. both a & b* d. None

23. Both I/o mapped and memory mapped I/o having ____ bits
a. 4 b. 8 c. 10* d. 32

24. I/o controlled by _____

a. Hand shaking b. Ready signal c. both a & b* d. None

PART-B ( 2 MARKS)
1. For obtaining the data form keyboard
i. Detect a closed key ii. Debounce the closed key iii. Encode the closed key
a. Only I b. Both I & ii c. Both ii & iii d. All*

2. The keyboard also associated with _____

i. 2-key lock out ii. N-key roll over
a. Only I b. Only ii c. Both I & ii* d. None

3. With the help of microprocessor, we can achieve _____

i. Output the required code for the display
ii. Output the code vice left to right entirely into the displace of more than one key in
member
a. Only I b. Only ii c. Both I & ii* d. None

4. For interfacing the Hexadecimal. We use the technique

i. None of the above multiplexed ii. Multiplexed
a. Only I b. Only ii c. Both I & ii* d. None

5. The size of the memory is N x M where

i. N= no of Registers ii. M= Length of the board
a. Both are right* b. Only I right c. Both are wrong d. None

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

6. The memory interfacing requires _____

i. Select the chip ii. Identify the Register iii. Enable the appropriate buffer
a. All* b. both I & ii c. both ii & iii d. None

Interrupts
PART – A (1 MARK)

1. A process of data transfer by an external device is called _____

a. Input b. Output c. Exclaim d. Interrupt*

2. If the interrupt occur, then the microprocessor will do _____

a. same work b. other work* c. idle d. None

3. The interrupt signal is activated by

a. input b. output c. CALL* d. RET

4. The sub routine starts from _____

a. First location b. Second location c. Vector location* d. None

5. The microprocessor does not respond _____

a. marked* b. unmarked c. both d. None

6. The interrupt marked under

a. hardware b. software control* c. both d. None

7. Interrupts are ____ types

a. 1 b.2* c. 3 d.4

8. Hardware interrupts are _____types

a. 1 b. 3 c. 5* d. 7

9. Software interrupts are _____ types

a. 2 b. 4 c. 6 d. 8*

10. TRAP is a _____

a. Maskable b. nonmaskable* c. both d. None

11. Maskable interrupts are

a. RST 7.5 b. RST 6.5 c. RST 5.5 d. All*

12. The highest priority interrupt is _____

a. TRAP* b. RST 7.5 c. RST 5.5 d. All

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

13. TRAP acknowledge clear is

a. Gate b. Flip* c. Both d. None

14. The triggers having

a. D flip flop b. AND gate c. both* d. None

15. Polling must be done to find out which device has called
a. Multiplexer b. Decoder c. Microcomputer d. Microprocessor*

16. If the poling is set _____ routine is called

a. I/o port A* b. I/o port B c. I/o port C d. I/o port D

17. _____ interrupts can be enabled and disabled under program control
a. Maskable* b. unmaskable c. both d. None

18. Multiple interrupt devices using _____

a. 1 to 5 priority b. 8 to 3 priority* c. 3 to 4 priority d. 5 to 8 priority

19. The only drawback in interrupting is _____

a. I7 is always lower, priority b. I7 is always higher priority*
c. Both d. None

PART – B
1. Interrupts are having
i. Maskable ii. Unmaskable
a. Only I b. Only ii c. both I & ii* d. None

2. Interrupts are classified

i. Hardware ii. Software
a. Only I b. Only ii c. both I & ii* d. None

3. Maskable interrupts are

i. RST 7.5 ii. RST 6.5 iii. RST 5.5
a. both I & ii b. both ii & iii c. both I & iii d. All*

4. Vector interrupts are

i. TRAP ii. RST 7.5 iii. RST 6.5 iv. RST 5.5
a. both I, ii & iii b. both ii, iii, & iv c. only I d. All*

5. TRAP interrupt is recognized by

I, low signal in the RESET IN pin ii. High signal on TRAP
a. Only I ii. Only ii c. both I & ii* d. None

6. Pending means _____

i. first interrupt ii. Remaining except first iii. first and rest remains

10

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

a. Only I b. Only ii c. Only I & ii d. Only iii*

PART - C

1. A pill may programmed for

i. Simple input or output mode ii. Strobed input or output mode iii. Control mode
a. Only I b. Only ii & iii c. both I & ii d. All*

2. The machine cycles are ____-

i. Fetch cycle ii. Indirect cycle iii. Execute cycle iv. Interrupt cycle
a. Only I & iii b. Only ii & iv c. Only I & ii d. All*

3. Arranging the following data A/c to I/o Transfer technique

1. Hardware controlled I/o 2. I/o controlled by ready signal
3. Program controlled I/o 4. Interrupt program controlled I/o
5. I/o controlled by handshaking
a. 1,2,3,4,5 b. 5,4,3,2,1 c. 3,2,1,4,5 d. 3,4,1,5,2*

Programmable Peripheral Services

PART – A ( 1 MARK)
1. The serial programmable peripheral devices _____
a. 8212 b. 8279 c. both a & b* d. None

2. The parallel programmable peripheral devices

a. 8255 b. 8259 c. 8253/54 d. All*

3. The 8212 has ____ pins

a. 40 b. 24* c. 42 d. 50

4. The 8212 has _____ D-type latches

a. 2 b. 4 c. 6 d. 8*

5. Each latch having _____ buffer

a. single b. tri* c. bi d. All

6. For the input and output

a. 8212* b. 8279 c. 8255 d. 8259 e. 8253/54

7. For only input through keyboard

a. 8212 b. 8279* c. 8255 d. 8259 e. 8253/54

8. For ports _____

a. 8212 b. 8279 c. 8255 * d. 8259 e. 8253/54

9. For Registers _____

a. 8212 b. 8279 c. 8255 d. 8259* e. 8253/54

11

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

10. For interrupts _____

a. 8212 b. 8279 c. 8259 d. 8253/54*

11. The keyboard entries are stored in _____

a. FIFO* b. LIFO c. both d. None

12. In 8212, the segment has _____ memory

a. 16 x 1 b. 16 x 4 c. 16 x 8* d. 16 x 16

13. The keyboard section has ____ memory

a. 8 x 1 b. 8 x 4 c. 8 x 8* d. 8 x 16

14. The keyboard section has ____- register

a. 2 b. 4 c. 8* d. 16

15. The scan counter has ____ scan lines

a. 2 b. 4* c. 8 d. 16

16. It uses _____ decoder

a. 14 x 16 b. 4 x 16* c. 3 x 8 d. 2 x 4

17. The microprocessor interface section have _____ bi-directional

a. 2 b. 4 c. 8* d. 16

18. 8255-has 24 pin divided into 3 bi-directional ports called

a. port A b. port B c. port C d. All*

19. To store all the interrupts level

a. ISR b. IRR * c. both d. IMR
PART – B ( 2 MARKS)
1. The 8212 have
1. MD (mode) = 0 i. Latch state buffer
2. MD = 1 ii. Latch to demultiplexing
a. (1,I), (2,ii)* b. (1,ii), (2,I) c. both a & b d. None

2. The tri-state bi-directional buffer is used

i. interface between keyboard & micro process
ii. Interface between database of 8255 & system database
a. Only I* b. Only ii c. both I & ii d. None
PART – C (4 MARKS)

1. Arrange the following data

1. RST 5.5 2. INTR 3. TRAP 4. RST 7.5 5. RST 6.5
a. 1,4,5,3,2 b. 2,3,4,1,5 c. 3,2,1,5,4 d. 3,4,5,1,2*

12

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

2. Match the following.

1. TRAP i. 0034 H
2. RST 7.5 ii. 0024 H
3. RST 6.5 iii. 003C H
4. RST 5.5 iv. 002 C H
a. (1,I), (2,ii), (3,iii), (4,iv) b. (1,ii), (2,iii), (3,I), (4 iv)*
c. (2,I), (3,iv), (1, iii), (4,iv) d. None

3. Match the following.

1. Input & output i.40
2. control pins ii. 2
3. Select pins iii. 4
4. Total pins iv. 8
a. (1,I), (2,ii), (3,iii), (4,iv) b. (1,iv), (2,iii), (3,ii), (4,i)* c. both d. None

4. The control pins are

1. CLR (clear) 2. STB (strobe) 3. INT (interrupt) 4. MD (mode)
a. both I & iii b. both ii & iv c. both I & iv d. All*
Serial I/o Data Communication

1. The 8085 microprocessor is a ____ device

a. parallel* b. serial c. both d. None

2. The parallel Data Communication for a long distance

a. Reliable b. Expensive* c. Inexpensive d. None

3 In serial I/o mode ____bits are at a time

a. 1* b. 2 c. 3 d.4

4. The no. of bits per second called _____

a. band * b. serial c. parallel d. All

5. The microprocessor identifies the peripheral through

a. Data bus b. Address bus c. Port address * d. All

6. The parallel I/o uses _____

a. Data line b. Entire data bus* c. Address line d. Address bus

7. The serial I/o uses _____

a. Data line* b. Entire data bus c. Address line d. Address bus

8. The microprocessor selects the peripheral through ______

a. Device select b. Address select c. Chip select* d. None

13

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

9. At the time of chip select it will use ____

a. READ b. WRITE c. both * d. None

10. The synchronous data transfer is used for ____

a. Low speed b. high speed* c. both d. None

11. The Asynchronous data transfer is used for ____

a. Low speed* b. high speed c. both d. None

12. The data transfer only in one direction at a time is ____

a. Simplex ( half duplex) b. duplex (full duplex) c. both d. None

13. The data can transfer in both direction _____

a. simplex b. duplex* c. both d. None

14.The teletype (TTY) generally run on ____ band or baud

a. 10 b. 100 c. 110* d. None

15. The terminals like printer run on ____ band

a. 10 to 9600 b. 50 to 960 c. 50 to 96 d. 50 to 96*

16. 1200 bits per second . Each bit take the time is _____
a. 0.63 b. 0.73 c. 0.83* d. 0.93

17. In parity check, the bit is added at ____

a. MSB* b. LS c. both sides d. None

18. The 2’s compliment need in _____

a. parity check b. check sum* c. CRC d. All

19. Mathematical relationship in polynomial technique in ____

a. parity check b. check sum c. CRC * d. All

20. _____ technique is used for long distance through telephone

a. parallel I/o b. serial I/o* c. both d. None

21. Bandwidth of the telephone line is _____ (Analog signal)

a. 3 to 33 Hz b. 30 to 330 Hz c. 300 to 330 d. 300 to 330*

22. Bandwidth of the digital signal is ______

a. Hz b. MHz* C. Both d. None

23. _____ is a circuit that translates digital data into audio tone
a. modem* b. speaker c. chip d. All

14

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

24. Computer exchange information over telephone line by using -____

a.1 modem* b. 2 modem c. 3 modem d. 4 modem

25. The serial I/o technique is used to _____

a. interface* b. input c. output d. All

26. The standard in serial I/o is _____

a. RS-232 C b. DTE c. DCE d. All*

27. The serial data transmission can be implemented through

a. Software b. Hardware c. both* d. None
28. Which approach is flexible
a. parallel I/o* b. serial I/o c. both d. None

29. Receiving one bit at a time and forming an 8 bit parallel was
a. Data b. Data input c. Data reception* d. All

30. _____ is a device widely used in serial I/o

a. INTEL 8521 A b. INTEL 8512 c. INTEL 8251 A USART* d. None

31. ____ is a programmable chip designed for synchronous and Asynchronous

a. 8251 A* b. 8521 A c. 8125 d. All

32. ______ is the 8251 A and forces it into the idle mode
a. Read b. Write c. Clock d. Reset*

PART – B (2 MARKS)
1. Serial peripheral can be interfaced under
i. program control ii. Interrupt control
a. Only I b. Only ii c. both I & ii* d. None

2. ASCII stands for

a. American standard code for information Interchange*
b. American synchronous code for information Interchange
c. both d. None

3. Match the following data.

1. logic 1 i. mark
2. logic 0 ii. Space
a. (1,I), (2, ii)* b. (1,ii), (2,i) c. both d. None

4. For error check

i. party check ii. Check sum iii. CRC ( Cyclic Redundancy Check)
a. Only iii b. both I & ii c. both I & iii d. All*

15

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

5. Modulation Technique are

i. Frequency shift keying (FSK) ii. Phase shift keying (PSK)]
a. Only I b. Only ii c. both I & ii* d. none

6. Match the following.

1. logic 0 i. -3V to -5V
2. logic 1 ii. +3V to +5V
a. (1,i), (2,ii) b. (1,ii), (2,i)* c. Both d. None

7. 8085 microprocessor has 2 pin specially designed for

i. serial output data (SOD) ii. Serial input data (SID)
a. Only I b. Only ii c. both I & ii* d. None
8. USART stands for
a. Universal Synchronous/Asynchronous Receiver/Transmitter*
b. Union Symbol All Receive and Transfer
c. United Standard and Resource Transfer d. None

9. R/W control having

i. I control logic ii. 6 input signal iii. 3 buffer Register
a. Only I b. both I & iii c. both ii & iii d. All*
PART – C (4 MARKS)
1. Match the following data.
1. Interface Requirements i. CRC
2. Alphanumeric code ii. Serial I/o and parallel I/o
3. Error check iii.2 compliment
4. Data communication iv. Modems
a. (1,I), (2,ii), (3,iii), (4,iv) b. (1,iv), (2,iii), (3,ii), (4,i)
c. (1,ii), (2,iii), (3,I), (4,iv)* d. None

2. Match the following data.

1. 30 H to 39 A H i. carriage return and line
2. 41 H to 5 A H ii. 0-9 (numeric)
3. 21 H to 2 F H iii. Various symbols
4. 00 H to 1 F H iv. A – Z (Alphabets)
a. (I, ii), (2,iv), (3,iii), (4,i)* b. (1,I), (2,iii), (3,ii), (4,iv)
c. (I,ii), (2,I), (3,iv), (4,iii) d. None

3. Transmission formal involves

i. Synchronization ii,. Data flow iii. Speed iv. Errors v. medium transmission
a. Only I b. Only iii* c. both I, ii & iii d. All

4. ASCII character in asynchronous transmission having ____

i. 1 start bit ii. 8 character bits iii. 2 stop bits iv. Low & high speed
a. both I & ii b. I, Ii, iii* c. Only iv d. None

16

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451

 Micro Processor Basics

5. The RS-232 having

1. data signals 2. control signals 3. timing signals 4. Grounds
a. 1,2,3 b. 2,3,4 c.2,4 d. All*

6. The program should perform

1. Output a start bit 2. Convert the character into a stream
3. Add parity information if necessary 4. Output one or two stop bits
a. 1,2,3 b. 1,2,3,4 c. 2,3,4 d. 1,2

7. 8251 A having ____

1. Data bus buffer 2. Read/write control logic 3. Modem control
4. Transmitter 5. Receiver
a. 1,2,3,4 b. 1,2,3,4,5 c. 3,4,5 d. None

17

Bhargavi Institute of Management and Technology, KPHB, Ph:-040-23068451