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NK Arjun

The document provides a summary of a physical design engineer's experience including their technical skills, projects, academics, and contact information. They have over 3 years of experience in VLSI physical design using tools like Synopsys ICC2 and Primetime for nodes ranging from 45nm to 7nm. Key responsibilities included synthesis, STA, timing closure, DRC/LVS signoff, and fixing timing issues through ECO iterations.

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Nishanth Gowda
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44 views3 pages

NK Arjun

The document provides a summary of a physical design engineer's experience including their technical skills, projects, academics, and contact information. They have over 3 years of experience in VLSI physical design using tools like Synopsys ICC2 and Primetime for nodes ranging from 45nm to 7nm. Key responsibilities included synthesis, STA, timing closure, DRC/LVS signoff, and fixing timing issues through ECO iterations.

Uploaded by

Nishanth Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ARJUN N K

Email: [email protected]
PROFILE SUMMARY:

✔ Physical Design Engineer with 3 years 1month of total experience in VLSI


✔ Technology Nodes: 45nm,28nm, 10nm,7nm,5nm
✔ Tools Used: Synopsys Tools ICC2, Primetime
✔ Language: TCL Scripting
✔ Technical Skills : Physical Design, Static Timing Analysis, Sign off, ECO, TCL scripting
✔ Previous Client Experience: Ai Micron
EXPERIENCE SUMMARY:

● Physical Design Engineer, 2021– 2024: Working as Physical Design Engineer for Ai Micron client
from BigPerl Solutions Pvt Ltd.
PROJECT DETAILS:

Project Description Role & Challenges


TSMC 28nm Technology Node:  Responsible for synthesis
>TSMC 28nm Block  overall setup and execution of Flat STA
 Synthesis and STA timing closure for top level and interface paths
> Clock Frequency - for top and sub-HM (hard macro)
800Mhz  Developed scripts to report violating interface paths
 Worked with SOC on hierarchical STA for constraint updates at
>Block TOP level
Dimension:350x1400um  Clock mapping for AUSDIA runs at SOC and supporting PD
(WxH) collaterals on timing closure.
>Tool Used:
Synopsys ICC2

TSMC 10nm Client: Ai Micron  This Project is from RTL to GDS, and this block was critical with
respect to timing and congestion.
>Node: 10nm.  Sanity checks in each stage
 Responsible for timing closure using STA.
>Clock Frequency :1Ghz.  DRC, LVS and IR checked as a sign-off checks.
 Analyzed and changed the Bounds Placements for worst timing
>Block Dimension: critical paths.
620x2800um(WxH)  Analyzed and fixed Intra and Inter Timing and DRC are by
several ECO Iterations.
>Tool Used:
Synopsys ICC2,Primetime
Nokia >Technology node : 5nm  Block level Synthesis, SDC validation

>2million gate count.  -timing optimization


 -Involved in LEC implementation.
> It has 4 clocks with  Flow setup, Complete analysis of timing and reporting
Operating frequency of 1 GHz constraints related issues
>Tool Used: Genus, PT

Roject > Technology Node :7nm - Synthesis & STA Environment setup
Neolite - LIB/LEF & NDM generation across multiple corners
> Tool : Fusion Compiler, - Tech-Node Migration for the Modules
Prime Time - Synthesis, STA and CLP for the Modules
- Timing closure with usage of less leakage cells
> Frequency : 2.1 GHZ
- ECO (Engineering Change Order) done on netlist to swap the
> Cell count : 480 K memories (to reduce clock to q delay) and provided feedback to
design team
> Description : Block Level
Implementation

NXP PF8200 >Tech node : 45nm  Done Block level Synthesis, SDC validation
 Complete analysis of timing and constraints
>100k gate count. related issues
 Involved in LEC implementation
>It has 2 clocks with
Operating frequency of  Fixing of preserve related issue, timing lint issue,
0.25GHz SDC modifications, Checklist requirement

>Tool Used:
Genus, PT, Conformal
ACADEMICS:

 B.Tech (ECE) from College of Engineering Munnar,Idukki,Kerala


 Higher Secondary from GBHSS Koyilandy,Kerala
 SSLC Completion from Poilkave HSS,Kerala

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