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B V Nishanth

The document provides a technical summary and work experience of an individual. It details their skills and qualifications, as well as 3 projects they worked on involving physical design implementation from netlist to GDSII using EDA tools like Synopsys ICC2, Innovus and Primetime on technologies ranging from 10nm to 16nm.

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Nishanth Gowda
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88 views3 pages

B V Nishanth

The document provides a technical summary and work experience of an individual. It details their skills and qualifications, as well as 3 projects they worked on involving physical design implementation from netlist to GDSII using EDA tools like Synopsys ICC2, Innovus and Primetime on technologies ranging from 10nm to 16nm.

Uploaded by

Nishanth Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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NISHANTH B V 9972320906

[email protected]

TECHNICAL SUMMARY
● Having 2+ years of experience as a Physical Design Engineer
● Hands on technical expertise in Block level physical design implementation from Netlist
to GDSII.
● Worked on 10nm, 14nm, 16nm , 28nm
● Good knowledge and Understanding of Synthesis.
● Good knowledge on Static Timing Analysis.
● Basic knowledge of TCL Scripting.
● Hands on experience on cadence Innovus, Synopsys ICC2 and Primetime.
● Ability to multi-task and flexibility to work in global environment.

TECHNICAL SKILLS
● Operating System : Windows and Linux.
● EDA Tools : Synopsys ICC2, innovus, Design compiler (DC), Primetime.
● Scripting Language : TCL

WORK EXPERIENCE:
● Worked as PD Engineer in VA-Solutions Pvt Ltd from June 2021 to till now

EDUCATION QUALIFICATION:
● Bachelor of Engineering in Electronics & Communication in 2019, from VTU

PROJECT DETAILS:
Project: 1
Duration : 7month
Client : Texas Instruments

Tools Used Synopsys ICC2,Primetime


Technology 10nm
Instant Count 2M
Macro 40
Clocks & Frequency 3clock and 1GHZ
Roles & Responsibilities Floor plan and timing closure responsible for block DRC

Internal
Description and Challenges:
● Multiple iterations of floor plan to achieve acceptable congestion.
● Rectilinear floor plan with lots of congestion High congested design where macro
placement played a key role
● Timing closure of highly congested design by techniques such as load-splitting, swaps,
sizing, buffering
● Congestion fixing, Timing fixing DRV Fixing.
● DRCs (Shorts and opens)
● Timing Analysis &Optimization techniques.

Project: 2
Duration : 7 Month
Client : Texas Instrument
Technology/Layers 16nm/ 13 Metal layers
Instant count 2M
Macros 20
No. of clocks 4 clock
Frequency 1GHz
Tool Used Synopsys ICC2, Primetime
Role Floor plan ,Place and route

Description and Challenges:


● The following stages of Physical Design were covered in this project work.
● Floor plan: Used source file for placement of IO Ports. Placed Macros, created keep out
margin for macros. Fixed Macros and IO ports. Added End-Cap Cells, Tap cells. Derived
PG connection, created power straps for nets VDD, VSS and pre route standard cell rails,
● Placement: Create placement, legalized placement, Verified Cell density, Pin density,
Placement utilization & generated Congestion report. Setup fix Drv fix.
● CTS: Defined the routing rules width and clock nets, specified CTS buffers used for
optimization. Setup fix hold fix Drv fix done.
● Routing: Defined routing layers for routing, fixing timing and shorts and opens.

Project: 3
Duration : 7 Month
Client : SIPREL

Internal
Tools Used INNOVUS
Technology 14nm
Instant Count 1M
Macro 11
Clocks 1.6GHZ
Roles and Responsibilities Block level PnR implementation

Description and Challenges:


● Macro Placement using Flyline analysis.
● Creating the secondary grid at initial Floorplan stage and Adding Custom Buffers and
verify the secondary grid after Floorplan stage.
● Port Placement.
● Bound creation (Hard bound) at pre-place stage with specified region for cells.
● Place stage issues with congestion, cell density, pin density.
● After CTS stage issues with Skew, Latency.
● After Post CTS issues with setup and hold violations.
● After Route OPT stage issues with shorts, opens.

Internal

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