Q No Question Answer Domain Subdomain SubdomainLevel

1 What is the difference Physically Exclusive clocks: The Tree

Clock two clocks
Synthesi originate
CLOCK GROUPSfrom same cts source and4have only one entry po
Will scan chain reordering
in thehappen
design. during CTS?
At a time isonly one clock can exist in the design. These
2 scan chain reordering nClock Tree SynthesiSCAN CHAIN CTS clocks5won’t
3 After your CTS is compAfter CTS we are getting vClock Tree SynthesiTIMING VIOLATIONCTS 5
If you have setup 2k violation paths, hold 2k violation paths, What you
First preference is given Clock Tree SynthesiTIMING VIOLATIONrouting 4 will fix first and why?
4
5 why can’t we use AND We g use the ICG cell to stoClock Tree SynthesiCLOCK GATING CTS 5
6 The reason for double widClock Tree Synthesis cts 4
7 Which one is better is In hold perspective BufferClock Tree SynthesiBUFF AND INV cts 4
8 Why CSS block is diffic Because that block contain Clock Tree SynthesiCLOCKS 4
9 why we need to reduceif ID is not reduce or it Clock Tree SynthesiID 4
10 What are the crosstalkDue to the crosstalk we get theTree
Clock timing and noise
Synthesi Signalviolations
Integrity an Signal Inte 3
11 What did u mean by less The cells with equal rise aClock Tree SynthesiCTS Spec Files Illegal cells3
12 If crosstalk in false pa Then we should fixe thoseClock Tree SynthesiSignal Integrity an Signal Inte 3
13 What is Noise Analysis When one net is switching and Tree
Clock otherSynthesi
is in static condition
Signal Integrity then we get Noise
an Advanced l3 violation,
14 What you mean by Cros due to noise the functionality
Crosstalk: Clock Tree will Synthesi
be affected.CTS SpecAnalysing
Files these CMOS paths 3to fix those noise viola
15 How the Crosstalk effeCrosstalk
• When is Both
the undesirable
the netsClockare voltage
Switching
Tree Synthesitransitions
in same betweenFiles twoCMOS
direction:
CTS Spec or more 3adjacent nets through
16 In
How will you decreaseLatency:the data path if the netsClock Tree SynthesiCTS Quality Checks this the1logic is pulled and the
are switching in same direction, due to
17 User is running CTS to •The quality
Use theofminimum clock
results depends Clock level
on
Tree with
the balanced
flow
Synthesi being clock
used Files
CTS Spec branches
to synthesize the clock 1 trees
18 Explain frequency divide Flow1:
Clock dividers are ubiquitClock Tree SynthesiCTS Quality Checks 1
19 Tell me about Non-Def● Double width and double Clockspace:
Tree SynthesiSignal Integrity and Crosstalk 1
20 After the
How spacing helps in rwidth PNR stage
is more ➜ more if you will get
spaClock Tree timing
Synthesi /crosstalk/noise
Signal Integrity violations which1are difficult to fix at EC
and Crosstalk
21 Why Clock Buffers are To balance skew (i.e. flopClock Tree SynthesiSkew concept 3
22 How Shielding avoids ● High frequency noiseClock (or glitch) is coupled to VSS
Tree SynthesiSignal (or VDD)
Integrity andsince shielded
Crosstalk 3 layers are connecte
23 Why do we emphasize● on Coupling
Practically clockcapacitance
will be ideal remains
Clock the constant
in Tree Placement
Synthesisetup with VDD
stage weorassume
timing VSS.
analysisit could reach 4 in 0 time to every p
24 What is meant by insert The Setup time of a
● The insertion delay concept valid timing
Clock Tree path
comes depends on: Max
into picture indelay
SynthesiInsertion data network computation
clock tree synthesis.3 time vs clock e
25 Why don't we do routin ● While building
● Routing should be done the clock
Clock tree,
once CTS
Treeyour starts building the
design is at a Overview
SynthesiRouting clock from
stage where all of yourthe clock
3 data andto
source the logica
clock sinks.
26 What makes meeting tim ●
● During
What makes logic synthesis
it more Clockwe do
critical notSynthesiClock
than
Tree balance
a regularHFN and Clock
setup/hold
gating nets,
flop
concepts so atiming
to flop single
4 clock
path?portWhilemight be
buildin
27 Can we get 0 skew? Wh ● Now
If skew if the
is 0, thenfanout
all theof Clock
CG is more than it's driving
Tree SynthesiSkew capability then a small
concept 3 bigger tree (or maybe
28 While Doing CTS whichClock tree synthesis uses Clock Tree Synthesicts spec file 4
29 Explain Clock Tree OptiFive special clock optionsClock are available to address
Tree Synthesicts steps this situation. They greatly
4 expand your ability t
30 Clock phase:
Why to reduce Clock ● Reducing clock skewClock is notTreejust aSynthesiSkew
performanceconcept issue, it is also a manufacturing4 issue.
31 ● Scan based
What are all the Check● Hierarchical pins should testing, which
Clock is
not
Treecurrently
be defined the most popular
as a clockchecks
Synthesipre-CTS source way to structurally
4 test chips for man
32 ● Generated
What is latency? Give Source Latency clock should have a valid master
Clock Tree SynthesiCTS overview clock source A generated 3clock does not have a v
33 How should CRPR be trea ●
CRPRItand is also knownAnalysis
Crosstalk as source
Clocklatency. It is defined asANALYSIS
Tree SynthesiTIMING "the delay from the 4clock origin point to the
34 ● When you
What are the pros & coInverter: Less area & moreperform crosstalk
distance
Clock analysis using
can be driven. But
Tree SynthesiTIMING PrimeTime moreSI,switching.
ANALYSIS a change Goodin 4delay
fordue
pulseto width
crosstalk
anda
35 What happens if you ha ●
● In We other
havewords:
to build Inverter's
"clock current
Clocktree"
Treefor driving
the
SynthesiCTS capability
functional
ANALYSISclockis more
goingthan the buffer
through 4 pinwhen
D0 of MUX youfrom
compaits f
36 ● Set_dont_touch_network
Why do you focus on clReducing clock skew is not just on
a MUX/Z
performance pin
Clock Tree SynthesiSkew concept and then
issue, it build
is also CTS
a for test_clock
manufacturing 4 issue.
37 There are 3 flops. setu ●will borrow
Scan based testing,
timing on eithwhich
Clock is Treecurrently the most popular
SynthesiTIMING ANALYSIS way to structurally
4 test chips for man
38 At the post route stageAdjusting clock frequencyClock Tree SynthesiTIMING ANALYSIS 4
39 Why can’t we route the● In general routing will be done
Clock Tree based
SynthesiCTS on timing
ANDdrivenROUTING & it will be possible only after the cloc
SCENARIO3
40 What is the die/scribe ● If the
Special design
corner gets
cells arerouted
Clockfirst,
TreethenSynthesifor clock tree you
Integrated will Gating
Clock not getconc proper
4 routing resources an
41 What is the technique rteduce net length, IncreasClock Tree SynthesiSignal Integrity and Crosstalk 3
42 Sources of Clock Skew In-die Process, Voltage, Temperature (PVT) variation:
Clock Tree SynthesiUseful Skew 4
43 ● Different
What is Jitter and thei Clock jitter is theclock buffers
clock edge with different
inaccuracy channel
introduced
Clock Tree SynthesiCTS Overview lengths
by the clock signal generation
4 circuitry w.r.t id
44 ● Temporal power supply variations:
After clock tree syntheAfter clock tree synthesisClock Tree SynthesiTiming DRC's wrt Clock Path 3
45 What do you mean by cl When the clock edge devia Clock Tree Synthesis 2
46 What do you mean by Asi set of design issues sucClock Tree SynthesiSignal Integrity an signal integ3
47 What do you mean by D c ue to the cross-couplingClock Tree SynthesiSignal Integrity an signal integ3
48 How the spacing reduce When the spacing between Clock Tree SynthesiSignal Integrity an signal integ3
49 What is the difference 1-Crosstalk noise is- functionality Clock Tree failure (EX. whenIntegrity
SynthesiSignal the aggresor net isinteg
an signal switching
3 & victim net is id
50 What are the two mainThere c are two clock distribution systems: 1. Clock
Clock Tree SynthesiCTS Overview tree, also known as clock
clock tree 2 tree synthesis (cts). It
51 currently, we are using MultiPoint CTS
Are clock tree synthesiNo, clock tree synthesis aClock Tree SynthesiCTS Overview (a hybrid method of conventional
clock tree 2 CTS and clock mesh.)
52 What is the need for clclock gates will inserted during synthesis
Clock Tree , but placed inClock
SynthesiIntegrated placement
Gclockstage
gatin3, the main purpose to re
53 What is the clock grid The
The clock
main goalgating ofmeans
the clockcontrolling
Clock Treethe clock toggling
SynthesiCTS activity. Asclock
Overview the tree
clock 3drives a lot of elements
54 What is the difference Clock mesh distribution system: Clock Tree SynthesiCTS Overview clock tree 3
55 Expain clock jitter and 1.
ClockPresence
jitter isofthe
meshclock net, whichTree
e Clock smooths the arrival
SynthesiCTS Overview time difference
clockfromgener multiple
2 mesh drivers.
56 What are the advantage 1. By applying the doubleClock widthTreewe can avoid theSpec
SynthesiCTS em. Files ndrs 3
57 What Is Noise Margin?The 2. Byminimum
applying amount
double spacing no we
of Clock can avoid the cross-talk.
Tree SynthesiSignal Integrity an Electronic 2
58 what's the impact on th Before inserting inverter,Clock Tree Synthesis Half Cycle 2
59 Difference between cloClock skew is the clock reClock Tree Synthesis Useful Ske 1
60 Clock gating: Clock gating is a techniq Clock Tree Synthesis Advance Ti1
61 Generally in which stagPost CTS stage because skew Clockcontrol between the clock gated and
Tree Synthesis CTS no clock
Qualit 1 gated cells is difficult.
62 Drawbacks of clock gatCGC 1. You type depends
could get some on the pos edge/neg
glitches
Clock edgeclock
in theSynthesis
Tree gated triggered
if clockflip flop.Integrated
gating was not done 2 properly. Which co
63 2. Synchronization
What are the synchronSynchronous clocks: SameClock (skew balancing).
sourceTree In fact
orSynthesis gated and not
constant phase difference Basic gated circuits
(mainTimin1 are not generated
clocks and clocked at the sa
clocks
64 Async’hronous clocks:
What is the difference Stop pin also called as leaf Different clock sources
pin Tree Synthesis
Clock or no constant phase difference
CTS Qualit 3
65 Nonstop pin also
What are the inputs gi • Well floor planned and called as Placed
Clock Tree design
Synthesis CTS Overvi1
66 Why clock buffers and 1. •i Module
To Placement
maintain minimum Utilization
clock (which
pulse
Clock Tree Synthesis widthcontains the clock nets
CTSis Overvi3
set to 5–7 percent less than th
67 In which paths mainly w 2. To have timing margin for
Paths related to IO like I Clock Tree Synthesisthe both negative and positive edge
Routing ov2 flip flops i.e for half
triggered
68 What are the changes • Clock propagation Clock Tree Synthesis CTS Overvi2
69 What is the advantage•• Uncertainty
used for highvalues frequencyClockclocks
Tree Synthesis CTS Qualit 3
70 •
Will you use the bufferInverter: less than 1ps skew can be achieved
Clock Tree Synthesis CTS Overvi2
71 What are the NDR (Non•• Less Double areaspacing or extra Clockspacing
Tree Synthesis Synthesize1
72 • Shielding
Which metal did you usNext lower layer to the top twoTree
Clock metal layers (global routing layers).
Synthesis Routing ov3
73 What CTS SpecificationBecause
Skew Balancing:it has less resistance hence less
Clock Tree Synthesis RC delay. CTS Qualit 3
74 What is a difference b •There Give
is atight
major skew constraint
difference between
Clock Clock Tree & Reset Tree - in
Tree Synthesis CTS regards
Overvi3 to correct design practic
75 What is Static and DynClock uncertainties can beClock classified as
Tree Synthesisstatic or dynamic. StaticCTS Overvi2 does not vary or varie
uncertainty
76 On the other hand, dynamic
What is the difference Std Cells are logical cel Clock Tree Synthesisuncertainty varies with time. Dynamic power
Physical Ce3supply induced delay v
77 Design has no setup anYes we can but Clock Tree Synthesis Working Sm 3
78 Which Vt cells will you •Standard Power Vtconsumption
cells becauseClock will beTree
of The more
delay and leakage power compromise
Synthesis CTS Overvi2
79 When will you break thTheWhen less process
there are no variations compared
pathsClock
talking Treebetween to LVT
Synthesis theandmainHVT clock and generated
CTS Overvi2 clock. Define as through
80 What is Advantages and Use clock grouping
• Advantages of VirtualClock to balance the
Clocks: skew
Tree Synthesis between the generatedStandard
clocks/synchronous
D2 clocks.
81 • Directly
What is the significancSSO: we can change
The abbreviation of ClocktheTree
clockSynthesis
latency after CTS, No need Not to relave
change3 the input delay (inser
82 Why IO delays change IpO delays should be definClock Tree Synthesis CTS Overvi3
83 Which design you pref100 ps because 0ps will cClock Tree Synthesis CTS Overvi3
84 What might be the reas• Clock source might be far from the
Clock Tree Synthesis sinks CTS Overvi3
85 What are the effects o •Effects Low aredrive
crossstrength
talk noiseatClock
the
andsource point
delay.Synthesis
Tree Advance Ti1
86 Formation of capacitance
what is cross talk and Cross Talk : With the scaling between
of Tree
Clock the
the horizontal nets will create
Synthesis dimensions of wires, problem bythe
Advance chargeTi1 transfer
aspect from
ratio of theone net
horizon
87 When the signals in the neighboring wires switch,
How are the number ofLogic levels are based co Clock Tree SynthesiCTS timing and conSequential 1 the coupling capacitors cause transfer of charg
88 Whether optimization O wptimization will be doneClock Tree SynthesiBasics of PD flow CTS Steps 2
89 If you use normal buff For normal buffers the ri Clock Tree SynthesiCTS Quality ChecksCTS Qualit 2
90 How to balance insertii. upsizing the cells ii . Clock Tree SynthesiCTS Quality ChecksTiming Ana2
91 How does a skew group A skew group is a set of Clock Tree SynthesiCTS Overview Useful Ske 2
92 In CTS we have 50 corm In my project , at CTS sta Clock Tree SynthesiCTS Overview Timing Ana2
93 How will you synthesize Single clock-normal synthClock Tree SynthesiCTS overview CTS Overvi2
94 Have you worked on mu NO I didn’t worked on multi clock
Clock Tree entering
Synthesi points. But I have idea
CTS overview SDCif multiple 3 clock entry points ar
95 i) If clock is generated
we are getting clock n May be at that area we ha inside the block ,then the tool will
Clock Tree SynthesiCTS timing and conDRC and Sh2automatically balance the insertion dela
96 How did you handle mul Multiple clocks →synthesiClock Tree Synthesis Basics of Timing Analysis
97 Clock gating: ? ICG cell basically stops theClock clockTreepropagation through it when
SynthesiIntegrated Clock we PDapply a low 1 clock enable signal o
98 What are the types of cClock
H tree,gating
Binary, reduces
PDr, meshpower dissipation for the following
Clock Tree SynthesiCTS Overview reasons: CTS Overvi1
99 How the clock uncertaiThe clock uncertainty include/components: jitter (PLL), clock skew
Clock Tree SynthesiUncertainty (before
cts spec fil 2CTS), OCV (before post
100 How to decrease the cl To minimize the clock clock Tree SynthesiSkew & Insertion Dcts quality 2
101 Does order of clocks in Clock Tree SynthesiClock Specificationcts spec fil 2
102 No, the order of
How to decrease the s Cloning to balance the load clocks in a CTSTree
Clock clockSynthesiSkew
specification file does not cts affect the quality
quality 2 of the results. Th
103 Minimizing the
How will you calculate Generated clock latency wi clock levels with high drive strength
Clock Tree SynthesiLatency cell cts quality 2
104 What is Static and DynClock uncertainties can beclock classified as Static or dynamic. Static uncertainty
Tree SynthesiSkew 3 does not vary or varie
105 what is Hold Time Ske On Thethe big other hand,betwee
difference dynamic uncertainty varies
Clock Tree SynthesiSkew with time. DynamicTiming anal3supply induced delay v
power
106 How will you decide thGenerally it will be 100-200ps.It Clock Tree needs to more hold buffers/invTiming
SynthesiSkew as the anal
skew 3 increases. Bette
107 After CTS what will yo Uncertainty
• skew and values
insertionfor setup
delay and
(SOURCEhold after CTS
LATENCY) will
CLOCK TREE SYNTHCTS Quality Checks be generally given by foundry .uncertainty
4 va
108 • timing (drv’s , setup and hold)
What are the inputs fo• Placement netlist (.v) CLOCK TREE SYNTHCTS INPUTS & Spec Files 4
109 • Sdc
what is skew ? and whaa) skew is the difference between Clock Tree the capture latency
SynthesiUseful Skewand&launch latency. There are4 two types of
Skew reduction
110 what is cross talk? cross talk is the transfer of a voltage
CLOCK TREEtransition
SYNTHSignal fromIntegrity
multiple,Crosstalk
switching&net 4
111 what is EM? (aggressor ) to another
Electron migration: The gradual static or switching
CLOCK displacement net
TREE SYNTHSignal ( victim
of metal ) through a
atoms along with
Integrity,Crosstalk capacitor.
& Ethe charge4carriers due t
112 How to fix setup and ha) setup fixes: CTS Timing DRC's wrt Clock Path 4
113 Do you manually work yes , I solved the setup a CTS CTS Steps 4
114 What you will do in CT Before running CTS , we should
CTS provide some constraints
CTS overview like 4
115 What is useful skew ? If the clock is skewed intentionally CTS to resolveUseful
the violations,
Skew & Skew it is called as useful skew.
reduction 4
116 Have you fixed skew? I Improve
I didn’t the
fixed setup
skew. slack
But without
CTS effecting the hold. This can be
Useful Skew & Skew reduction done by pulling or pushing
4 the clo
117 After cts optimization By skewing the clock pathCTS we will fix the timing Timingviolations.
DRC's wrt Hold can Path
Clock be fixed by pushing4 (adding b
118 What you will fix first First we have to fix DRV’ CTS CTS Quality Checks 4
119 Which one is importantLatency is important thanCTS skew. If timing is met CTSfor both &
INPUTS scenarios
Spec Files then which one you 4 will choos
120 How to analyse timing • First look at starting and CTS ending points isCTS both are triggered
Quality Checks by the same clock 4 or different clo
121 What are NDR’s ? •NDR’s Then
( non see the slack
default routi value
CTS . if slack is violating more than
CTS INPUTS & Spec1ns Files
, then analyse why4it is violating t
122 Why clock buffers are Because the size of clock CTS CTS INPUTS & Spec Files 4
123 What is cross talk nois It is undesired change in CTS Signal Integrity,Crosstalk & E 4
124 What is cross talk dela When there is some delayCTS i Signal Integrity,Crosstalk & E 4
125 What is uncertainty be Pre CTS : CTS CTS Overview 4
126 what exactly happens iuncertainty
In post CTS ,=variousskew +optimizations
jitterCTS+ designwill margin post
be doneCTSthatCTS
Steps:
includes: meeting DRV’s , 4
127 setup and hold,
What is the difference The clocks originate fromCTSArea and Power optimization,
two different sources congestion
CTSare called&as
INPUTS reduction.
asynchronous
Spec Files clocks. Physically
4 exclu
128 Why do you apply MMM only
deratesoneare entry point in the
considered for
CTS design.
intra chip variationsCTSi.e PVT variations on a chip
Overview 4
129 Pulse width checks? Wh (process
Minimum pulse width checks CTS are done to ensure that width
CTS Quality Checks of the clock signal is wide 4
130 Once you setup and hold enough
Yes , surelyfor the cell’s to
we have internal
f CTS operations to complete. i.e.
CTS Quality Checks to get a stable output you 4need
131 Is fixing setup is diffic Setup fixing is more diffult, CTS because setup is CTS dependsQualitypurely
Checks on design. For fixing setup 4 violation ,
132 what is the use of cloc clock buffers and clock in CTS` CTS Steps 4
133 What are the technique Layer promotion, reduce Clock ne Tree SynthesiSignal Integrity and Crosstalk 3
134 Does the noise glitch No it doesn’t always impac Clock Tree SynthesiSignal Integrity and Crosstalk 4
135 Difference between cloc pros: equal rise & fall tr CTS cts 2
136 Why Buffers Are Used Ti o balance skew (i.e. flopCTS CTS Spec Files 2
137 How Shielding Avoids High frequency noise (or CTS Signal Integrity and Crosstalk 3
138 Disadvantage of clock The only disadvantage is more Clock space occupancy
Tree Synthesi Integrated Clock Gating conc 3
139 Pros and cons of cts s A. andMesh:
it may need More design time for closure
Clock Tree SynthesiCTS Overview 2
140 Pros and cons of ndr pri.xtalkMore routing
(glitch, resource
delay), net Clock Tree Synthesis 3
141 Why is mixing of vt typDesign variation are differClock Tree SynthesiAdvanced level timing analys 3
142 Cgc vios fixing techniq Automatically in tool: i. Clock Tree SynthesiUseful Skew 3
143 Checks at cts: Checks Clock Tree SynthesiCTS Quality Checks 4
A. All cells are legally placed, macro is already checked before placement
144 Cts inputs: A) db completed all placement checks
Clock Tree SynthesiCTS Overview 3
145 Checks after cts B) cts target
A) cells are legally placedClock Tree SynthesiCTS Quality Checks 3
146 Cts targets B) cells
A) usedinsertion
soc level as per input
delaygiven
is hard requirement
Clock Tree SynthesiCTS Overviewto meet (wifi chip max insertion delay
4 5ns)
147 How to decide on minim B) balance clocks only
A. Communication to other for the blocks
blocks
Clock communicating
Tree SynthesiUseful Skew 4
148 B. It is must to decide
What is the impact if A. Mem2reg paths for setup and apply
Clocktimingin design
Tree SynthesiUseful Skew 4
149 why are clock nets have B.extra
Reg2memspacing?paths for hold timing
Clock Tree Synthesis
150 Why is spacing preferreA. Shielding adds extra ground cap toSynthesiSignal
Clock Tree clock nets which is increasing
Integrity the load.
and Crosstalk 4
151 Is shielding or spacing B.
A)Shielding
this is softalso consumeClock
constraints; morewill
tool routing
follow resource.
wherever space is available
Tree SynthesiSignal Integrity and Crosstalk 5
152 Select the cells requireB) typically,
A. Main intree
clock congested Clock
areas,Treethese are not getting
SynthesiCTS followed.
Overview 5
153 B. Size_only
Fixing timing on clock gating vios: Clock Tree Synthesis
154 Cts build steps A) trace Clock Tree SynthesiCTS Overview 4
155 Cts checks: B) Drv
A. deletion
(max_transition, max_capacitance, fanout)
Clock Tree SynthesiCTS Quality Checks 4
156 Clock_gating vios: B.
A. Skew
Clock (local
gater and
alwaysglobal)
be at capture
Clock Tree side, it cannot
Synthesi launchClock
Integrated dataGating
to any conc
flops. I. Timing5 paths always
157 What is change in lower B.
A. What
Identify arehigh
thetoggle
basic problems
cells (clock
Clock with
Tree clock
nets: 200%,gating viosnets
signal
SynthesiAdvanced based
level in vcd,
timing tcf,5saif)
analys
158 B. More clock cells are
Outif the following tw 1. With huge insertion delay clustered
Clock and
Treeminimal skew. Overview
SynthesiCTS 5
159 2. With less insertion
Two clocks (clka and c 1. If pll generated these twodelay and
Clock more
clocks skew.
Treefreq/time Timing ofthe
period will
SynthesiAdvanced block
timing analys 5case 1.
be same.
level is better in Case 1. Re
160 2. 2. In constraints both the clocks get generated from different
Why clock gating is timiClock gating cells generalClock Tree Synthesi Integrated Clock Gating conc4 ports. So, tool sees them as differ
161 Setup Fixes during pla Setup Fixes During Placement ClockStage: 1. Timing path groups:
Tree SynthesiAdvanced We cananalys
level timing use this5 option
to resolve Setup timing during placement stage. Groups a set of paths or endpoints for cost functi
Timing Analysis