Basic Structure of Computer

1.1 COMPUTER TYPES

A computer can be defined as a fast electronic calculating machine that accepts the (data) digitized input
information process it as per the list of internally stored instructions and produces the resulting information.List of
instructions are called programs & internal storage is called computer memory. The different types of computers are
1. Personal computers: - This is the most common type found in homes, schools, Business offices etc., It is the
most common type of desk top computers with processing and storage units along with various input and
output devices.
2. Note book computers: These are compact and portable versions of PC
3. Work stations: These have high resolution input/output (I/O) graphics capability, but with same dimensions
as that of desktop computer. These are used in engineering applications of interactive design work.
4. Enterprise systems: These are used for business data processing in medium to large corporations that
require much more computing power and storage capacity than work stations. Internet associated with servers
has become a dominant worldwide source of all types of information.
5. Super computers: These are used for large scale numerical calculations required in the applications like
weather forecasting etc.,

1.2. FUNCTIONAL UNIT

Fig 1: Functional units of computer and control unit.

A computer consists of five functionally independent main parts input, memory, arithmetic logic unit (ALU), output
Input Output & Control units.

Input unit
Input device accepts the source program/high level language program/coded information/simply data is fed to a
computer through input devices keyboard is a most common type. Whenever a key is pressed, one corresponding
word or number is translated into its equivalent binary code over a cable & fed either to memory or processor.
Joysticks, trackballs, mouse, scanners etc are other input devices.

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 Memory unit
Its function is to store programs and data. It is basically to two types
1. Primary memory
2. Secondary memory
1. Primary memory: Associated with the processor and operates at the electronics speeds programs must be stored
in this memory while they are being executed. The memory contains a large number of semiconductors storage cells.
Each capable of storing one bit of information. These are processed in a group of fixed site called word. To access a
word in memory, a distinct address is associated with each word location. Addresses are numbers that identify memory
location. Number of bits in each word is called word length of the computer. Programs must reside in the memory
during execution. Instructions and data can be written into the memory or read out der the control of processor.
Ex: Random-access memory (RAM) & Read only memory (ROM):
2. Secondary memory: Is used where large amounts of data & programs have to be stored, particularly
information that is accessed infrequently.
Examples: Magnetic disks & tapes, optical disks (ie CD-ROM's), floppies etc.,

Arithmetic logic unit (ALU)

Most of the computer operators are executed in ALU of the processor like addition, subtraction, division,
multiplication, etc. the operands are brought into the ALU from memory and stored in high speed storage elements
called register. Then according to the instructions the operation is performed in the required sequence.

Output unit: Its basic function is to send the processed results to the outside world.
Examples : Printer, speakers, monitor etc.

Control unit
It is the nerve center that sends signals to other units and senses their states. The timing signals transfer of data
between input unit, processor, memory and output unit are generated by the control unit.

1.3 BASIC OPERATIONAL CONCEPTS

To perform a given task a program consisting of a list of instructions is stored in the memory. An Instruction consists
of 2 parts, 1) Operation code (Opcode) and 2) Operands.
The data/operands are stored in memory.
• The individual instruction are brought from the memory to the processor.
• Then, the processor performs the specified operation.
• Let us see a typical instruction
ADD LOCA, R0
• This instruction is an addition operation. The following are the steps to execute the instruction:
Step 1: Fetch the instruction from main-memory into the processor.
Step 2: Fetch the operand at location LOCA from main-memory into the processor.
Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the contents of register R0.
Step 4: Store the result (sum) in R0.
The same instruction can be realized using 2 instructions as:

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 Load LOCA, R1
Add R1, R0
The following are the steps to execute the instruction:
Step 1: Fetch the instruction from main-memory into the processor.
Step 2: Fetch the operand at location LOCA from main-memory into the register R1.
Step 3: Add the content of Register R1 and the contents of register R0.
Step 4: Store the result (sum) in R0. Transfers between the memory and the processor are started by sending the
address of the memory location to be accessed to the memory unit and issuing the appropriate control signals. The
data are then transferred to or from the memory.

Fig 2: Connections between the processor and the memory

The fig2 shows how memory & the processor can be connected.
MAIN PARTS OF PROCESSOR
The processor contains ALU, control-circuitry and many registers. The processor contains „n‟ general-purpose
registers R0 through Rn-1. The IR holds the instruction that is currently being executed.
• The control-unit generates the timing-signals that determine when a given action is to take place.
• The PC contains the memory-address of the next-instruction to be fetched & executed.• During the execution of an
instruction, the contents of PC are updated to point to next instruction.
• The MAR holds the address of the memory-location to be accessed. The MDR contains the data to be written into or
read out of the addressed location. MAR and MDR facilitates the communication with memory.
(IR :Instruction-Register, PC : Program Counter) (MAR : Memory Address Register, MDR: Memory Data Register)
STEPS TO EXECUTE AN INSTRUCTION
1) The address of first instruction (to be executed) gets loaded into PC.
2) The contents of PC (i.e. address) are transferred to the MAR & control-unit issues Read signal to memory.
3) After certain amount of elapsed time, the first instruction is read out of memory and placed into MDR.

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 4) Next, the contents of MDR are transferred to IR. At this point, the instruction can be decoded &executed.
5) To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a result,the operand is
transferred from memory into MDR, and then it is transferred from MDR to ALU.
6) Likewise required number of operands is fetched into processor.
7) Finally, ALU performs the desired operation.
8) If the result of this operation is to be stored in the memory, then the result is sent to the MDR.
9) The address of the location where the result is to be stored is sent to the MAR and a Write cycle is initiated.
10) At some point during execution, contents of PC are incremented to point to next instruction in the program.
1.4 BUS STRUCTURE
A bus is a group of lines that serves as a connecting path for several devices. A bus may be lines or wires.
• The lines carry data or address or control signal.
• There are 2 types of Bus structures: 1) Single Bus Structure and 2) Multiple Bus Structure.
1) Single Bus Structure: Because the bus can be used for only one transfer at a time, only 2 units can actively use
the bus at any given time. Bus control lines are used to arbitrate multiple requests for use of the bus.
Advantages:Low cost &) Flexibility for attaching peripheral devices.
2) Multiple Bus Structure
Systems that contain multiple buses achieve more concurrency in operations. Two or more transfers can be carried
out at the same time.
Advantage: Better performance.
Disadvantage: Increased cost.
Figure 3 : Single Bus Structure
The devices connected to a bus vary widely in their speed of operation. To synchronize their operational-speed,
buffer-registers can be used.
Buffer Registers
→ are included with the devices to hold the information during transfers.
→ prevent a high-speed processor from being locked to a slow I/O device during data transfers.
1.5 PERFORMANCE
The most important measure of the performance of a computer is how quickly execute programs. The speed of a
computer is affected by the design of
1) Instruction-set.
2) Hardware & the technology in which the hardware is implemented.
3) Software including the operating system.
Because programs are usually written in a HLL, performance is also affected by the compiler that translates

the compiler, machine instruction set and hardware in a co-ordinated way.The processor time depends on the
hardware involved in the execution of individual machine instructions. This hardware comprises the processor and
the memory which are usually connected by the bus as shown in the fig 4.

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 Figure 4 : The processor cache

Let us examine the flow of program instructions and data between the memory and the processor. At the start
of execution, all program instructions and the required data are stored in the main memory. As the execution
proceeds, instructions are fetched one by one over the bus into the processor, and a copy is placed in the cache later
if the same instruction or data item is needed a second time, it is read directly from the cache.
Processor clock
Processor circuits are controlled by a timing signal called a Clock.The clock defines regular time intervals called
Clock Cycles. To execute a machine instruction, the processor divides the action to be performed into a sequence
of basic steps such that each step can be completed in one clock cycle.
Let P = Length of one clock cycle,R = Clock rate. Relation between P and R is given by

1.4 BASIC PERFORMANCE EQUATION

Let T = Processor time required to executed a program.
N = Actual number of instruction executions.
S = Average number of basic steps needed to execute one machine instruction.
R = Clock rate in cycles per second.
The program execution time is given by If clock rate is 'R' cycles per second, the program execution time is given by

This is often referred to as the basic performance equation.

To achieve high performance, the computer designer must reduce the value of T, which means reducing N and S, and increasing R.
The value of N is reduced if source program is compiled into fewer machine instructions. The value of S is reduced if instructions
have a smaller number of basic steps to perform. The value of R can be increased by using a higher frequency clock.
Pipelining and super scalar operation
A substantial improvement in performance can be achieved by overlapping the execution of successive instructions
using a technique called pipelining.
Consider Add R1R2R3
This adds the contents of R1& R2 and places the sum in to R3
The contents of R1 & R2 are first transferred to the inputs of ALU. After the addition operation is performed, the
sum is transferred to R. The processor can read the next instruction from the memory, while the addition operation

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is being performed. Then of that instruction also uses, the ALU, its operand can be transferred to the ALU inputs at
the same time that the add instructions is being transferred to R
If multiple instructions pipelines are implemented in the processor. This means that multiple functional units are used
creating parallel paths through which different instructions can be executed in parallel such an arrangement, to start
the execution of several instructions in every clock cycle is called superscalar execution. CLOCK RATE

There are 2 possibilities for increasing the clock rate R:

1) Improving the IC technology makes logic-circuits faster.

This allows the clock period P to be reduced and the clock rate R to be increased.
2) Reducing the amount of processing done in one basic step also reduces the clock period P.
• In presence of a cache, the percentage of accesses to the main-memory is small.
Hence, much of performance-gain expected from the use of faster technology can be realized.
The value of T will be reduced by same factor as R is increased „.‟ S & N are not affected.
Instruction set CISC & RISC

1.5 PERFORMANCE MEASUREMENTS

It is very important to be able to access the performance of a computer, comp designers use performance
estimates to evaluate the effectiveness of new features. Hence measurement of computer performance using bench
mark programs is done to make comparisons possible, standardized programs must be used.
The performance measure is the time taken by the computer to execute a given bench mark. Initially some
attempts were made to create artificial programs that could be used as bench mark programs. A non profit
organization called SPEC- (system performance evaluation corporation) selects and publishes bench marks.
The 'SPEC' rating is computed as follows.
Running time on the reference computer
SPEC rating =

Running time on computer under test

SPEC rating = 50: The computer under test is 50 times as fast as reference-computer. The test is repeated for all the
programs in the SPEC suite.Then, the geometric mean of the results is computed.

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Let SPECi be the rating for program 'i' in the suite. The overall SPEC rating for the computer is given by

where „n‟ = number of programs in suite.

Since actual execution time is measured the SPEC rating is a measure of the combined effect of all factors affecting
performance, including the compiler, the OS, the processor, the memory of comp being tested.
Problem 1:
List the steps needed to execute the machine instruction:
Load R2, LOC
in terms of transfers between the components of processor and some simple control commands.Assume that the
address of the memory-location containing this instruction is initially in register PC.
Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory.
And, then wait until it has transferred the requested word into register MDR.
3. Transfer the instruction from MDR into IR and decode it.
4. Transfer the address LOCA from IR to MAR.
5. Issue a Read command and wait until MDR is loaded.
6. Transfer contents of MDR to the ALU.
7. Transfer contents of R0 to the ALU.
8. Perform addition of the two operands in the ALU and transfer result into R0.
9. Transfer contents of PC to ALU.
10. Add 1 to operand in ALU and transfer incremented address to PC.
Problem 2:
List the steps needed to execute the machine instruction:
Add R4, R2, R3
in terms of transfers between the components of processor and some simple control commands.
Assume that the address of the memory-location containing this instruction is initially in register PC.
Solution:
1. Transfer the contents of register PC to register MAR.
2. Issue a Read command to memory.
And, then wait until it has transferred the requested word into register MDR.
3. Transfer the instruction from MDR into IR and decode it.
4. Transfer contents of R1 and R2 to the ALU.
5. Perform addition of two operands in the ALU and transfer answer into R3.
6. Transfer contents of PC to ALU.
7. Add 1 to operand in ALU and transfer incremented address to PC.
Problem 3:
(a) Give a short sequence of machine instructions for the task “Add the contents of memory-location A
to those of location B, and place the answer in location C”. Instructions:
Load Ri, LOC and
Store Ri, LOC
are the only instructions available to transfer data between memory and the general purpose registers.
Do not change contents of either location A or B.
(b) Suppose that Move and Add instructions are available with the formats:
Move Location1, Location2 and
Add Location1, Location2
These instructions move or add a copy of the operand at the second location to the first location, overwriting the
original operand at the first location. Either or both of the operands can be in the memory or the general-purpose
registers. Is it possible to use fewer instructions of these types to accomplish the task in part (a)? If yes, give the
sequence.

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Solution:
(a)
Load A, R0
Load B, R1
Add R0, R1
Store R1, C
(b) Yes;
Move B, C
Add A, C

Problem 4:
A program contains 1000 instructions. Out of that 25% instructions requires 4 clock cycles,40%
instructions requires 5 clock cycles and remaining require 3 clock cycles for execution. Find the total
time required to execute the program running in a 1 GHz machine.
Solution:
N = 1000
25% of N= 250 instructions require 4 clock cycles.
40% of N =400 instructions require 5 clock cycles.
35% of N=350 instructions require 3 clock cycles.
T = (N*S)/R= (250*4+400*5+350*3)/1X109 =(1000+2000+1050)/1*109= 4.05 μs.
Problem 5:
For the following processor, obtain the performance.
Clock rate = 800 MHz
No. of instructions executed = 1000
Average no of steps needed / machine instruction = 20
Solution:

Problem 7:
(a) Suppose that execution time for a program is proportional to instruction fetch time. Assume that
fetching an instruction from the cache takes 1 time unit, but fetching it from the main-memory takes
10 time units. Also, assume that a requested instruction is found in the cache with probability 0.96.
Finally, assume that if an instruction is not found in the cache it must first be fetched from the mainmemory
into the cache and then fetched from the cache to be executed. Compute the ratio of program
execution time without the cache to program execution time with the cache. This ratio is called the
speedup resulting from the presence of the cache.
(b) If the size of the cache is doubled, assume that the probability of not finding a requested
instruction there is cut in half. Repeat part (a) for a doubled cache size.
Solution:
(a) Let cache access time be 1 and main-memory access time be 20. Every instruction that is
executed must be fetched from the cache, and an additional fetch from the main-memory must
be performed for 4% of these cache accesses.
Therefore,

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MACHINE INSTRUCTIONS & PROGRAMS
MEMORY-LOCATIONS & ADDRESSES
Numbers and character operands as well as instruction are stored in the computer memory. Memory consists of
many millions of storage cells (flip-flops). Each cell can store a bit of information i.e. 0 or 1 (Figure 5). Each group
of n bits is referred to as a word of information, and n is called the word length. The word length can vary from 8 to
64 bits. A unit of 8 bits is called a byte.
• Accessing the memory to store or retrieve a single item of information (word/byte) requires distinct
addresses for each item location. If 2k = no. of addressable locations then 2k addresses constitute the address-space
of the computer.
For example, a 24-bit address generates an address-space of 224 locations (16 MB).
BYTE Addressability
We now have three basic information quantities to deal with: the bit, byte and word. A byte is always 8 bits,
but the word length typically ranges from 16 to 64 bits. The most practical assignment is to have successive addresses
refer to successive byte

(a) A signed integer

(a) Four characters

Fig 5 Memory words

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Locations in the memory. This is the assignment used in most modern computers, the term byte-addressable memory is
use for this assignment. Byte locations have addresses 0,1,2, …. Thus, if the word length of the machine is 32 bits,
successive words are located at addresses 0,4,8,…., with each word consisting of four bytes.

Big-Endian and Little-Endian Assignments

There are two ways that byte addresses can be assigned across words, as shown in fig 6 & 7. The name big-endian
is used when lower byte addresses are used for the more significant bytes (the leftmost bytes) of the word. The name
little-endian is used for the opposite ordering, where the lower byte addresses are used for the less significant bytes
(the rightmost bytes) of the word.
In addition to specifying the address ordering of bytes within a word, it is also necessary to specify the
labeling of bits within a byte or a word. The same ordering is also used for labeling bits within a byte, that is, b7, b6,
…., b , from left to right.

(5) Big-endian assignment (6) Little-endian assiagnment

Word Alignment
Words are said to be Aligned in memory if they begin at a byte-address that is a multiple of the number of bytes in a word.
• For example,
If the word length is 16(2 bytes), aligned words begin at byte-addresses 0, 2, 4 . . . . .
If the word length is 64(2 bytes), aligned words begin at byte-addresses 0, 8, 16 . . . . .
• Words are said to have Unaligned Addresses, if they begin at an arbitrary byte-address.
Accessing Numbers, Characters and Character Strings
A number usually occupies one word. It can be accessed in the memory by specifying its word address. Similarly,
individual characters can be accessed by their byte-address.
• There are two ways to indicate the length of the string:
1) A special control character with the meaning "end of string" can be used as the last character in the string.
2) A separate memory word location or register can contain a number indicating the length of the string in bytes.
1.12 MEMORY OPERATIONS
Both program instructions and data operands are stored in the memory. To execute an instruction, the processor
control circuits that word (or words) containing the instruction to be transferred from the memory to the processor.
Operands and results must also be moved between the memory and the processor. Thus, two basic operations involving

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the memory are needed, namely, Load (or Read or Fetch) and Store (or Write).
Two memory operations are:
1) Load (Read/Fetch) &
2) Store (Write).
• The Load operation transfers a copy of the contents of a specific memory-location to the processor.
The memory contents remain unchanged.
• Steps for Load operation:
1) Processor sends the address of the desired location to the memory.
2) Processor issues „read‟ signal to memory to fetch the data.
3) Memory reads the data stored at that address.
4) Memory sends the read data to the processor.
• The Store operation transfers the information from the register to the specified memory-location.
This will destroy the original contents of that memory-location.
• Steps for Store operation are:
1) Processor sends the address of the memory-location where it wants to store data.
2) Processor issues „write‟ signal to memory to store the data.
3) Content of register (MDR) is written into the specified memory-location.
1.13 INSTRUCTIONS AND INSTRUCTION SEQUENCING
A computer must have instructions capable of performing four types of operations.
• Data transfers between the memory and the processor registers (MOV, PUSH, POP, XCHG).
• Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR, NOT).
• Program sequencing and control (CALL.RET, LOOP, INT).
• I/O transfers (IN, OUT).

Register Transfer Notation

Transfer of information from one location in the computer to another. Possible locations are memory locations
that may be involved in such transfers are memory locations, processor registers, or registers in the I/O subsystem.
Identify a location by a symbolic name standing for its hardware binary address.
Example, names for the addresses of memory locations may be LOC, PLACE, A, VAR2; processor
registers names may be R0, R5; and I/O register names may be DATAIN, OUTSTATUS, and so on. The contents of a
location are denoted by placing square brackets around the name of the location. Thus, the expressionMeans that
the contents of memory location LOC are transferred into processor register R1. As another example, consider the
operation that adds the contents of registers R1 and R2, and then places their sum into register R3. This action is
indicated as

This type of notation is known as Register Transfer Notation (RTN). Note that the right- hand side of an RTN
expression always denotes a value, and the left-hand side is the name of a location where the value is to be places,
overwriting the old contents of that location.

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 Assembly Language Notation
To represent machine instructions and programs, assembly language format is used.

Basic Instructions
The operation of adding two numbers is a fundamental capability in any computer. The statement
C=A+B
When the program containing this statement is compiled, the three variables, A, B, and C, are assigned to distinct
locations in the memory. We will use the variable names to refer to the corresponding memory location addresses. The
contents of these locations represent the values of the three variables.
Access to data in the registers is much faster than to data stored in memory-locations.

Access to data in the registers is much faster than to data stored in memory-locations.
• Let Ri represent a general-purpose register. The instructions: Load A,Ri
Store Ri,A
Add A,Ri
are generalizations of the Load, Store and Add Instructions for the single-accumulator case, in which
register Ri performs the function of the accumulator.
• In processors, where arithmetic operations as allowed only on operands that are in registers, the task
C<-[A]+[B] can be performed by the instruction sequence:
Move A,Ri
Move B,Rj
Add Ri,Rj
Move Rj,C

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 1.1.4 Instruction Execution and Straight-line sequencing
In the preceding discussion of instruction formats, we used to task C =[A]+[B] instruction. Fig 7 shows a possible
program segment for this task as it appears in the memory of a computer. Computer allows one memory operand per
instruction and has a number of processor registers. The three instructions of the program are in successive word
locations, starting at location i. since each instruction is 4 bytes long, the second and third instructions start at addresses
i + 4 and i + 8.

Fig7 C= [A]+[B]

The program is executed as follows:

1) Initially, the address of the first instruction is loaded into PC (Figure 7).
2) Then, the processor control circuits use the information in the PC to fetch and execute instructions, one at a time, in
the order of increasing addresses. This is called Straight-Line sequencing.
3) During the execution of each instruction, PC is incremented by 4 to point to next instruction.
• There are 2 phases for Instruction Execution:
1) Fetch Phase: The instruction is fetched from the memory-location and placed in the IR.
2) Execute Phase: The contents of IR is examined to determine which operation is to be performed. The specified-
operation is then performed by the processor.

1.4.5. Branching
Consider the task of adding a list of n numbers. Instead of using a long list of add instructions, it is possible to place a
single add instruction in a program loop, as shown in fig 8.
Program Explanation
• Consider the program for adding a list of n numbers (Figure 8).
• The Address of the memory-locations containing the n numbers are symbolically given as
NUM1,NUM2…..NUMn.
• Separate Add instruction is used to add each number to the contents of register R0.
• After all the numbers have been added, the result is placed in memory-location SUM.

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 Figure 8 : A Straight-line program for adding n numbers
Consider the task of adding a list of n numbers. Instead of using a long list of add instructions, it is possible to place a
single add instruction in a program loop, as shown in fig 9.
Consider the task of adding a list of „n‟ numbers (Figure 9).
• Number of entries in the list „n‟ is stored in memory-location N. Register R1 is used as a counter to determine the
number of times the loop is executed. Content-location N is loaded into register R1 at the beginning of the program.
• The Loop is a straight line sequence of instructions executed as many times as needed.The loop starts at location LOOP
and ends at the instruction Branch>0.
• During each pass,→ address of the next list entry is determined and that entry is fetched and added to R0.
• The instruction Decrement R1 reduces the contents of R1 by 1 each time through the loop. Then Branch Instruction
loads a new value into the program counter. As a result, the processor fetches and executes the instruction at this new
address called the Branch Target. A Conditional Branch Instruction causes a branch only if a specified condition is
satisfied. If the condition is not satisfied, the PC is incremented in the normal way, and the next instruction in sequential
address order is fetched and executed.

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 Figure 9 : Using a loop to add n numbers
Condition Codes
CONDITION CODES
• The processor keeps track of information about the results of various operations. This is
accomplished by recording the required information in individual bits, called Condition Code Flags.
• These flags are grouped together in a special processor-register called the condition code register
(or statue register).
• Four commonly used flags are:
1) N (negative) set to 1 if the result is negative, otherwise cleared to 0.
2) Z (zero) set to 1 if the result is 0; otherwise, cleared to 0.
3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0.
4) C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0.

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