TPSF12C3

SNVSCB8A – MARCH 2023 – REVISED APRIL 2023

TPSF12C3 Standalone, Active, EMI Filter for Common-mode Noise Mitigation in

Three-Phase, AC, Power Systems

1 Features 3 Description
• Functional Safety-Capable The TPSF12C3 is an active filter IC designed
– Documentation available to aid functional safety to reduce common-mode (CM) electromagnetic
system design interference (EMI) in three-phase AC power systems.
• Voltage-sense, current-inject active EMI filter The active EMI filter (AEF) configured with voltage
– Optimized for CISPR 11 and CISPR 32 Class B sense and current inject (VSCI) uses a capacitive
conducted EMI requirements multiplier circuit to emulate the Y-capacitors in a
– Low impedance for common-mode emissions conventional passive filter design. The device senses
over the applicable EMI frequency range (150 the high-frequency noise on each power line using a
kHz to 3 MHz) set of sense capacitors and injects noise-canceling
– 50%+ reduction in choke size, weight and cost currents back into the power lines using an injection
– Peak inject current of ±80 mA (typical) capacitor. The effective active capacitance is set by
– Amplifier with unity gain bandwidth of 113 MHz the circuit gain and the injection capacitance. The
• Wide supply voltage range of 8 V to 16 V AEF sensing and injection impedances use relatively
• Junction temperature range of –40°C to 150°C low capacitance values with small component
• Simple external configuration for three-phase AC footprints. The device includes integrated filtering,
power systems compensation and protection circuitry, and an enable
– Integrated sensing filter and summing network input.
– Low leakage current at line frequency
– Simplified compensation network The TPSF12C3 provides a very low impedance path
• Inherent protection features for robust design for CM noise in the frequency range of interest for
EMI measurement. Enabling up to 30 dB of CM noise
– Withstands surge of 6 kV (IEC 61000-4-5) with
reduction at the lower end of specified frequency
minimal external component count
ranges (for example, 150 kHz to 3 MHz) significantly
– Enable pin for remote ON and OFF control
reduces the size, weight and cost of the CM filter
– VDD voltage UVLO protection with hysteresis
implementation.
– Thermal shutdown protection with hysteresis
• 4.2-mm × 2-mm SOT-23 14-pin (DYY) package Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
2 Applications
TPSF12C3 DYY (SOT-23-THIN, 14) 4.20 mm × 2.00 mm
• Grid infrastructure – EV charging station
• HVAC motor control, aerospace and defense (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Welders, inverters and other industrial systems
• Telecom AC/DC rectifiers
L1

L2
3-phase AC/DC
AC source regulator
L3

PE N Chassis

CSEN1–CSEN4 CINJ

COMP1 COMP2
SENSE1
INJ

SENSE2
EN
SENSE3
VDD 12 V
SENSE4

REFGND IGND
TPSF12C3 Chassis (PE)

Simplified Schematic
EMI Mitigation Result

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.3 Feature Description.....................................................9
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................12
3 Description.......................................................................1 9 Applications and Implementation................................ 13
4 Revision History.............................................................. 2 9.1 Application Information............................................. 13
5 Device Comparison Table...............................................3 9.2 Typical Applications.................................................. 13
6 Pin Configuration and Functions...................................3 9.3 Power Supply Recommendations.............................20
7 Specifications.................................................................. 4 9.4 Layout....................................................................... 20
7.1 Absolute Maximum Ratings........................................ 4 10 Device and Documentation Support..........................23
7.2 ESD Ratings............................................................... 4 10.1 Device Support....................................................... 23
7.3 Recommended Operating Conditions.........................4 10.2 Documentation Support.......................................... 24
7.4 Thermal Information....................................................5 10.3 Receiving Notification of Documentation Updates..24
7.5 Electrical Characteristics.............................................5 10.4 Support Resources................................................. 24
7.6 System Characteristics............................................... 7 10.5 Trademarks............................................................. 24
7.7 Typical Characteristics................................................ 8 10.6 Electrostatic Discharge Caution..............................24
8 Detailed Description........................................................9 10.7 Glossary..................................................................24
8.1 Overview..................................................................... 9 11 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram........................................... 9 Information.................................................................... 24

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2023) to Revision A (April 2023) Page
• Changed status from Advance Information to Production Data......................................................................... 1

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5 Device Comparison Table

JUNCTION TEMPERATURE
DEVICE ORDERABLE PART NUMBER PHASES GRADE
RANGE
TPSF12C3 TPSF12C3DYYR 3 Commerical –40°C to 150°C
TPSF12C1 TPSF12C1DYYR 1 Commercial –40°C to 150°C
TPSF12C3-Q1 TPSF12C3QDYYRQ1 3 Automotive –40°C to 150°C
TPSF12C1-Q1 TPSF12C1QDYYRQ1 1 Automotive –40°C to 150°C

6 Pin Configuration and Functions

NC 1 14 IGND
VDD 2 13 INJ
NC 3 12 NC
SENSE1 4 11 COMP2
SENSE2 5 10 COMP1
SENSE3 6 9 REFGND
SENSE4 7 8 EN

Not to scale

Figure 6-1. 14-Pin SOT-23-THIN DYY Package (Top View)

Table 6-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
1, 3, 12 NC – No internal connection. Tie to the GND plane on the PCB.
2 VDD P Power supply for IC. Bypass to IGND with a 1-µF X7R ceramic capacitor.
4 SENSE1 I Sense input (power line 1, 2, 3, or neutral)
5 SENSE2 I Sense input (power line 1, 2, 3, or neutral)
6 SENSE3 I Sense input (power line 1, 2, 3, or neutral)
7 SENSE4 I Sense input (power line 1, 2, 3, or neutral)
8 EN I Enable signal to activate noise cancellation
9 REFGND G Reference ground (Kelvin connected to IGND)
10 COMP1 I Connection 1 for external compensation circuit
11 COMP2 I Connection 2 for external compensation circuit
13 INJ O Injection signal output
14 IGND G Injection ground

(1) P = Power, G = Ground, I = Input, O = Output

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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN MAX UNIT
Pin voltage VDD to IGND and REFGND –0.3 18 V
Pin voltage SENSE1, SENSE2, SENSE3, SENSE4 to REFGND –5.5 5.5 V
Pin voltage COMP1 to IGND and REFGND –0.3 5.5 V
Pin voltage COMP2 to IGND and REFGND –0.3 15 V
Pin voltage INJ to IGND –0.3 VVDD V
Pin voltage EN to IGND and REFGND –0.3 18 V
Pin voltage IGND to REFGND –0.3 0.3 V
Sink current INJ 150 mA
Source current INJ 150 mA
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 ((2)) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN NOM MAX UNIT
VVDD VDD voltage range 8 12 16 V
VINJ Output voltage range 2.5 VVDD – 2 V
VSENSE Sense voltage range –5 5 V
VEN Pin voltage 0 16 V
IINJ Output current range Source and sink magnitude 80 mA
TA Operating ambient temperature –40 105 °C

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7.4 Thermal Information

DYY (SOT-23-THIN)
THERMAL METRIC(1) UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 94 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43 °C/W
RθJB Junction-to-board thermal resistance 30 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 28 °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

Limits apply over the junction temperature (TJ) range of –40°C to 150°C, unless otherwise stated. Minimum and maximum
limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at
TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VVDD = 12
V(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
SENSE1, SENSE2, SENSE3, and
SENSE4 grounded, VEN = 5 V, 8 V ≤ 6.25 13.2 25.5
VVDD ≤ 16 V
IQ VDD quiescent current mA
SENSE1, SENSE2, SENSE3, and
SENSE4 grounded, VEN = 5 V, VVDD = 11 13.2 15.5
12 V, TJ = 25°C
ISD VDD shutdown supply current VEN = 0 V 55 µA
SUPPLY VOLTAGE UVLO
VVDD-UV-R UVLO rising threshold VVDD rising 7.35 7.7 7.95 V
VVDD-UV-F UVLO falling threshold VVDD falling 6.4 6.7 7.0 V
VVDD-UV-HYS UVLO hysteresis 0.97 V
ENABLE
VEN-H EN voltage high 2.2 V
VEN-L EN voltage low 0.8 V
REN EN pin pull-up resistance to VDD VEN = 0 V 850 kΩ
IEN-LKG EN input leakage current VEN = 12 V 840 nA
INPUT FILTER NETWORK
CSEN = 2 µF(2), 60 Hz –44
Gain from shorted power lines through C (2)
SEN = 2 µF , 50 kHz –4
ACM single sense cap, CSEN, to COMP1 vs. dB
REFGND CSEN = 2 µF(2), 500 kHz(3) –2
CSEN = 2 µF(2), 1 MHz(3) –1

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7.5 Electrical Characteristics (continued)

Limits apply over the junction temperature (TJ) range of –40°C to 150°C, unless otherwise stated. Minimum and maximum
limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at
TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VVDD = 12
V(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4, –71
CSEN1 = CSEN3 = 1 µF(2), 60 Hz
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4, –59
CSEN1 = CSEN3 = 1 µF(2), 1 kHz
SENSE1 shorted to SENSE2,
Gain from differential signal applied to
ADM SENSE3 shorted to SENSE4, –42 dB
SENSE lines to COMP1 vs. REFGND
CSEN1 = CSEN3 = 1 µF(2), 500 kHz(3)
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4, –43
CSEN1 = CSEN3 = 1 µF(2), 1 MHz(3)
SENSE1 shorted to SENSE2,
SENSE3 shorted to SENSE4, –35
CSEN1 = CSEN3 = 1 µF(2), 10 MHz(3)
AMPLIFIER
ADC DC gain 52 58 69 dB
fBW Unity gain bandwidth(3) 113 MHz
fBW40 40 dB gain frequency 1 MHz
VOFST COMP1 offset voltage 2 V
Maximum output voltage for linear
VINJ-MAX COMP2 to INJ gain > 36 dB VVDD – 2 V
operation(3)
Minimum output voltage for linear
VINJ-MIN COMP2 to INJ gain > 36 dB 2.5 V
operation(3)
VINJ = VVDD – 2 V 80 mA
IINJ-MAX-OP INJ current at linearity limits(3)
VINJ = VIGND + 2.5 V –80 mA
PSRR
10 pF in parallel with the series
PSRR10 combination of 10 nF and 2 kΩ 0
between COMP1 and COMP2, 10 kHz
10 pF in parallel with the series dB
combination of 10 nF and 2 kΩ
PSRR100 6
between COMP1 and COMP2, 100
kHz
STARTUP
Time from VDD = EN applied until
tW Startup delay(3) 43 ms
output valid
tSU EN high to valid output 42 ms
tSD EN low to stop output signal 0.32 µs
THERMAL SHUTDOWN
TJ-SHD Thermal shutdown threshold(3) Temperature rising 175 °C
TJ-HYS Thermal shutdown hysteresis(3) 20 °C

(1) MIN and MAX limits are 100% production tested at 25ºC unless otherwise specified. Limits over the operating temperature range
verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality
Level (AOQL).
(2) Capacitance chosen for effective test only. Do not use this capacitance in applications.
(3) Parameter specified by design, statistical analysis and production testing of correlated parameters.

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7.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C and VVDD = 12 V only. Specifications in the minimum (MIN) and maximum (MAX)
columns apply to the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications
are not ensured by production testing.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
ISUPPLY Input supply current with INJ loaded 15 mA

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7.7 Typical Characteristics

VVDD = VEN = 12 V, unless otherwise specified.

80 30
Shutdown Quiescent Current (A)

25

Active Quiescent Current (mA)

60
20

40 15

10
20
5 VVDD = 8 V
VVDD = 12 V
VVDD = 16 V
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
VEN = 0 V Figure 7-2. Quiescent Supply Current vs.
Figure 7-1. Shutdown Supply Current vs. Temperature
Temperature
10 2
VDD UVLO Threshold Voltage (V)

8
EN Threshold Voltage (V)

1.5

6
1

0.5
2
Rising Rising
Falling Falling
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)

Figure 7-3. VDD UVLO Thresholds vs. Temperature Figure 7-4. EN Threshold vs. Temperature
0 0

-20 -20
CM Gain (dB)

DM Gain (dB)

-40 -40

-60 -60

-80 -80
0.01 0.1 1 10 100 1000 10000 1 10 100 1000 10000
Frequency (kHz) Frequency (kHz)
Figure 7-5. Input Filter Response – Common Mode Figure 7-6. Input Filter Response – Differential
Mode

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8 Detailed Description
8.1 Overview
The TPSF12C3 is an active electromagnetic interference (EMI) filter that is designed to reduce common-mode
(CM) conducted emissions in off-line power converter systems. Using a VSCI architecture, the device senses the
high-frequency noise on each power line using a set of Y-rated capacitors, CSEN1-4, then injects noise-canceling
currents back into the power lines using a Y-rated capacitor, CINJ, along with a damping circuit that ensures
stability. The device includes integrated filtering, compensation and protection circuitry.
The TPSF12C3 provides a low-impedance shunt path for CM noise in the frequency range of interest for EMI
measurement. This feature can achieve approximately 15 to 30 dB of CM attenuation over the applicable
frequency range (for example, 100 kHz to 3 MHz) helping to reduce the size of CM chokes, typically the largest
components in the filter.
The TPSF12C3 operates over a supply voltage range of 8 V to 16 V and can withstand 18 V. The device
features include:
• Internal circuitry that simplifies compensation and design
• Built-in supply voltage UVLO to ensure proper operation
• Built-in thermal shutdown protection
• An EN input that allows power saving when the system is idling
The active EMI filter circuit significantly reduces EMI filter cost, size, and weight, while helping to meet CISPR 11
and CISPR 32 Class B limits for conducted emissions. Leveraging a pin arrangement designed for simple layout
that requires relatively few external components, the TPSF12C3 is specified for maximum ambient and junction
temperatures of 105°C and 150°C, respectively.
8.2 Functional Block Diagram

Inject stage

Neutral

INJ

VDD
REF

EN

REFGND IGND
GND GND GND

8.3 Feature Description

8.3.1 Active EMI Filtering
A compact and efficient design of the input EMI filter is one of the main challenges in high-density switching
regulator design and is critical to achieving the full benefits of electrification in industrial, enterprise, aerospace

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and other highly constrained system environments. For AC-input applications in general, CM chokes and Y-
capacitors provide CM filtering, whereas the leakage inductance of the CM chokes and the X-capacitors provide
DM filtering. However, CM filters for such applications may have limited Y-capacitance due to touch-current
safety requirements and thus require large-sized CM chokes to achieve the requisite attenuation – ultimately
resulting in filter designs with bulky, heavy and expensive passive components. Fortunately, the deployment of
active filter circuits enable more compact filter solutions for next-generation power conversion systems.
8.3.1.1 Schematics
Figure 8-1 and Figure 8-2 show schematics for conventional two-stage passive EMI filters with and without
neutral, respectively, in kilowatt-scale, grid-connected applications. L, N and PE refer to the respective live,
neutral and protective earth connections. Multistage filters as shown provide high roll-off and are widely used
in high-power AC line applications where CM noise is often more challenging to mitigate than DM noise. The
low-order switching harmonics usually dictate the size of the reactive filter components based on the required
corner frequency (or multiple corner frequencies in multistage designs).
Also included in Figure 8-1 and Figure 8-2 are the corresponding active filter designs. The active circuit replaces
the bank of Y-capacitors positioned between the CM chokes with a three-phase AEF circuit using the TPSF12C3
to provide a lower impedance shunt path for CM currents. The sense pins of the TPSF12C3 interface with
the power lines using a set of Y-rated sense capacitors, typically 680 pF, and feed into an internal high-pass
filter and signal combiner. The IC rejects both line-frequency (50-Hz or 60-Hz) AC voltage as well as DM
disturbances, while amplifying high-frequency CM disturbances and maintaining closed-loop stability using an
external tunable damping circuit.
LCM1 Passive filter circuit LCM2
L1
CX1 CX4 CX7
L2
3-phase
3-phase
AC supply
CX2 CX5 CX8 AC/DC
L3 regulator
CX6 CX9
N
CX3
PE Chassis
CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8

4-5 times 4-5 times

lower lower
inductance inductance

LCM1-AEF LCM2-AEF
Active filter circuit
L1
CX1 CX4 CX7
L2 3-phase
3-phase CX2 CX8
AC supply
CX5 AC/DC
L3 regulator

CX3 CX6 CX9

N Chassis
PE

CSEN3 CSEN1 CG1 R CINJ

G
CSEN4 CY1 CY2 CY3 CY4
CSEN2
CG2
CD3 RD3
COMP1 COMP2 RD1A CD1
SENSE1 INJ

SENSE2 RD1 DINJ

= 3-phase source TPSF12C3
SENSE3 EN CD2
= 3-phase AC/DC 12 V
SENSE4 VDD RD2
= Three-phase AEF IC CVDD
REFGND IGND
= Sense, inject capacitors

Figure 8-1. Circuit Schematic of a Three-Phase, Four-Wire Passive Filter and Corresponding Active Filter
Solution for CM Attenuation

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LCM1 Passive filter circuit LCM2

L1
CX1 CX4 CX7 3-phase
3-phase L2
AC/DC
AC supply
CX2 CX5 CX8 regulator
L3

PE CX3 CX6 CX9 Chassis

CY1 CY2 CY3 CY4 CY5 CY6

4-5 times 4-5 times

lower lower
inductance inductance

LCM1-AEF Active filter circuit LCM2-AEF

L1
CX1 CX4 CX7 3-phase
3-phase L2 AC/DC
AC supply
CX2 CX5 CX8 regulator
L3

PE CX3 CX6 CX9 Chassis

CSEN3 CSEN1 CG1 R CINJ

G
CY1 CY2 CY3
CSEN2
CG2
CD3 RD3
COMP1 COMP2 RD1A CD1
SENSE1 INJ

SENSE2 RD1 DINJ

= 3-phase source TPSF12C3
SENSE3 EN CD2
= 3-phase AC/DC 12 V
SENSE4 VDD RD2
= Three-phase AEF IC CVDD
REFGND IGND
= Sense, inject capacitors

Figure 8-2. Circuit Schematic of a Three-Phase, Three-Wire Passive Filter and Corresponding Active
Filter Solution for CM Attenuation

The X-capacitors placed between the two CM chokes effectively provide a low-impedance path between the
power lines from a CM standpoint, typically up to low-MHz frequencies. This allows current injection onto one
power line, typically neutral, using only one inject capacitor. If the three-phase filter is a three-wire system
without neutral as shown in Figure 8-2, the SENSE4 pin of the TPSF12C3 ties to ground and the inject capacitor
couples through a star-point connection of the X-capacitors.
8.3.2 Capacitive Amplification
An AEF circuit for CM noise mitigation fundamentally either amplifies the apparent inductance of a CM choke or
the apparent capacitance of a Y-capacitor over the frequency range of interest. A VSCI AEF circuit configured
for CM attenuation uses an amplifier stage as a capacitive multiplier of the inject capacitor, CINJ. This higher
value of the active capacitance supports lower values for the CM chokes to achieve a target attenuation. More
specifically, the amplified Y-capacitance enables a reduction of each CM choke inductance by up to 80% (while
keeping the filter corner frequencies effectively unchanged), resulting in lower size, weight, and cost of the CM
chokes.
Capacitive multiplication of the inject capacitance occurs over a relevant frequency range for low- and mid-
frequency emissions, while not impacting the value at low frequency applicable for touch current measurement.
The total capacitance of the sense and inject capacitors (highlighted in yellow in Figure 8-1 and Figure 8-2) is
kept less than or equal to that of the replaced Y-capacitors in the equivalent passive filter, which results in the
total line-frequency leakage current remaining effectively unchanged or reduced.

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8.3.3 Integrated Line Rejection Filter

The TPSF12C3 has a built-in input line filter. The high-pass filter stage attenuates the large line-frequency (50
Hz or 60 Hz) components of the power-line voltages, both line-to-line and line-to-earth, thus maximizing the
useful voltage range of the low-voltage output at INJ.
The circuit also sums the signals in a CM combiner, rejecting the DM components of the voltages and extracting
a signal that represents the CM noise signature without line-frequency components. Combined with the action of
the high-pass filter, the net result is that the COMP1 pin voltage represents the sensed high-frequency CM noise
that the device attempts to cancel. Because the entire filter is integrated in the device, matching is better than
what can be achieved using discrete components.
8.3.4 Compensation
The TPSF12C3 contains partial internal compensation that, when combined with two capacitors and a
resistor between COMP1 and COMP2, forms a lead-lag network. This internal network allows fewer external
components to be used.
8.3.5 Remote Enable
The TPSF12C3 has an enable input, EN, that allows the device to be shut down, drastically reducing power
consumption during intervals when EMI mitigation is not required. The typical quiescent current consumption is
13.2 mA and 55 μA when the device is enabled and disabled, respectively. Because many designs may not use
this feature, a 850-kΩ pullup resistor connects internally between VDD and EN, allowing the EN pin to be left
open.
In addition, INJ is pulled low when the device is disabled to reduce the effective resistance in series with CINJ.
8.3.6 Supply Voltage UVLO Protection
To ensure that the TPSF12C3 operates safely while VDD is powered on and off as well as during brownout
conditions, this device has a built-in UVLO protection to provide predictable behavior while VDD is below its
operating voltage. UVLO releases when the VDD voltage exceeds 7.7 V (typical), allowing normal operation.
UVLO engages if the VDD voltage falls below approximately 6.7 V (typical). There is approximately 1 V of UVLO
hysteresis.
8.3.7 Thermal Shutdown Protection
The TPSF12C3 provides built-in overtemperature protection that shuts down the device if the junction
temperature exceeds approximately 175°C. After the junction temperature decreases by approximately 20°C,
the device restarts. This process is repeated until the ambient temperature or power dissipation is reduced. The
device has a relatively low thermal time constant and can cycle into and out of thermal shutdown at a high rate
during a sustained overtemperature condition.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides ON and OFF control for the TPSF12C3. When the EN voltage is below approximately 0.8
V, the device is in shutdown mode. Most internal circuitry is shutdown. The quiescent current in shutdown mode
drops to 55 µA (typical). The TPSF12C3 also employs VDD internal undervoltage protection. If the VDD voltage
is below its UVLO threshold, the device remains off. The INJ output pulls to ground while in shutdown mode.
8.4.2 Active Mode
The TPSF12C3 is in active mode when VVDD is above its UVLO threshold, EN is high, and there is no
overtemperature fault. The simplest way to enable operation is to connect EN to VDD, which allows startup
when the applied supply voltage exceeds the UVLO threshold voltage. In this mode, the device amplifies signals
on COMP2 and outputs the amplified signal on the INJ pin.

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9 Applications and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The TPSF12C3 common-mode AEF IC helps to improve the CM EMI signature of three-phase AC power
systems. The device provides a very low impedance path for CM noise in the frequency range of interest for EMI
measurement and helps to meet prescribed limits for EMI standards, such as:
• CISPR 11, EN 55011 – Industrial, Scientific and Medical (ISM) applications
• CISPR 25, EN 55025 – Automotive applications
• CISPR 32, EN 55032 – Multimedia applications
To expedite and streamline the process of designing of a TPSF12C3-based solution, a comprehensive
TPSF12C3 quickstart calculator is available by download to assist the system designer with component selection
for a given application.
9.2 Typical Applications
For the circuit schematic, bill of materials, PCB layout files, and test results of a TPSF12C3-powered
implementation, see the TPSF12C3 EVM.
9.2.1 Design 1 – AEF Circuit for Grid Infrastructure Applications
Figure 9-1 shows a schematic diagram of a 10-kW high-density AC/DC regulator with conventional two-stage
passive EMI filter. The CM chokes and Y-capacitors provide CM filtering, whereas the leakage inductance of the
CM chokes and the X-capacitors provide DM filtering. Similar to TI reference designs TIDA-01606, the circuit
uses a three-phase power-factor correction (PFC) stage with SiC power MOSFETs.
The PFC stage runs at a fixed switching frequency of 100 kHz. Even though the use of GaN or SiC power
switches enables a high power density, the conventional passive EMI filter typically occupies over 20% of the
total solution size.
LCM1 LCM2

L1
CX1 CX4 CX7
L2 3-phase
3-phase
CX2 CX5 CX8 AC/DC
AC supply
L3 regulator
CX3 CX6 CX9
N Chassis
PE
CY1 CY2 CY3 CY4 CY5 CY6 CY7 CY8

Figure 9-1. Circuit Schematic of a Three-phase AC/DC Regulator With a Conventional Two-Stage Passive
EMI Filter

The AC/DC stage increases the CM EMI signature based on the high dv/dt of the SiC power switches as well as
the various switch-node parasitic capacitances to chassis ground.
This application example replaces the four Y-capacitors, designated as CY1, CY2, CY3 and CY4 in Figure 9-1, with
a three-phase AEF circuit using the TPSF12C3. See Figure 9-2. The AEF circuit provides effective capacitive
multiplication of the inject capacitor, which reduces the inductance values to maintain the target LC corner

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frequencies and thus the size, weight, and cost of the CM chokes, now designated as LCM1-AEF and LCM2-AEF.
The total capacitance of the sense and inject capacitors is kept less than or equal to that of the replaced Y-
capacitors, which results in the total line-frequency leakage current remaining effectively unchanged or reduced.
AC mains LCM1-AEF LCM2-AEF

L1
CX1 CX4 CX7
L2 3-phase
3-phase
CX2 CX5 CX8 AC/DC
AC supply
L3 regulator
CX3 CX6 CX9
PE N Chassis

CY1–CY4
CG1 RG
CSEN3 CSEN1
CINJ
CSEN4 CSEN2 CG2
U1
CD3 RD3
RD1A CD1
COMP1 COMP2

SENSE1 INJ

SENSE2
RD1 DINJ
= 3-phase source
TPSF12C3
SENSE3 EN From MCU CD2
= 3-phase AC/DC Chassis-referred
power supply
SENSE4 VDD RD2
= 3-phase AEF IC CVDD
REFGND IGND
= Sense, inject capacitors

Chassis (PE)

Figure 9-2. Circuit Schematic of a Three-phase Regulator With AEF Circuit Connected

9.2.1.1 Design Requirements

Table 9-1 shows the intended operating parameters for this application example. Also included is the total
Y-rated filter capacitance that is allowed in order to meet the applicable touch current fault specification.
Table 9-1. Design Parameters
DESIGN PARAMETER VALUE
AC input voltage 230 V L-N or 400 V L-L (RMS)
AC input line frequency 47 Hz to 63 Hz
DC output voltage range 600 V to 1 kV
DC output current (max) 18 A
Rated output power 10 kW
AC/DC stage switching frequency 100 kHz
Total Y-rated filter capacitance (maximum) 10 nF

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9.2.1.2 Detailed Design Procedure

Table 9-2 gives the selected component values, which are the same as those used in the TPSF12C3 EVM. This
design uses a TVS diode placed at the low-voltage side of the inject capacitor for clamping during input surge
conditions.
Table 9-2. AEF Circuit Components for Application Circuit 1
REFERENCE
QTY SPECIFICATION MANUFACTURER(1) PART NUMBER
DESIGNATOR
CSEN1, CSEN2,
4 Capacitor, ceramic, 680 pF, 300 VAC, Y2 MuRata DE2B3SA681KN3AX02F
CSEN3, CSEN4 (2)
CINJ (2) 1 Capacitor, ceramic, 4.7 nF, 300 VAC, Y2 MuRata DE2E3SA472MA3BX02F
CD1 (2) 1 Capacitor, ceramic, 4.7 nF, 50 V, 0603 Various –
CD2 (2) 1 Capacitor, ceramic, 22 nF, 50 V, 0603 Various –
CD3 1 Capacitor, ceramic, 4.7 nF, 50 V, 0603 Various –
CG1 1 Capacitor, ceramic, 10 nF, 50 V, 0603 Various –
CG2 1 Capacitor, ceramic, 10 pF, 50 V, 0603 Various –
CVDD 1 Capacitor, ceramic, 1 µF, 25 V, X7R, 0603 Various –
DINJ 1 TVS diode, bidirectional, 24 V, SOD-323 Eaton STS321240B301
RD1 1 Resistor, 1 kΩ, 0.1 W, 0603 Various –
RD1A 1 Resistor, 50 Ω, 0.1 W, 0603 Various –
RD2 1 Resistor, 200 Ω, 0.1 W, 0603 Various –
RD3 1 Resistor, 698 Ω, 0.1 W, 0603 Various –
RG 1 Resistor, 1.5 kΩ, 0.1 W, 0603 Various –
TPSF12C3 common-mode AEF IC for three-phase AC
U1 1 Texas Instruments TPSF12C3DYYR
power systems

(1) See the Third-Party Products Disclaimer.

(2) Check the effective capacitance value based on the applied voltage and operating temperature.

More generally, the TPSF12C3 AEF IC is designed to operate with a wide range of passive filter components
and system parameters.
9.2.1.2.1 Sense Capacitors
The sense pins of the TPSF12C3 feed into a high-pass filter and signal combiner within the IC, which rejects the
line-frequency and DM components of the power line voltages, extracting the high-frequency CM component.
The sense pins externally interface to the power lines using Y-rated capacitors, designated as CSEN1, CSEN2,
CSEN3 and CSEN4 in Figure 9-2. Choose Y2-rated sense capacitors of 680 pF, 300 VAC in this application to
establish voltages at the SENSE pins of less than 1-V peak-to-peak when operating at maximum line voltage.
9.2.1.2.2 Inject Capacitor
The INJ node interfaces to a power line using a Y-rated capacitor, designated as CINJ in Figure 9-2. Choose a
Y2-rated inject capacitor of 4.7 nF, 300 VAC in this design to accommodate an AC voltage swing at INJ with at
least a 2.5-V margin of headroom from the positive and negative supply rails. The INJ pin biases at half the VDD
supply voltage. Assuming a 12-V supply rail and allowing 2.5 V of upper and lower headroom, this implies that a
swing of ±3.5 V is available around the DC operating midpoint.

Note
Many commercially available Y-rated capacitors yield an effective capacitance that derates
significantly with operating temperature. The effective capacitance value can be much lower than
the nameplate capacitance, particularly when operating near the boundaries of the rated operating
temperature range. Select the dielectric of the sense and inject capacitors to meet the required
temperature range. Depending on the implementation, lower than expected sense and inject
capacitances can affect the stability performance.

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9.2.1.2.3 Compensation Network

The CM noise signal derived from the internal sensing filter and summation network of the TPSF12C3 is
internally inverted and amplified by a gain stage. The components between the COMP1 and COMP2 pins of the
IC, designated as as RG, CG1 and CG2 in Figure 9-2, set the gain characteristic.
More specifically, resistor RG establishes a high midband AEF gain at frequencies where EMI filtering is required.
Capacitor C G1 increases the impedance of that branch at low frequencies, which sets a lower AEF amplifer gain
to further reject line-frequency components appearing at the INJ output. Capacitor CG2 preserves gain at high
frequencies, which extends the AEF bandwidth.
Choose a value for RG between 1 kΩ and 2 kΩ. A resistance of 1.5 kΩ is a common choice and selected in this
example to set a midband gain of 50 dB. Choose capacitances for CG1 and CG2 of 10 nF and 10 pF, respectively,
which establishes a gain rolloff below approximately 10 kHz for line- and low-frequency attenuation.
9.2.1.2.4 Injection Network
The components connected between the INJ pin and inject capacitor establish a damped injection network.
Damping is specifically required to manage resonance between the CM choke inductance and inject
capacitance, which manifests in the AEF loop gain as a pair of complex zeros.
Figure 9-3 highlights three specific RC branches: RD1, RD1A and C D1 form one branch from the INJ pin; RD2 and
CD2 in series connect to GND; RD3 and CD3 in parallel connect to the inject capacitor.
LCM1-AEF LCM2-AEF
L1

L2 3-phase
3-phase
AC/DC
AC source
L3 regulator

PE N Chassis
CX1–CX3 CX4–CX6 CX7–CX9

CY1–CY4
CG1 RG
CSEN1–CSEN4 CINJ
CG2
ZD3
U1 CD3
ZD1 RD3
COMP1 COMP2
RD1A CD1
SENSE1 INJ

SENSE2 RD1 DINJ

ZD2 = ZD1 branch
SENSE3 EN
CD2
12 V = ZD2 branch
SENSE4 VDD
RD2
CVDD = ZD3 branch
REFGND IGND

TPSF12C3 Chassis (PE)

Figure 9-3. Injection Network

Based on the injection mechanism, the AEF circuit presents a low shunt impedance to CM noise. Given the
three damping impedance branches highlighted in Figure 9-3, Equation 1 approximates the AEF impedance as:

(1)

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where the term GAEF is the gain from the power lines to the INJ node (see the TPSF12C3 quickstart calculator
for related detail).
Equation 1 shows that the impedance ZINJ appears in series with ZD3 and a parallel combination of ZD1 and ZD2.
Furthermore, the gain GAEF is reduced by the voltage divider ratio between ZD2 and ZD1. These effects combine
to increase the effective impedance of the AEF and hence reduce its attenuation performance, thus illustrating a
trade-off between performance and stability.
So while an injection network is needed for stability, it also adds impedance in series with the inject capacitor,
thus compromising EMI mitigation. As shown below, the user can minimize the impact on performance with
careful and appropriate design.
Increasing
frequency

CSEN1–CSEN4 Low-frequency CSEN1–CSEN4 Mid-frequency

CG1 equivalent circuit CINJ equivalent circuit CINJ
RG

RD3 RD3
COMP1 COMP2 COMP1 COMP2 CD1
SENSE1 INJ SENSE1 INJ

SENSE2 RD1 SENSE2

SENSE3 EN SENSE3 EN
CD2 CD2
SENSE4 VDD 12 V SENSE4 VDD 12 V

REFGND IGND REFGND IGND

TPSF12C3 TPSF12C3

RC filter (RD1, CD2) provides compensation

at low frequency for stability The impedance of CD1 shunts that of RD1 as
frequency increases. Lower impedance in series
RD3 in series with inject capacitor CINJ with CINJ helps AEF performance. CD2 > CD1
provides damping at low frequency
Increasing
frequency
Increasing
frequency
CSEN1–CSEN4 Highest-frequency CSEN1–CSEN4 High-frequency
equivalent circuit CINJ equivalent circuit CINJ
CG2 RG

CD3 CD3

COMP1 COMP2
RD1A
COMP1 COMP2 CD1
SENSE1 INJ SENSE1 INJ VINJD

SENSE2 SENSE2

SENSE3 EN SENSE3 EN

SENSE4 VDD 12 V RD2 SENSE4 VDD 12 V RD2

REFGND IGND REFGND IGND

TPSF12C3 TPSF12C3

At high frequencies, the impedance of RD1A At higher frequency, the impedance of RD2 exceeds
exceeds that of CD1. RD1A provides damping and that of CD2, resulting in RD2 and CD1 forming a high-
improves the phase margin of the AEF loop pass filter, which maximizes VINJD

As frequency increases, the impedance of CD3 shunts that

of RD3, which helps attenuation performance. CD3 CINJ

Figure 9-4. Dominant Components of the Injection Network vs Frequency

Illustrated in Figure 9-4, at low frequencies in the range of 5 kHz to 50 kHz, components RD1 and CD2 provide
compensation and RD3 damps the effects of LC resonance. At higher frequencies (above 10 kHz), the dominant
component impedance of each branch transitions to enable better attenuation performance:
• RD1 transitions to CD1

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• CD2 transitions to RD2

• RD3 transitions to CD3
Finally, CD1 transitions to RD1A if needed for phase margin of the AEF loop at high frequencies, typically above
100 kHz. When viewed in a clockwise direction, Figure 9-4 shows these transitions in sequence as frequency
increases.
Below are basic guidelines to select the component values for the injection network:
1. The undamped loop gain characteristic is likely to be unstable within the range of 5 kHz to 50 kHz, which,
as mentioned previously, relates to an LC resonance between CM choke inductance and inject capacitance.
Observe from circuit simulation – or by using the TPSF12C3 quickstart calculator – the frequency, fLFstability,
at which the phase crosses –180° with positive gain, indicating negative gain margin.
2. Choose a corner frequency with RD1 and CD2 equal to one fifth of the instability frequency:

(2)
Assigning RD1 = 1 kΩ and assuming instablity at 35 kHz, use Equation 3 to find a value for the capacitance
of CD2:

(3)
3. Select CD1 < CD2, where a typical choice is CD1 = CD2/5 = 4.7 nF.
4. Choose the resistance of RD2 such that the RD2, CD2 corner frequency is equal to that of RD1, CD1:

(4)
5. Select the resistance of RD3 to damp the resonance around the instability frequency, fLFstability.
• A typical choice for RD3 is 500 Ω to 1 kΩ.
• Assign CD3 equal to CINJ or a suitable value such that the RD3, CD3 corner frequency is less than
switching frequency.
• A lower resistance for RD3 results in more damping but at the penalty of reduced high-frequency
attenuation (or forces a higher value for CD3 to maintain the applicable corner frequency below the
switching frequency).
6. Select a resistance for RD1A of 50 Ω to improve the phase margin of the AEF loop (if needed).
9.2.1.2.5 Surge Protection
EMI filter designs, both passive and active, typically use MOVs connected from the power lines to chassis
ground to clamp surge voltage transients. While the sense pins of the TPSF12C3 have internal clamp protection,
the higher value of inject capacitance produces larger currents during surge events and thus requires external
protection. Place a bidirectional TVS diode on the low-voltage side of the inject capacitor with standoff voltage
of 24 V. Using the SOD-323 packaged device given in Table 9-2, clamping occurs at 40 V and 50 V with surge
currents of 1 A and 8 A, respectively.

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9.2.1.3 Application Curves

Unless otherwise indicated, VVDD = VEN = 12 V.

–29dB

AEF disabled AEF enabled

Note
A high DM noise signature may mask improvement in CM noise performance related to AEF. A
reduction of CM choke inductance may also reduce leakage inductance, which could impact DM noise
attenuation. Install higher X-capacitance or a discrete DM filter inductor to manage DM attenuation as
needed. Also, use a DM-CM noise splitter to isolate the CM component of the measured total noise.

Figure 9-5. CISPR 32 Class B EMI Mitigation Result with AEF On and Off (EN Tied High and Low)

VLINE 500 V/DIV INJ TVS diode clamps VLINE 500 V/DIV
Negative undershoot
eventually decays

VINJ-C 20 V/DIV VINJ-C 20 V/DIV

SENSE internal
protection clamps INJ TVS diode clamps
VSENSE1 10 V/DIV VSENSE1 10 V/DIV

SENSE internal
ISENSE1 2 A/DIV 1 µs/DIV ISENSE1 2 A/DIV protection clamps 200 µs/DIV

(a) (b)

Figure 9-6. IEC 61000-4-5 Positive Surge, 5-kV Single Strike – 1 µs/div (a), 200 µs/div (b)

VLINE 500 V/DIV VLINE 500 V/DIV Positive overshoot

eventually decays
VINJ-C 20 V/DIV
INJ TVS diode clamps INJ TVS diode clamps
VINJ-C 20 V/DIV

VSENSE1 10 V/DIV VSENSE1 10 V/DIV

ISENSE1 2 A/DIV ISENSE1 2 A/DIV

SENSE internal SENSE internal
protection clamps protection clamps
1 s/DIV 200 s/DIV

(a) (b)

Figure 9-7. IEC 61000-4-5 Negative Surge, 5-kV Single Strike – 1 µs/div (a), 200 µs/div (b)

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VLINE 500 V/DIV VLINE 500 V/DIV

VSENSE1 10 V/DIV VSENSE1 10 V/DIV

ISENSE1 2 A/DIV ISENSE1 2 A/DIV

IINJ 10 A/DIV 10 s/DIV IINJ 10 A/DIV

10 s/DIV

(a) (b)

Figure 9-8. IEC 61000-4-5 Surge, 5-kV Repetitive Strike at 10-Second Intervals – Positive (a), Negative (b)

Note
The surge test circuit used MOVs (Littelfuse V20E300P) connected from line and neutral filter inputs
to chassis ground. See Figure 9-11.

9.3 Power Supply Recommendations

The TPSF12C3 AEF IC operates over a wide supply voltage range of 8 V to 16 V (typically 12 V) and is
referenced to chassis ground of the system. The characteristics of this VDD bias supply must be compatible with
the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the VDD
supply must be capable of delivering the required supply current to the loaded AEF circuit.
The supply rail can already be present in the system or can be derived using a low-cost solution with an auxiliary
winding from an isolated flyback regulator. Connect a ceramic capacitor of at least 1 µF close to the VDD and
IGND pins of the TPSF12C3. Ensure that the ripple voltage at VDD is less than 20 mV peak-to-peak to avoid
low-frequency noise amplification.
9.4 Layout
Proper PCB design and layout is important in active EMI circuits (where high regulator voltage and current slew
rates exist) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of
the design depends to a large extent on PCB layout.
9.4.1 Layout Guidelines
The following list summarizes the essential guidelines for PCB layout and component placement to optimze AEF
performance. Figure 9-9 and Figure 9-10 show a recommended layout for the TPSF12C3 circuit specifically with
optimized placement and routing of the IC and small-signal components. Figure 9-11 shows an example of a
three-phase, four-wire filter board design with CM chokes, X-capacitors, Y-capacitors, protection components
(varistors and X-capacitor discharge resistors), and AEF circuit.
• Position the sense and inject capacitors between the CM chokes near the X-capacitor that couples the
injected signal to the other power lines. Avoid placement close to the CM choke windings that may result in
parasitic coupling to the sense and inject capacitors.
• Maintain adequate clearance spacing between high-voltage and low-voltage traces. As an example, Figure
9-11 has 150 mils (3.8 mm) copper-to-copper spacing from power lines (lives and neutral) to chassis ground.
• Route the sense lines S1, S2, S3 and S4 away from the INJ line. Avoid coupling between the sense and
inject traces.
• Use a solid ground connection between the TPSF12C3 and the filter board. Minimize parasitic inductance
from the AEF circuit return to the chassis ground connections on the board.
• Place a ceramic capacitor close to VDD and IGND. Minimize the loop area to the VDD and IGND pins.
• Place the compensation network copnponents close to the COMP1 and COMP2 pins. Reduce noise
sensitivity of the feedback compensation network path by placing components RG, CG1 and CG2 close to
the COMP pins. COMP2 is the inverting input to the AEF anplifier and represents a high-impedance node
sensitive to noise.

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• Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal
impedance. Provide adequate heatsinking for the TPSF12C3 to keep the junction temperature below 150°C.
A top-side ground plane is an important heat-dissipating area. Use several heat-sinking vias to connect
REFGND (pin 9) and IGND (pin 14) to ground copper on other layers.
9.4.2 Layout Example

Figure 9-9. Typical Layout

Legend
Route sense traces S1, S2, Top layer copper
S3 and S4 away from the Layer-2 GND plane
INJ trace
Top solder

Keep the VDD capacitor

close to the VDD pin

Place the compensation

network close to the Keep the damping network
COMP1 and COMP2 pins close to the INJ pin

INJ pin probe point

Figure 9-10. Typical Top-Layer Design

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Legend
Top layer copper
Bottom layer copper
Top solder

Figure 9-11. Typical Three-Phase Filter Board Design With AEF

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10 Device and Documentation Support

10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.1.2 Development Support
All AEF devices from the family shown in Table 10-1 are rated for a maximum junction temperature of 150°C and
are functional safety-capable. See the Texas Instruments power-supply filter ICs landing page for more detail.
Table 10-1. Common-mode AEF IC Family
JUNCTION TEMPERATURE
DEVICE ORDERABLE PART NUMBER PHASES GRADE
RANGE
TPSF12C3 TPSF12C3DYYR 3 Commercial –40°C to 150°C
TPSF12C1 TPSF12C1DYYR 1 Commercial –40°C to 150°C
TPSF12C3-Q1 TPSF12C3QDYYRQ1 3 Automotive –40°C to 150°C
TPSF12C1-Q1 TPSF12C1QDYYRQ1 1 Automotive –40°C to 150°C

For development support see the following:

• TPSF12C3 quickstart calculator
• TPSF12C3 EVM Altium layout source files
• TPSF12C3 PSPICE for TI and SIMPLIS simulation models
• TPSF12C3 EVM user's guide
• For TI's reference design library, visit TI Reference Design library
• To design a low-EMI power supply, review TI's comprehensive EMI Training Series
• TI Reference Designs:
– 3-kW, 180-W/in3 single-phase totem-pole bridgeless PFC reference design with 16-A max input
– 1-kW reference design with CCM totem pole PFC and current-mode LLC realized by C2000™ and GaN
– 7.4-kW on-board charger reference design with CCM totem pole PFC and CLLLC DC/DC using C2000™
MCU
– GaN-based, 6.6-kW, bidirectional, onboard charger reference design
– 10-kW, bidirectional three-phase three-level (T-type) inverter and PFC reference design
• Technical Articles:
– Texas Instruments, How a stand-alone active EMI filter IC shrinks common-mode filter size
– Texas Instruments, How device-level features and package options can help minimize EMI in automotive
designs
– Texas Instruments, How to use slew rate for EMI control
• White Papers:
– Texas Instruments, How Active EMI Filter ICs Mitigate Common-Mode Emissions and Save PCB Space in
Single- and Three-Phase Systems
– Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies
– Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies
• Video:
– Texas Instruments, Single- and three-phase active EMI filter ICs mitigate common-mode EMI, save space
and reduce cost
• To view a related device of this product, see the TPSF12C1 single-phase active EMI filter for common-mode
noise mitigation or refer to the Texas Instruments power-supply filter ICs landing page

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10.2 Documentation Support

10.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TI pioneers the industry's first stand-alone active EMI filter ICs, supporting high-density
power supply designs press release
• Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
• Texas Instruments, Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics ADJ
article
• Texas Instruments, Designing High Performance, Low-EMI, Automotive Power Supplies application report
• Texas Instruments, EMI Filter Components And Their Nonidealities For Automotive DC/DC Regulators
technical brief
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPSF12C3DYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 150 TPSF12C3 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPSF12C3 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Jul-2023

• Automotive : TPSF12C3-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSF12C3DYYR SOT-23- DYY 14 3000 330.0 12.4 4.8 3.6 1.6 8.0 12.0 Q3
THIN

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPSF12C3DYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8

Pack Materials-Page 2
 PACKAGE OUTLINE
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

3.36 C
3.16 SEATING PLANE

A PIN 1 INDEX
AREA 0.1 C

12X 0.5
14
1

4.3 2X
4.1
NOTE 3 3

7
8

14X 0.31
0.11
0.1 C A B 1.1 MAX
B 2.1
1.9

0.2 TYP
0.08

SEE DETAIL A

0.25
GAUGE PLANE

0°- 8°
0.63 0.1
0.33 0.0
DETAIL A
TYP

4224643/B 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB

www.ti.com
 EXAMPLE BOARD LAYOUT
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

SYMM
14X (1.05)

1 14

14X (0.3)

SYMM

12X (0.5)

8
7

(R0.05) TYP
(3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

SOLDER MASK METAL UNDER

OPENING SOLDER MASK SOLDER MASK
METAL OPENING

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4224643/B 07/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DYY0014A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

SYMM
14X (1.05)

1 14

14X (0.3)

SYMM

12X (0.5)

8
7

(R0.05) TYP
(3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 20X

4224643/B 07/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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