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Amba-Apb Protocol

The document discusses the APB protocol which is part of the AMBA specification. It provides details about the APB protocol such as transfers, signals, handshaking mechanism and features it supports like single write, read and wait states. It also explains concepts like transactions, performance and debugging testcases.

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vimal raj
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360 views8 pages

Amba-Apb Protocol

The document discusses the APB protocol which is part of the AMBA specification. It provides details about the APB protocol such as transfers, signals, handshaking mechanism and features it supports like single write, read and wait states. It also explains concepts like transactions, performance and debugging testcases.

Uploaded by

vimal raj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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@shraddha_pawankar Date : 19/01/2024

APB Protocol

APB:
Advanced Peripheral Bus.
 The APB (Advanced peripheral bus) protocol is a part of AMBA
(advanced microcontroller bus architecture) family.
 Design under test (DUT) is tested and it establishes the communication
between master (test bench) and slave (design).
 Provide low cost interface(minimal power consumption and reduced
interface complexity).
 APB interfaces to any peripherals that are low-bandwidth.
 All signal transitions are only related to the rising edge of the clock..
 Every transfer takes atleast 2 cycle.

What is Amba APB protocol specification V2?

 This specification defines the interface signals, the basic read and write
transfers, and the two APB components the APB bridge and the APB
slave.
 This version of the specification is referred to as APB2.
@shraddha_pawankar Date : 19/01/2024

Transfers
There are 2 types of transfers
Write transfer : With no wait states
With wait states
Read transfer: With no wait states
With wait states.

Protocol ??
Set of signals + Guidelines
 Set of guidelines on how communication happen between two
components.
 One component called Master,another slave.
 How address phase will happen?
 How data phase will happen?
 How response phase will happen?
@shraddha_pawankar Date : 19/01/2024

--------------------------------------------------------------------------------------------------------

What type of protocol?


There are 2 types.
On chip protocol :
 Communicate for the blocks on the chip
 Ex: AXI,APB,AHB
 Limited by frequency of operation
 Data communication happens in terms of transaction.
 Arbitration phase,request phase,data phase,response phase.
 Handshaking using dedicated signals.

Peripheral protocol : Communication for the blocks with other blocks outside
the chip.
Ex: PCIe,USB,DDR,I2C,SPI,UART,SATA
 Data communication happens in terms of packets/frames.
 Handshaking happens using preamble/Sync
 Receiving devices uses preamble/sync pattern to start packet.
 There is no dedicated handshaking signals

APB is a On chip protocol.


--------------------------------------------------------------------------------------------------------
Protocol based system architecture:
One master connecting to multiple slaves using APB interconnect.

Components in the APB architecture:


 Master
 Interconnect
 Multiple slaves
@shraddha_pawankar Date : 19/01/2024

Interconnect :
Interconnect made up of Decoder + Multiplexer logic
It decodes incoming request address,figures out in which direction shouls
be routed.
It automatically knows in which direction response should be routed.

APB signals :

In APB every signals starts with “P”.


PCLK
PRST
PADDR : We want to perform transaction
PWDATA
PRDATA
PWRITE : PWRITE = 1 (Write) ,PWRITE = 0 (Read).
PENABLE : Transaction actually happens
PSEL : Among connected slaves,which slave is selected
PREADY : Slave is ready for completing the transaction
PERROR : Some non-supported things.

HANDSHAKING SIGNALS:
PENABLE,PREADY

CONTROL SIGNALS:
PSEL,PENABLE,PREADY,PWRITE

DATA SIGNALS:
@shraddha_pawankar Date : 19/01/2024

PADDR,PWDATA,PRDATA,PRDATA,PREADY,PERROR.

PENABLE and PREADY are the handshaking signals


PENABLE : Master is giving valid information.
PREADY : Slave is ready to accept the information.

How handshaking happens in APB protocol ?


For handshaking,
PENABLE = 1
PREADY = 1

Penable and pready should be high at any +edge of clock.

How transaction or packets transfers happen ?


Master drives PSEL to select a particular slave.
Master then completes transaction by driving PENABLE = 1,to which slave will
respond by giving PREADY = 1.

Different features APB protocol supports:


1) Single write
2) Single read
3) Wait states

APB is synchronous protocol


 All the signal sampling happens at the positive edge of the clock.
 Any changes in between clock edges is not important.
@shraddha_pawankar Date : 19/01/2024

Error response in APB:


 PSLVERR indicates error condition on an APB transfer.
 Error condition can occur both read and write transaction.
 PSLVERR is only considered valid during the last cycle of APB transfer,
 When PSEL,PENABLE and Pready are all high.

Difference between transfer and transaction.

Transfer : A single exchange of information,with one valid and ready


handshake.

Transaction: Entire burst of transfers


Containing an address transfer,one or more data transfer
Write sequence,response transfer.

How will you decide the performance?


In a given amount of time (clock cycles),How much data can be transferred.
In APB, each transaction required at least 2 clock cycles
1) One cycle for request phase
2) One cycle for response phase.

How many data buses does the APB protocol have?


 The APB protocol has two independent data buses, PRDATA for read
data and PWDATA for write data,.
 The buses can be 8 bits, 16 bits, or 32 bits wide.
 The read and write data buses must have the same width.
 Data transfers cannot occur concurrently because the read data and
write data buses do not have their own individual handshake signals .
@shraddha_pawankar Date : 19/01/2024

Explain Testplan:
 This would include all the supported features, interfaces and protocols ,
configuration and initialization information including registers, and other
details.
 A verification engineer who is responsible for verifying a given design
considers the design specification as a golden reference.
 His job is to make sure that the design implementation is functionally
correct with respect to this design specification.
 A Verification Test plan is a specification document that captures all the
details needed for verifying a given design.
 A Verification engineer is responsible for developing this plan initially as
he understands the details of the DUT (Design under Test).
 A proper planning is always important to complete verification with
highest quality and in a predictable time period.

Testcase Debugging Approach:

Understand the UVM Testbench Structure

Review the Test Case and Testbench Code

Use UVM Debugging Features:

UVM's built-in features for debugging, such as uvm_report_fatal,


uvm_report_error, and uvm_report_warning

Enable Tracing:

Enable transaction tracing selectively for specific UVM components or


hierarchies.

Check UVM Configuration:

Review the uvm_config_db settings to ensure that objects are properly


connected.

Verify DUT Interface Connections:


@shraddha_pawankar Date : 19/01/2024

 Confirm that the interfaces between the UVM testbench and the DUT
are properly connected.
 Check the signal connections, clocking, and reset logic.

Inspect Transaction Flow

 Examine the transaction flow between the testbench and the DUT.
 Use waveform viewers and debugging tools to visualize signal activity
and transaction sequences.

Check for Race Conditions:

 Investigate the possibility of race conditions or synchronization issues


between concurrent UVM processes.
 Review the usage of locks and semaphores for synchronization.

Review Constraints and Randomization:

Consider UVM Phase Execution:

Log and Document Findings

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