Implementation of Simulation Algorithms in FPGA for Real Time Simulation

of Electrical Networks with Power Electronics Devices

Julio C G Pimentel, IEEE Senior Member

Laval University, Quebec, Canada
Dept. ofElect. And Computer Eng., Ste-Foy, GIK 7P4
Cisco Systems Inc.
Ottawa, Ontario, Canada
pimentel@ieee. org

Abstract time step at a reasonable cost. That is because the

processor-memory hardware paradigm and the inter-
Development of digital simulators for transient processor communication overhead experienced with
analysis of electric power systems has been the subject the present technology set a minimum time step around
of many research works during the last four decades. 20 gs. Such number is a consequence of the load on the
In most studies, the simulation can be done off-line but main processor bus, the data memory allocation
in some particular situations, usually equipment strategy and the data network load and latency which
testing, it may be mandatory to have the simulation cause a bottleneck in present digital systems [3].
executed in real time so that the interaction with real In this paper we show how a high-density FPGA
equipments can be studied. Digital Real Time Power can be used to implement a DRTPSS simulation
System Simulators, DRTPSS for short, became a algorithm. The simulator is capable of simulating large
mandatory tool to ensure the quality ofpower systems. electrical networks including high frequency power
Most of the DRTPSSs in use nowadays are based on electronic devices. One important feature of the
high performance parallel processors using last simulator is the use of multiple timesteps so that sub
generation technology. Recently, some works have networks with very different natural frequencies can be
proposed new architectures based on the use ofFPGAs simulated using the most appropriate timestep. In order
("Field Programmable Gate Arrays") as a mean to to achieve such high performance the simulation
increase the simulator's processing power without algorithm is mapped directly into hardware following a
increasing its cost too much. This work shows how hardware acceleration approach. The real time FPGA
FPGAs can be used to implement a DRTPSS capable simulator can also be integrated to a parallel processor
of simulating large electrical networks including high following a "hardware-software" co-design approach.
frequency power electronic devices. This way, part of the simulation algorithm runs in
software in the parallel processor and part of the
1. Introduction algorithm runs directly in hardware as presented in [3].
This combined approach allows the real time simulator
A general architecture for a DRTPSS consists of a to handle high frequency networks as well as very
high performance parallel processor, a simulation large networks. Finally, we should also point out that
engine normally coded in C/C++ and input/output this hybrid architecture has higher flexibility than a
acquisition cards responsible for interfacing the purely hardware or purely software architecture.
simulator to the external equipment. The simulation
engine has a library of device models the simulator can 2. Related Works
understand and a representation of the power systems
network using, for example, state-space formulation FPGAs are being used in many areas of research as
[18]. Although parallel processor architectures present a way of accelerating algorithms. For example, [1] and
many desirable characteristics such as being readily [9] present FPGA hardware acceleration for the
reconfigurable to study new network topologies and Conjugate Gradient and Jacob iterative methods
not too difficult to scale it up to address complex respectively. These works show that the FPGA
problems, it is very difficult to reduce the minimum implementation of an algorithm can achieve higher

1-4244-0690-0/06/$20.00 ©2006 IEEE.

peak performance than its implementation in software VHDL SimPowerSystem User
System Simulink
running in state-of-the-art microprocessors. The results
presented in [1] and [2] show that the architecture
performs very well for large matrices especially when
the solver runs continuously. Because of the real time SimPowerSystem
constraint and the nature of the equations involved, Valdate Simulink
these scenarios are rarely applicable to real time VHDL
Library
simulation of power electronics circuits. This paper Power System

addresses the problem of small and medium size state Spec

space matrices where the calculation is bounded by the GenVhdl
simulation time step.
The method proposed in [8] is based on the Scheduler Non linear Linear
Sub circuit Sub circuit
generalized algorithm developed by Dommel and
implements each element of the network using their FPGA C/C++ Or FPGA
discrete-time equivalent resistances and current Figure 1. FPGA DRTPSS Programming Flow
sources. This approach models the linear network at
very low level but it can use a lot of the FPGA area. A proprietary tool called GenVhdl reads the
The work presented in [17] is based on a hybrid Simulink power network schematic, the VHDL
solution where an FPGA is responsible for sampling libraries as well as data provided by the user and
the high-speed PWM firing pulses, conditioning them automatically generates the VHDL code that
in 32-bit words and send it to two IBM 750GX double- implements the real time simulation. The derived
precision RISC processors responsible for the VHDL code can be synthesized with general
algorithm computing. The FPGA also coordinates the commercial EDA tools using an FPGA design and
signals at the beginning of each small time-step in implementation flow such as Xilinx ISE [7].
order to maintain the synchronism of the small time-
steps in the two processors. This solution can achieve a 3.2. High Level Architecture Overview
reported minimum timestep of 2 gs which is one of the
shortest results reported in the literature. We propose a The architecture shown in Figure 2 is a coarse grain
different approach where the simulation is entirely dataflow architecture of highly specialized processor
realized in the FPGA. As presented in the following elements (PEs) running in parallel and synchronized at
sections, the preliminary results show our approach can time step level. The power system sub-circuits are
achieve a timestep smaller than 0.4 gs. modeled as concurrent PEs which are interconnected
through their input and output ports so that the inputs
3. Overview of the DRTPSS using FPGAs of a module can only change at the end of a time step.
The outputs of the sub-circuits only depend on their
This section presents an overview of the DRTPSS inputs and their internal states. At the end of each time
high level architecture so that the reader can step each PE transfer their calculated voltages and
understand the constraints guiding the design and currents to the next PE.
implementation of each module of the system in Non linear sub-circuits
FPGA. Further information about its architecture can
be found in [19]. Non linea ar~ Votg
Voltage
Sub - ict
Voitage
Current Linear Current
sub-circuit
3.1. The Programming Flow
Sgb Voltage Voltage
Current Current
Figure 1 shows the programming flow. The State Space
(Ad, Bd, Cd, Dd)
modules in the VHDL library were designed to be Sub-ri Voitage
Current Control
Voltage
Current I
compatible with their SimPowerSystemTM counterparts
[6]. The VHDL models were developed and tested
using the following model-based methodology: 1) The Control Control Control
modules are developed and tested using Simulink; 2) Scheduler
After the behavior of the model attained the expected
accuracy it is coded in VHDL; 3) the results are Figure 2. FPGA DRTPSS High Level Architecture
compared against the simulink model and then stored
in the VHDL system library.
 PEs may run at different time step depending on the An EFSM is defined as 6-tuple where the sixth
natural frequency of the sub-circuit it is modeling. element of the tuple is a counter holding the elapsed
Therefore, the system should provide a way of up time since it has moved to a new state [4]. Because the
sampling and down sampling the PEs inputs and devices modeled here do not use elapsed time we
outputs to the same clock domain so that they can removed it from the PE EFSM representation. In this
exchange information with each other. The scheduler work an EFSM is defined as 5-tuple (S, I, V, 6, init)
synchronizes the function of all PEs and is responsible where: S is a finite set of states; I is a finite set of
for coordinating the following tasks: simulation events (i.e., transitions); V is a finite set of variables
initialization; generation of the multiple time steps that represent inputs, outputs and parameters; 6 is a
reference clocks; synchronization of the simulation and finite set of transition rules; and init represents the
exchange data between linear and nonlinear. initial state and initial values of all variables. The
Decoupling the electrical network in concurrent PEs transition rules are represented as a logical conjunction
reduces the overall complexity of the model which is of integer linear inequalities on the variables. The
highly desirable. However, because the PEs are EFSMs are made periodic by introducing a dummy
simulated independently of each other they only transition as the last event of a path starting at the
exchange information at the end of a time step. It is initial state so that it returns to the initial state [4]. In
well known that this strategy can introduce one or two order to execute an event a the value of the associated
timesteps delay in the feedback loop formed by the transition rule P must be true. Input events are
linear and non linear sub-circuits affecting the accuracy represented as a?x and output events are represented as
of the simulation and in certain cases causing it to b!y{y := E(x)} where x and y denote input and output
become instable [16]. Also, the use of iterative variables, respectively. b!y( {y:=E(x)}[P] denotes that
methods to solve this problem is not usually possible the output event b is executed at the end of the time
because of the real time constraint. step satisfying P and its output value y is E(x) [4]. This
notation will be used in the following sections to
4. Distributed Concurrent Modules describe PEs.
The EFSM representing a PE model is mapped to
Concurrent periodic Extended Finite Sate Machines hardware such that the EFSM variables (input and
("EFSMs") are used in distributed real time systems as output voltages and currents, some logical signals, etc.)
a formal representation of concurrent process [4]. We are part of the data path implemented using MAC
have modeled the PEs as a parallel composition of ("Multiply-And-Accumulate") units [ 1 ] [2] [11]. The
concurrent periodic EFSMs synchronized by a remaining signals are part of the control path and are
scheduler. Figure 3 shows their interfaces. intended to send information to or receive information
from the scheduler. The EFSM S and (I, 6) tuple
CLK - High frequency clock used as the reference elements are respectively the state and the branches of
clock for the whole system. the PE state machine implementing the control path.
TSI to TSn -Multiple time step synchronizing signals; All PEs follow the same standard interface
STC_1 to STC_n -The PE inputs are sampled when a specification which is based on the following
STC for the module is asserted; processing model: at every time step sample inputs,
REG_1 to REG_n -Asserted at the end of each process information, and hold computed data at
timestep to store the newly computed result at the outputs. The PE and the scheduler interfaces use the
output registers of the PE; following main signals:
EOC_1 to EOC_n - Tells the scheduler all PEs Special care was taken in the development of the
completed their processing before the end of the non linear models (described in section 5) as well as in
timestep. the design of the simulator itself to reduce the
occurrence of unrealistic oscillations caused by the
RST
CLK EOC
EOC1 E
EN
decoupling strategy used. Also, notice that the
simulation becomes more stable and more accurate as
S CLK
F CLK EOC2

SIC
Sub
sSTC
the time step decreases when compared to the circuit
STC nl
EOCn
natural frequencies. The scheduler can synchronize the
Voltage
PEs to let them run in series or in parallel using the
C ircut
Voltage
REG
Currents Currenrc_it 4 Voltages RST

LogicalF Logical
CLK RREG nl
same or different timesteps. Because non linear PEs
Signals, ,_ Signals can run at a timestep that is a fraction of the time
Figure 3. PE and Scheduler Standard Interface required for the linear sub-circuit PEs. Simulating the
first in series with non linear PEs do not increase much
the total timestep but reduces the decoupling delay to
 U)
C)
(I)

(A

0~5
4

I~ 1 I.
one timestep instead of two as is the case for parallel
simulation. This improves the simulation stability.
Also, multiple timestep simulation allows us to
optimize the FPGA resource allocation. For example, if
the linear sub-circuit requires to be simulated at 10 gs
timestep and a PWM converter requires less than 1 s,
we can tell GenVhdl to allocate less hardware for the
state space solver in order to allow more hardware for
the PWM converter. Figure 4 shows an example of a
series and a parallel sequencing.
Linear PE

short:
timestep

Sample
inputs

5. Recoupling link model

timestep

Linear PE

Nonn
Linear
PE

long timestep
M

Process
data
U0
Non 1/o
Linear
PE

0..
1_1

short:
timestep

1 Store at
< outputs

Figure 4. Series and Parallel Scheduler Sequencing

Sub-circuits running at different timesteps can not

immediately exchange information. We should first
decrease ("downsample") or increase ("upsample") the
signal sample rate to the same reference clock. In order
to simplify the design of the architecture we chose to
let the PE running at the shortest timestep to up convert
and down convert the signals going to PEs running at
larger timestep. In this way, the VHDL system library
includes a down sampler and an up sampler module
and GenVhdl tool instantiates them into the appropriate
PE according to their specified sampling rate.

5.1. Down sampling

Some downsampling methods have been proposed
by works in multi rate digital filter design. If M is the
specified downsampling rate, one method that is
Linear PE

PE
Linear

Nons
Linear
PE

long timestep
timestep

n
> ADC/DAC
0

1/0 cards
Non :1/0
Linear
PE
implement but it has no physical relationship with how
power electronics circuit works.
In general, power electronics circuits work based on
averaging the current flowing through an inductor or
the charge stored in a capacitor. Thus, an averaging
based method is the natural choice because it
resembles the normal functioning of the circuit. We
have studied the moving average, fixed interval
average and low pass filtering. The fixed interval
average method was found to be the easiest to
implement and the one that produced the best results. It
consists in deriving the average simulated at each
timestep of the fast clock during one timestep of the
slow clock. For example, the average current between
times Ta and Tb as a function of the fast clock timestep
At is defined by (1):

i(t)
twI
b
T

n
a
n

i(T+(k 1))
k=l

i(Ta+(k l)jV
AI

The approach assumes the slow clock period is an

Figure 5 shows the data path of the downsampling

module implementation. It uses a MAC unit where one
(1)

integer multiple n of the fast clock period so that (1)

can be rewritten as (2):

(2)

input is the fixed value (1 / n) and the second input is

the instantaneous output of the PE running at the fast
clock. The MAC accumulator is cleared at the
beginning of every slow timestep and the accumulated
result is transferred to the next PE at the end of it.
Because the numerical representation of (1 / n) is
calculated a priori by GenVhdl and passed to the PE,
the ratio n do not need to be a power of 2 so that the
simulator accepts any integer ratio between the slow
and fast timesteps.

Figure 5. Down Sampling Hardware Implementation

largely used consist in simply keeping one sample for 5.2. Up sampling
every M samples at the input and discarding the
remaining (M-1) ones [10]. This method is simple to The fast clock PE inputs are sampled at the
beginning of each slow clock timestep. The simplest
method to up sample them is to keep their value
constant during the whole slow clock timestep [10]. 6. Power Electronics Devices
Because the maximum bandwidth of the input signals
can be comparable to the frequency of the slow clock Currently the VHDL system library includes five
this approach can incur in non negligible simulation power electronic devices: diode, MOSFET, thyristor,
errors. A more accurate approach is to use a predictor power switch and power bridge. We present the models
to extrapolate the value at the next timestep based on of the thyristor and the power bridge in the following
the past history of the slow clock sampled data, and sections. The diode, MOSFET and power switch are
update it with the new sampled value at the beginning not presented here because their model can be
of the next slow clock timestep. We have considered extrapolated from the two models presented. We
only lower order predictors for two reasons: higher should notice that a similar approach can also be used
order methods have smaller region of stability; lower to model others types of non linear devices.
order methods consume lesser FPGA resources.
According to our simulation results, Adams-Bashforth- 6.1. Modeling of the thyristor PE
2 produced about half the error of Mid-Point or Euler.
Besides, it consumes little hardware so that we chose Figures 8 and 9 show the thyristor VHDL entity
to implement the Adams-Bashforth-2 extrapolation definition and its electrical and EFSM representation
rule [13] [14]. We can rearrange its interactive equation respectively. We should notice the module is fully
to use only addition, subtraction and shift operations: configurable so that it can be used in many different
k1 = f (x(n),y(n))+ O.5 f(x(n),y(n)), (3) applications. The same is also true for the others
k2= k1 - O.5 f(x(n -1),y(n -1)), (4) modules of the VHDL library. The EFSM
configuration variables are passed to the model as
y(n + 1) = y(n) + k2 *AT, (5) VHDL generic parameters while the I/0 and control
As shown in figure 6, the past samples are used to variables are passed as signals [12].
calculate the extrapolated value y(n+1). Afterwards,
we use a linear regression to interpolate the upsampled entity thyristor is
results between y(n) and y(n+1) at the fast clock generic (Vf natural:= 16; Ic natural := 0);
Tsl natural:= 1; Ts2 natural:= 1;
timesteps. In hardware, the predictor is implemented Ron natural:= 16; Lon: natural:= 0;
by the circuit shown in figure 7. NBits: natural:= 32; NBitsRadix: natural:= 8;
port (
iy(t) CLK: in std logic;
AT At
TS_sync: std_logic;
predicted RST: in std logic;
y(n+l) EN: in std_logic;
Reg_output: in std_logic;
--

Gate: in std logic;

Linear STC: in std_logic;
sampled 1 / interpolation Vak: in std_logic_vector(NBits-1 downto 0);
Iak: out std_logic_vector(NBits-1 downto 0);
Iavg: out std logic vector(NBits-1 downto 0);
EOC: out std_logic);
Ts(i-2) Ts(i 1) Ts(i) Ts(i+1)

Figure 8. Thyristor VHDL entity definition

Figure 6. Up Sampling Method

Electrically, the thyristor is modeled as a switch in

operation
parallel with a RC snubber [5][6]. The input and output
variables are respectively (Gate, Vak) voltages and the
averaged and instantaneous Jak currents. When turned
off it is an ideal switch so that Iak(n)=0. Otherwise,
when it is turned on it is modeled by a series RLV
circuit. During the decoupling phase, the RC snubber is
placed to be simulated in the linear sub-circuits. The
remaining devices in the model are simulated by the
thyristor PE. The continuous time transfer function
H(s) of the two port RLV network is given by (6):
Figure 7. Up Sampling Hardware Implementation
H(s) = Iak(s) ((1/R)
I + s (L/R)'
(6)
Vak(S) -Vf (s)
 Using backward Euler discretization rule we can Bl1on, the ON/OFF state of bridge, during the current
write (7) which is implemented in hardware using the and the last two timesteps. Notice the RC snubber is
same approach explained in section 5. simulated as part of the linear sub-circuit so the current
flowing through it is not readily available to the UPB.
Iak (n) = Al Vak (n) + A2Iak (n -1)), (7) However, to accurately model the switching, the UPB
Where: Al = TT , A==
^A2 to should take it into account. The UPB model includes a
first order predictor to estimate this current. When the
Lon + Ron n + Ron TS new bridge voltage VQ 1 arrives one time step later the
a-
Rs
v v v
Os
C new value is used to correct the estimated value. Figure
Ar K sample!{Vak=inp}[STC== 1 ] 11 shows the UPB data path.
turnon!{lak=lcalc}[P1]
G

Rs Cs
Ql EOsi s Bridge #1
K sample!{VQ1 =inp}[STC==1 ]
A GI Dl :.Rsl +)flywheel!{bl=(la/2}[Dl=on& D2=on]
I

Gate Vf Ron Lon store!{out=lak}[Reg==1] Ibl la

V 00
Icalc= f(Ron, Lon, Rs, Cs) A
i
P1: (Vak>O)&(Iak==O)&(G=1) P2 (2*lak(i)I=ak(i-1))&(Vak<=O)&(G=O) 1Ib2
Q2 Cs2
Figure 9. Modeling of the Thyristor 1Is2
G2 D2 VRs2
6.3. Modeling of the Universal Power Bridge
Ical cl=f(Ron1,Lon ,Rsl,Csl)
Ql on = VQ1>O and Gl l
As defined in SimPowerSystems'TM from Matlab, Dl on= not(Q2 on) and ..
the Universal Power Bridge ("UPB") block Bridgel-on = QT on or Dl_on
P1 (Bi state= O0)
implements a universal three-phase power converter P2 (Bi-state= 011
P3 (Bi state= 110)
that consists of up to six switches connected in a bridge P4 (B- state= 100)
topology and can be configured to model many
different types of power switches [5][6]. Currently, the Figure 10. Modeling of the UPB Bridge #1
VHDL library of the FPGA real time simulator
includes three types of UPBs: diode, thyristor and operation d bl (n)
MOSFET. This section describes the MOSFET UPB Icalcl
Id
ck
register
implementation.
1

Ib2 lb1 (fl,g

dq
Figure 10 shows the electrical model of a single- Id
ck
phase UPB composed of one arm. A three-phase UPB A2 Add/sub Q D blalcl (n)
Asl q

is formed by three arms connected in parallel. Each Id

ck
half of the arm, called a bridge, includes a forced- Vql 1 -d q I .l(n
lbli ck
commutated switch controlled by signal Gx and a Isi
0
G0 LK FRST CLR EN
Id
ck
naturally commutated flywheel diode. The proper RST
CLR---1'-
operation of the UPB requires the following conditions EN
to hold: 1) the two halves of an arm can not be turned
on at the same time; 2) every time QI is on the Figure I 1. Data path of UPB Bridge #1
associated diode D1 is turned off and vice-versa; 3) If
Gx=1 then Qx is on; 4) Current la can not suffer 7. State Space Solver
sudden changes.
During switching, the UPB presents a non linear Here we present the hardware implementation of the
behavior which combined with one or two timesteps state space solver. Its architecture exploits the
delay originated by the decoupling strategy can cause characteristics of the state space formulation to allow
simulation errors and possibly instability. To mitigate an efficient mapping to the FPGA resources. The linear
these problems, the UPB EFSM coordinates the data sub-circuits are modeled by their discrete-time state
path to ensure current through the UPB devices will be space formulation (8) and (9):
redistributed respecting voltage and current Kirschoff s X(n + 1) =Ad- X(n)+ Bd U(n), (8)
laws as well as energy conservation. The simplified
EFSM representation of bridge #1 is shown in figure y(n + 1) =Cd * X(n) + Dd U(n), (9)
10. Variable BIlstate stores the aggregated value of
 Where n is the timestep number and Ad, Bd, Cd and 9. Experimental Results
Dd are the discrete state space matrices. The high level
architecture of the state space solver is shown in figure In this section we present the simulation results using
12. It implements the linear sub-circuit PEs. The the FPGA simulator on a three-phase DC-AC converter
control signals MemAddr, SigAddr, doing_X_not_U, shown in figure 13 [5]. The circuit works on the
etc. are generated by its internal state machine. principle of converting energy from the DC voltage
Its basic module is the VVM ("Vector-To-Vector source into a 60 Hz sinusoidal current flowing through
Multiplier") which multiplies one column of a matrix the three-phase charge RL according to the
(Ad, Bd, Cd or Dd) by a vector (X or U). It includes a configuration parameters set to the PWM modulator.
MAC unit, a blockRAM memory bank configured as The gates of the MOSFET power switches are
512 entries x 32 bits, multiplexers and a state machine. controlled by a sinusoidal PWM modulator which had
The MAC units can run at a minimum clock frequency
of 150 MHz with a latency of 6 clock cycles [1] [2]. its carrier frequency set to 2 kHz at a modulation index
We should notice the matrices can have very of 0.85. The PWM was configured to generate a 60 Hz
different dimensions. Also, the minimum dimension sinus at the output when the high frequency carrier is
can vary from 1 up to hundreds of states. GenVhdl filtered out. The results are comparable to those
maps the ODE state space formulation into the FPGA obtained with SymPowerSystems from Mathworks,
using a priori algorithm. GenVhdl takes into account which is a commercial power system simulator tool
some parameters such as the number of VVMs to use largely used by electrical utilities and research centers
for the simulation, matrices dimensions, MAC pipeline [6]. The simulation used a fixed timestep Ts shown in
latency and the number of clocks per timestep to the schematic diagrams.
calculate the optimum distribution of VVMs per Lon=225uH@ O1us
Ron=0.l
Discrete,
Ts, l.-005.
matrices that minimizes the timestep. The current
implementation can solve a state space with 10 states
in less than 0.4 gs.
mem 0 MAC 0
MemAdd n
en
clk
blockRam ~~~~~Register file
mem 1MAC 1 ~~~~~X(O)
addr q mem res ~~~X(1)
___add r q f mem ries

mem-n MAC-n ~~~~~X(n-1)

en Sig ~~~~~~~~X(n)
m
Figure 13. Three-Phase DC-AC PWM converter

SigAddr X U SigAddr
U(O) X C__

U(n)
Figure 12. State Space Solver Macro Architecture

8. Others Modules
Besides the modules presented in the previous
sections, the VHDL system library includes PEs to
realize many others functions such as voltage and
current sources, Delta-Sigma and PWM modulators, PI
and PID controllers, digital filters, Clark/Park
transforms, etc. The implementation of some of these
modules and their experimental results are presented in
[15] [16]. Figure 14. Simulation Results Using FPGASim
10. Conclusion
[5] T.L. Skvarenina, "The Power Electronics Handbook,"
This work presented the implementation of a CRC Press, 2002.
DRTPSS which is fully realized in a FPGA. The [6] SimPowerSystems, Matlab Inc., 2005.
results demonstrate that modern FPGAs are effective
platform for implementing simulation algorithms and [7] ISE Development System, Xilinx Inc., 2005.
can compete favorably with high-performance
microprocessors and DSPs in applications where the [8] M. Matar, M. Abdel-Rahman, A. Soliman, "FPGA-Based
algorithms can be parallelized. The test environment Real-Time Digital Simulation," International Conference on
built consists of an AMD XP2400+ microcomputer Power Systems Transients (IPST'2005), 2005.
and a Digilent Inc. XUP Virtex II Pro Development
[9] G.R. Morris and V.K. Prasanna, "Pipelined Datapath for
FPGA Card with a 2VP30-7-FF896 Virtex II Pro an IEEE-754 64-Bit Floating-Point Jacobi Solver," 9th High
FPGA. Currently, we can simulate small and medium Performance Embedded Computing Workshop, 2005.
size power electronics networks such as DC-AC
converters, AC-AC cicloconverters, etc. with a [10] J. Franca, A. Petraglia and S. K. Mitra, "Multirate
timestep smaller than .4 gs. We should notice that the Analog-Digital Systems for Signal Processing and
smallest timestep reported in the literature is around 2 conversi6n," Proceedings of the IEEE, Vol. 85, No. 2,
gs. The non linear PEs can run at a time step of about
February 1997.
0.2 gs. Therefore, the state space solver is the system [11] B. Parhami, "Computer Arithmetic: Algorithms and
bottleneck. We recently found inefficiencies in the Hardware Designs," Oxford University Press, 2000.
MAC design that should allow us to run it at 200 MHz.
Also, we devised a better way of coordinating the [12] D.J. Smith, "HDL Chip Design: A Practical Guide for
VVMs to increase the number of operations per Designing, synthesizing and simulating ASICs and FPGAs
timestep. We estimate these changes combined should Using VHDL or Verilog," Doone Publications, 8th Ed. 2000.
allow the linear PEs to achieve a timestep of 0.2 gs.
[13] A. Ralston and P. Rabinowitz, "A First Course in
Numerical Analysis," 2nd Ed. Dover Publications Inc., 2001.
11. Acknowledgement
[14] L.O. Chua and P.Y. Lin, "Computer-Aided Analysis of
J. C. G. Pimentel thanks Xilinx Inc. for its support Electronic Circuits: Algorithms and Computational
providing the FPGA development kit used for the Techniques," Prentice Hall, 1975.
simulation and experimental results, and Dr. Yosef
Tirat-Gefen at Castel Research Inc., Dr. Guilherme [15] J.C.G. Pimentel, H. Le-Huy and G. Sybille, "A VHDL
DeSouza at Univ. of Missouri-Columbia and Dr. Library of IP Cores for Power Drive and Motion Control
Antonio Mesquita at COPPE/UFRJ for valuable Applications," CCECE'2000, 2000.
feedback during the preparation of this paper. [16] J.C.G. Pimentel, H. Le-Huy and G. Sybille, "An FPGA-
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