Encoders

An Encoder is a combinational circuit that performs the reverse operation of

Decoder. It has maximum of 2n input lines and ‘n’ output lines. It will produce a
binary code equivalent to the input, which is active High. Therefore, the encoder
encodes 2n input lines with ‘n’ bits. It is optional to represent the enable signal
in encoders.
4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0.
The block diagram of 4 to 2 Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective
binary code at the output. The Truth table of 4 to 2 encoder is shown below.
Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as
 A1=Y3+Y2, A1=Y3+Y2
A0=Y3+Y1, A0=Y3+Y1
We can implement the above two Boolean functions by using two input OR
gates. The circuit diagram of 4 to 2 encoder is shown in the following figure.

The above circuit diagram contains two OR gates. These OR gates encode the
four inputs with two bits
Octal to Binary Encoder
Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 &
A0. Octal to binary encoder is nothing but 8 to 3 encoder. The block diagram of
octal to binary Encoder is shown in the following figure.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective
binary code. The Truth table of octal to binary encoder is shown below.
 Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as

A2=Y7+Y6+Y5+Y4A2=Y7+Y6+Y5+Y4
A1=Y7+Y6+Y3+Y2A1=Y7+Y6+Y3+Y2
A0=Y7+Y5+Y3+Y1A0=Y7+Y5+Y3+Y1

We can implement the above Boolean functions by using four input OR gates.
The circuit diagram of octal to binary encoder is shown in the following figure.
The above circuit diagram contains three 4-input OR gates. These OR gates
encode the eight inputs with three bits.

Decoders

Decoder is a combinational circuit that has ‘n’ input lines and maximum of
2n output lines. One of these outputs will be active High based on the
combination of inputs present, when the decoder is enabled. That means decoder
detects a particular code. The outputs of the decoder are nothing but the min
terms of ‘n’ input variables lines, when it is enabled.

2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0.
The block diagram of 2 to 4 decoder is shown in the following figure.
One of these four outputs will be ‘1’ for each combination of inputs when enable,
E is ‘1’. The Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as
Y3=E.A1.A0Y3=E.A1.A0
Y2=E.A1.A0′Y2=E.A1.A0′
Y1=E.A1′.A0Y1=E.A1′.A0
Y0=E.A1′.A0′Y0=E.A1′.A0′
Each output is having one product term. So, there are four product terms in total.
We can implement these four product terms by using four AND gates having
three inputs each & two inverters. The circuit diagram of 2 to 4 decoder is
shown in the following figure.

Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two
input variables A1 & A0, when enable, E is equal to one. If enable, E is zero, then
all the outputs of decoder will be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A2,
A1 & A0 and 4 to 16 decoder produces sixteen min terms of four input variables
A3, A2, A1 & A0.
3 to 8 Decoder
In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know
that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas,
3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
We can find the number of lower order decoders required for implementing
higher order decoder using the following formula.
 Required number of lower order decoders = m2/m1
Were,

m1- is the number of outputs of lower order decoder.

m2- is the number of outputs of higher order decoder.
Here, m1 = 4 and m2 = 8.
Substitute, these two values in the above formula.
Required number of 2 to 4 decoders = 8/4 = 2

Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder.

The block diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the
following figure.

The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The complement
of input A2 is connected to Enable, E of lower 2 to 4 decoder in order to get the
outputs, Y3 to Y0. These are the lower four min terms. The input, A2 is directly
connected to Enable, E of upper 2 to 4 decoder in order to get the outputs, Y 7 to
Y4. These are the higher four min terms.
 Multiplexers
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line. One of these data inputs will be connected
to the output based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros
and ones. So, each combination will select only one data input. Multiplexer is
also called as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and
one output Y. The block diagram of 4x1 Multiplexer is shown in the following
figure.

One of these 4 inputs will be connected to the output based on the combination
of inputs present at these two selection lines. Truth table of 4x1 Multiplexer is
shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2
 1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
We can implement this Boolean function using Inverters, AND gates & OR gate.
The circuit diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can
implement 8x1 Multiplexer and 16x1 multiplexer by following the same
procedure.

8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1
Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines
and one output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines
and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data
inputs. Since, each 4x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as inputs
and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 &
s0 and one output Y. The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8x1 Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 8x1 Multiplexer is
shown in the following figure.
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data
inputs of upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1
Multiplexer are I3 to I0. Therefore, each 4x1 Multiplexer produces an output
based on the values of selection lines, s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1
Multiplexer that is present in second stage. The other selection line, s2 is applied
to 2x1 Multiplexer.
 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs
I3 to I0 based on the values of selection lines s1 & s0.
 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs
I7 to I4 based on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1
Multiplexer performs as one 8x1 Multiplexer.
16x1 Multiplexer
In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and
2x1 Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3 selection
lines and one output. Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection
lines and one output.
So, we require two 8x1 Multiplexers in first stage in order to get the 16 data
inputs. Since, each 8x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as inputs
and to produce the final output.
Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s3 to
s0 and one output Y. The Truth table of 16x1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9
 1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

We can implement 16x1 Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 16x1 Multiplexer is
shown in the following figure.
The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The
data inputs of upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1
Multiplexer are I7 to I0. Therefore, each 8x1 Multiplexer produces an output
based on the values of selection lines, s2, s1 & s0.
The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1
Multiplexer that is present in second stage. The other selection line, s3 is applied
to 2x1 Multiplexer.
 If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs
Is7 to I0 based on the values of selection lines s2, s1 & s0.
 If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs
I15 to I8 based on the values of selection lines s2, s1 & s0.
Therefore, the overall combination of two 8x1 Multiplexers and one 2x1
Multiplexer performs as one 16x1 Multiplexer.