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Assignment Project

Students will work in groups to modify a datapath to perform new instructions and present their work. The new instructions include load word register, add 3 operands, add to memory, branch on less than or equal, branch equal to memory, branch equal to 0 to immediate, store word and increment, and store word and decrement. Students must minimize additional hardware and clock cycles when adding each new instruction.

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65 views

Assignment Project

Students will work in groups to modify a datapath to perform new instructions and present their work. The new instructions include load word register, add 3 operands, add to memory, branch on less than or equal, branch equal to memory, branch equal to 0 to immediate, store word and increment, and store word and decrement. Students must minimize additional hardware and clock cycles when adding each new instruction.

Uploaded by

shvdo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Assignment Project: Multi‐Cycle Datapath Adding instructions

Students will work in groups of no less than 2 and no more than 3. All groups will present their work to the class in the last week (i.e. between 14/5/2023
to 18/5/2023) with no exceptions, and submit their report to me on course Moodle for grading.

1. Datapath Modification
Modify the datapath and control signals to perform the new instructions in the corresponding datapath. Use the minimal amount of additional hardware and
clock cycles/control states.

Remember:
 When adding new instructions, don't break the operation of the standard ones.
 Avoid adding ALUs, adders, Reg Files, or memories to the datapath
 You can add MUXes, logic gates, etc. but try to do minimally. (these cost in terms of area, cycle time, etc)
 You can add or remove step(s) to the datapath execution if it’s necessary, but try to do minimally

The new Instruction to be added to the standard multicycle datapath


1. Load Word Register (uses R instruction format)
lwr Rt, Rd (Rs) #Reg[Rt] = Mem[Reg[Rd]+Reg[Rs]]
2. Add 3 operands (new instruction format: opcode(6), rs(5), rt(5), rd(5), rx(5), (6 bits not used))
add3 Rd, Rs, Rt, Rx #Reg[Rd] = Reg[Rs] + Reg[Rt] + Reg[Rx]
3. Add to Memory (new instruction format: opcode(6), rs(5), rt(5), rd(5), offset(11))
addm Rd, Rt, Offset(Rs) #Reg[Rd] = Reg[Rt] + Mem[sign extended offset + Reg[Rs]]
4. Branch on less than or Equal (uses I instruction format)
blez Rs, label # if Reg[Rs] < 0, PC = PC+4 + (sign‐extended offset << 2)
5. Branch Equal to Memory (new instruction format: opcode(6), rs(5), rt(5), rd(5), offset(11))
beqm Rd, Rt, Offset(Rs) # if Reg[Rt] = Mem[Offset+Reg[Rs]], PC = PC + 4 + Reg[Rd]
6. Branch Equal to 0 to Immediate (uses R instruction format)
beqzi (Rs), Label #if Mem[Reg[Rs]] = 0, then PC = PC + (sign‐extended offset) (NOTE: This is not PC+4, and not shifted by 2)
7. Store Word and Increment
swinc Rt, offset(Rs) #Mem[Reg[Rs] + sign extended offset]= Reg[Rt], Reg[Rs] = Reg[Rs] + 4
8. Store Word and Decrement
swdec Rt, offset(Rs) #Mem[Reg[Rs] + sign extended offset] = Reg[Rt], Reg[Rs] = Reg[Rs] – 4

Note: Treat each new added instruction separately i.e. Each new added instruction is treated as the only one to be added to the standard datapath showing the
necessary added gates and control signals

2. Datapath Timing
Calculate the delay and the minimal clock cycle in the modified datapaths when performing each new instruction above. Assume the following delays:
 Memory: 200ps
 Register Files Access (READ/Write): 50ps
 ALU and adders: 100ps
 Logic Gates and Multiplexors: 1ps
 All other times are negligible

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