162 Chapter 2 Instructions: Language of the Computer

Frequency
Instruction class RISC-V examples HLL correspondence Integer Fl. Pt.
Arithmetic add, sub, addi Operations in assignment statements 16% 48%
Data transfer ld, sd, lw, sw, lh, References to data structures in memory 35% 36%
sh, lb, sb, lui
Logical and, or, xor, sll, Operations in assignment statements 12% 4%
srl, sra
Branch beq, bne, blt, bge, If statements; loops 34% 8%
bltu, bgeu
Jump jal, jalr Procedure calls & returns; switch statements 2% 0%

FIGURE 2.41 RISC-V instruction classes, examples, correspondence to high-level program language
constructs, and percentage of RISC-V instructions executed by category for the average integer and
floating point SPEC CPU2006 benchmarks. Figure 3.24 in Chapter 3 shows average percentage of the individual
RISC-V instructions executed.

2.21
2.21 Historical Perspective and Further
Reading

This section surveys the history of instruction set architectures (ISAs) over
time, and we give a short history of programming languages and compilers.
ISAs include accumulator architectures, general-purpose register architectures,
stack architectures, and a brief history of the x86 and ARM’s 32-bit architecture,
ARMv7. We also review the controversial subjects of high-level-language
computer architectures and reduced instruction set computer architectures. The
history of programming languages includes Fortran, Lisp, Algol, C, Cobol, Pascal,
Simula, Smalltalk, C++, and Java, and the history of compilers includes the key
milestones and the pioneers who achieved them. The rest of Section 2.21 is
found online.

2.22 Exercises

2.1 [5] <§2.2> For the following C statement, write the corresponding RISC-V
assembly code. Assume that the C variables f, g, and h, have already been placed
in registers x5, x6, and x7 respectively. Use a minimal number of RISC-V assembly
instructions.
f = g + (h − 5);

Ejecicios sugeridos: 2.1, 2.2, 2.3, 2.4, 2.7, 2.8, 2.17, 2.20,
2.21, 2.24, 2.25, 2.27
 2.22 Exercises 163

2.2 [5] <§2.2> Write a single C statement that corresponds to the two RISC-V
assembly instructions below.
add f, g, h
add f, i, f

2.3 [5] <§§2.2, 2.3> For the following C statement, write the corresponding
RISC-V assembly code. Assume that the variables f, g, h, i, and j are assigned to
registers x5, x6, x7, x28, and x29, respectively. Assume that the base address
of the arrays A and B are in registers x10 and x11, respectively.
B[8] = A[i−j];

2.4 [10] <§§2.2, 2.3> For the RISC-V assembly instructions below, what is the
corresponding C statement? Assume that the variables f, g, h, i, and j are assigned
to registers x5, x6, x7, x28, and x29, respectively. Assume that the base
address of the arrays A and B are in registers x10 and x11, respectively.
slli x30, x5, 3 // x30 = f*8
add x30, x10, x30 // x30 = &A[f]
slli x31, x6, 3 // x31 = g*8
add x31, x11, x31 // x31 = &B[g]
ld x5, 0(x30) // f = A[f]

addi x12, x30, 8

ld x30, 0(x12)
add x30, x30, x5
sd x30, 0(x31)

2.5 [5] <§2.3> Show how the value 0xabcdef12 would be arranged in memory
of a little-endian and a big-endian machine. Assume the data are stored starting at
address 0 and that the word size is 4 bytes.

2.6 [5] <§2.4> Translate 0xabcdef12 into decimal.

2.7 [5] <§§2.2, 2.3> Translate the following C code to RISC-V. Assume that the
variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29,
respectively. Assume that the base address of the arrays A and B are in registers x10
and x11, respectively. Assume that the elements of the arrays A and B are 8-byte
words:
B[8] = A[i] + A[j];

2.8 [10] <§§2.2, 2.3> Translate the following RISC-V code to C. Assume that the
variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29,
164 Chapter 2 Instructions: Language of the Computer

respectively. Assume that the base address of the arrays A and B are in registers x10
and x11, respectively.
addi x30, x10, 8
addi x31, x10, 0
sd x31, 0(x30)
ld x30, 0(x30)
add x5, x30, x31

2.9 [20] <§§2.2, 2.5> For each RISC-V instruction in Exercise 2.8, show the value
of the opcode (op), source register (rs1), and destination register (rd) fields. For
the I-type instructions, show the value of the immediate field, and for the R-type
instructions, show the value of the second source register (rs2). For non U- and
UJ-type instructions, show the funct3 field, and for R-type and S-type instructions,
also show the funct7 field.

2.10 Assume that registers x5 and x6 hold the values 0x8000000000000000

and 0xD000000000000000, respectively.
2.10.1 [5] <§2.4> What is the value of x30 for the following assembly code?
add x30, x5, x6
2.10.2 [5] <§2.4> Is the result in x30 the desired result, or has there been
overflow?
2.10.3 [5] <§2.4> For the contents of registers x5 and x6 as specified above,
what is the value of x30 for the following assembly code?
sub x30, x5, x6
2.10.4 [5] <§2.4> Is the result in x30 the desired result, or has there been
overflow?
2.10.5 [5] <§2.4> For the contents of registers x5 and x6 as specified above,
what is the value of x30 for the following assembly code?
add x30, x5, x6
add x30, x30, x5

2.10.6 [5] <§2.4> Is the result in x30 the desired result, or has there been
overflow?

2.11 Assume that x5 holds the value 128ten.

2.11.1 [5] <§2.4> For the instruction add x30, x5, x6, what is the range(s)
of values for x6 that would result in overflow?
2.11.2 [5] <§2.4> For the instruction sub x30, x5, x6, what is the range(s)
of values for x6 that would result in overflow?
 2.22 Exercises 165

2.11.3 [5] <§2.4> For the instruction sub x30, x6, x5, what is the range(s)
of values for x6 that would result in overflow?

2.12 [5] <§§2.2, 2.5> Provide the instruction type and assembly language
instruction for the following binary value:
0000 0000 0001 0000 1000 0000 1011 0011two
Hint: Figure 2.20 may be helpful.

2.13 [5] <§§2.2, 2.5> Provide the instruction type and hexadecimal representation
of the following instruction:
sd x5, 32(x30)

2.14 [5] <§2.5> Provide the instruction type, assembly language instruction, and
binary representation of instruction described by the following RISC-V fields:
opcode=0x33, funct3=0x0, funct7=0x20, rs2=5, rs1=7, rd=6

2.15 [5] <§2.5> Provide the instruction type, assembly language instruction, and
binary representation of instruction described by the following RISC-V fields:
opcode=0x3, funct3=0x3, rs1=27, rd=3, imm=0x4

2.16 Assume that we would like to expand the RISC-V register file to 128 registers
and expand the instruction set to contain four times as many instructions.
2.16.1 [5] <§2.5> How would this affect the size of each of the bit fields in the
R-type instructions?
2.16.2 [5] <§2.5> How would this affect the size of each of the bit fields in the
I-type instructions?
2.16.3 [5] <§§2.5, 2.8, 2.10> How could each of the two proposed changes
decrease the size of a RISC-V assembly program? On the other hand, how could
the proposed change increase the size of an RISC-V assembly program?

2.17 Assume the following register contents:

x5 = 0x00000000AAAAAAAA, x6 = 0x1234567812345678
2.17.1 [5] <§2.6> For the register values shown above, what is the value of x7 for
the following sequence of instructions?
slli x7, x5, 4
or x7, x7, x6
166 Chapter 2 Instructions: Language of the Computer

2.17.2 [5] <§2.6> For the register values shown above, what is the value of x7 for
the following sequence of instructions?
slli x7, x6, 4
2.17.3 [5] <§2.6> For the register values shown above, what is the value of x7 for
the following sequence of instructions?
srli x7, x5, 3
andi x7, x7, 0xFEF

2.18 [10] <§2.6> Find the shortest sequence of RISC-V instructions that extracts
bits 16 down to 11 from register x5 and uses the value of this field to replace bits 31
down to 26 in register x6 without changing the other bits of registers x5 or x6. (Be
sure to test your code using x5 = 0 and x6 = 0xffffffffffffffff. Doing so
may reveal a common oversight.)

2.19 [5] <§2.6> Provide a minimal set of RISC-V instructions that may be used
to implement the following pseudoinstruction:
not x5, x6 // bit-wise invert

2.20 [5] <§2.6> For the following C statement, write a minimal sequence of
RISC-V assembly instructions that performs the identical operation. Assume x6 =
A, and x17 is the base address of C.

A = C[0] << 4;

2.21 [5] <§2.7> Assume x5 holds the value 0x00000000001010000. What is

the value of x6 after the following instructions?
bge x5, x0, ELSE
jal x0, DONE
ELSE: ori x6, x0, 2
DONE:

2.22 Suppose the program counter (PC) is set to 0x20000000.

2.22.1 [5] <§2.10> What range of addresses can be reached using the RISC-V
jump-and-link (jal) instruction? (In other words, what is the set of possible values
for the PC after the jump instruction executes?)
2.22.2 [5] <§2.10> What range of addresses can be reached using the RISC-V
branch if equal (beq) instruction? (In other words, what is the set of possible values
for the PC after the branch instruction executes?)
 2.22 Exercises 167

2.23 Consider a proposed new instruction named rpt. This instruction combines
a loop’s condition check and counter decrement into a single instruction. For
example rpt x29, loop would do the following:
if (x29 > 0) {
x29 = x29 −1;
goto loop
}

2.23.1 [5] <§2.7, 2.10> If this instruction were to be added to the RISC-V
instruction set, what is the most appropriate instruction format?
2.23.2 [5] <§2.7> What is the shortest sequence of RISC-V instructions that
performs the same operation?

2.24 Consider the following RISC-V loop:

LOOP: beq x6, x0, DONE

addi x6, x6, -1
addi x5, x5, 2
jal x0, LOOP
DONE:

2.24.1 [5] <§2.7> Assume that the register x6 is initialized to the value 10. What
is the final value in register x5 assuming the x5 is initially zero?
2.24.2 [5] <§2.7> For the loop above, write the equivalent C code. Assume that
the registers x5 and x6 are integers acc and i, respectively.
2.24.3 [5] <§2.7> For the loop written in RISC-V assembly above, assume that
the register x6 is initialized to the value N. How many RISC-V instructions are
executed?
2.24.4 [5] <§2.7> For the loop written in RISC-V assembly above, replace the
instruction “beq x6, x0, DONE” with the instruction “blt x6, x0, DONE”
and write the equivalent C code.

2.25 [10] <§2.7> Translate the following C code to RISC-V assembly code. Use
a minimum number of instructions. Assume that the values of a, b, i, and j are in
registers x5, x6, x7, and x29, respectively. Also, assume that register x10 holds
the base address of the array D.
for(i=0; i<a; i++)
for(j=0; j<b; j++)
D[4*j] = i + j;
168 Chapter 2 Instructions: Language of the Computer

2.26 [5] <§2.7> How many RISC-V instructions does it take to implement the
C code from Exercise 2.25? If the variables a and b are initialized to 10 and 1 and
all elements of D are initially 0, what is the total number of RISC-V instructions
executed to complete the loop?

2.27 [5] <§2.7> Translate the following loop into C. Assume that the C-level
integer i is held in register x5,x6 holds the C-level integer called result, and
x10 holds the base address of the integer MemArray.

addi x6, x0, 0

addi x29, x0, 100
LOOP: ld x7, 0(x10)
add x5, x5, x7
addi x10, x10, 8
addi x6, x6, 1
blt x6, x29, LOOP

2.28 [10] <§2.7> Rewrite the loop from Exercise 2.27 to reduce the number of
RISC-V instructions executed. Hint: Notice that variable i is used only for loop
control.

2.29 [30] <§2.8> Implement the following C code in RISC-V assembly. Hint:
Remember that the stack pointer must remain aligned on a multiple of 16.
int fib(int n){
if (n==0)
return 0;
else if (n == 1)
return 1;
else
return fib(n−1) + fib(n−2);
}

2.30 [20] <§2.8> For each function call in Exercise 2.29, show the contents of the
stack after the function call is made. Assume the stack pointer is originally at address
0x7ffffffc, and follow the register conventions as specified in Figure 2.11.

2.31 [20] <§2.8> Translate function f into RISC-V assembly language. Assume
the function declaration for g is int g(int a, int b). The code for function
f is as follows:

int f(int a, int b, int c, int d){

return g(g(a,b), c+d);

}