Midterm Exam

Design of aTwo-Stage Miller Compensated OTA

Contents
Introduction ................................................................................................................................................ 2
Objective .................................................................................................................................................... 2
OTA Specifications ..................................................................................................................................... 2
Design Procedure of the Operational Transconductance Amplifier (OTA) ............................................... 3
Topology Selection ................................................................................................................................. 3
Charts Generation ................................................................................................................................... 3
Design Steps ........................................................................................................................................... 3
Simulations ................................................................................................................................................. 3
DC Analysis ............................................................................................................................................ 3
AC Analysis ............................................................................................................................................ 3
STB Analysis .......................................................................................................................................... 3
Transient Analysis................................................................................................................................... 3
Pole Splitting .......................................................................................................................................... 4
Effect of Large Load Capacitance .......................................................................................................... 4

Important Instructions
- This is a group task (max 4 students per group), do not cooperate between groups, otherwise
your grade will be affected.
- Report your answers in the answer sheet template, do not create your own document.
- The deadline for submitting your report is the 14th of April.
- Submission is through Moodle.

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Introduction
The two-stage miller compensated OTA is an important circuit for analog designers. It is widely used
in many analog circuits and has various applications. Its most advantage lies in providing high gain
while also maintaining high output voltage swing which is achieved by the two-stage configuration.
The first stage which consists of the 5T-OTA provides high gain, and the second stage which consists
of a common source amplifier with active load provides the high output swing while also providing
some moderate gain that adds up to the gain provided by the first stage.

Objective
The aim of this lab is to design a Two-Stage Miller Compensated OTA. Validate the design by
performing DC, AC, Stability, and Transient analysis. Also, the importance of the miller
compensation capacitance will be investigated by observing the pole splitting that is caused by
inserting the miller compensating capacitance. The effect of adding a high load capacitance will also
be investigated.

OTA Specifications
Design the OTA to achieve the following specification.

𝑉𝐷𝐷 1.2 V
𝐼𝑅𝑒𝑓 10 𝜇𝐴
𝐴𝑣 𝑂𝐿 𝐷𝑖𝑓𝑓 ≥ 62 dB
𝐶𝑀𝑅𝑅 ≥ 65 dB
𝐶𝑀𝐼𝑅ℎ𝑖𝑔ℎ ≤1V
𝐶𝑀𝐼𝑅𝑙𝑜𝑤 ≥ 0.6 V
𝐶𝐿 1 𝑝𝐹
𝐶𝑐 0.6 𝐶𝐿
GBW ≥ 8 MHz
PM ≥ 60
Power Consumption ≤ 50 𝜇𝑊

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Design Procedure of the Operational Transconductance Amplifier (OTA)
1) Topology Selection
The first step of any design is the selection of the topology. From the proposed specs, report
the selected topology that will be used for designing the OTA, explain the reasons for
choosing it.

2) Charts Generation
Designing the circuit means getting the aspect ratio (width and length) of all transistors. To
do so, you may need to generate some design charts to help you through the design.

3) Design Steps
- Report the detailed design steps and the hand calculations performed for designing the
OTA.
- Report a table showing the sizing of all transistors.

Simulations
1) DC Analysis
• Perform DC Analysis, set the input CM level to be half that of the input CM range (0.8 V).
• Check the operating points for all transistors.
• Check that all transistors are operating in saturation region.
• Report a screenshot from the schematic with the DC operating points (𝐼𝐷 , 𝑉𝑔𝑠 , 𝑔𝑚 , Region)
and DC node voltages clearly annotated.

2) AC Analysis
• Set the AC magnitude of the input differential voltage source to be equal to one.
• Set the input CM level to be half that of the input CM range.
• Perform AC Analysis.
• Plot the DC Gain in dB, does it achieve the specification ?
• From the plotted curve, annotate the BW and the GBW of the amplifier, did they achieve the
specification ?

3) STB Analysis
• Put the OTA in a closed loop configuration (buffer configuration).
• Run STB Analysis, adjust its settings.
• Plot the Loop Gain of the amplifier in dB.
• Check the Phase Margin of the amplifier, is the amplifier stable?

4) Transient Analysis
• Use the same test bench as used in the stb analysis, apply a step input using a pulse input having
a large period.
• Plot the input and output signals overlaid.
• Use the calculator to get the value for the slew rate, illustrate how the value of the slew rate be
improved.

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 • Apply a sudden change (vpulse) to the positive input of the amplifier and plot the output voltage.
• Hint: settings of the vpulse (Voltage 1 = 800 mV, Voltage 2 = 900 mV, period = 600 nS, rise
and fall time = 10pF, pulse width = 300nS)

5) Pole Splitting
• To observe the pole splitting, perform parametric sweep over the compensation capacitance 𝐶𝐶
(keep the OTA in a closed loop configuration).
• Run stb Analysis.
• Plot the phase margin.

• Run PZ Analysis for two values of 𝐶𝑐 .

• Plot the poles and zeros appended for the two scenarios, in the same graph.
• Comment on the graphs.

6) Effect of Large Load Capacitance

• Keep the OTA in a closed loop configuration, perform parametric sweep over the load
capacitance 𝐶𝐿 (0.1 p: 0.1p: 5p).
• Run stb Analysis.
• Plot the phase margin.
• Comment on the graphs.

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