PIC16F627A/628A/648A

6.0 TIMER0 MODULE 6.2 Using Timer0 with External Clock

The Timer0 module timer/counter has the following When an external clock input is used for Timer0, it must
features: meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
• 8-bit timer/counter
synchronization. Also, there is a delay in the actual
• Read/write capabilities incrementing of Timer0 after synchronization.
• 8-bit software programmable prescaler
• Internal or external clock select 6.2.1 EXTERNAL CLOCK
• Interrupt on overflow from FFh to 00h SYNCHRONIZATION
• Edge select for external clock When no prescaler is used, the external clock input is
Figure 6-1 is a simplified block diagram of the Timer0 the same as the prescaler output. The synchronization
module. Additional information is available in the “PIC® of T0CKI with the internal phase clocks is
Mid-Range MCU Family Reference Manual” (DS33023). accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
Timer mode is selected by clearing the T0CS bit (Figure 6-1). Therefore, it is necessary for T0CKI to be
(OPTION<5>). In Timer mode, the TMR0 register value high for at least 2TOSC (and a small RC delay of 20 ns)
will increment every instruction cycle (without and low for at least 2TOSC (and a small RC delay of
prescaler). If the TMR0 register is written to, the 20 ns). Refer to the electrical specification of the
increment is inhibited for the following two cycles. The desired device.
user can work around this by writing an adjusted value
to the TMR0 register. When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
Counter mode is selected by setting the T0CS bit. In prescaler so that the prescaler output is symmetrical.
this mode the TMR0 register value will increment either For the external clock to meet the sampling
on every rising or falling edge of pin RA4/T0CKI/CMP2. requirement, the ripple-counter must be taken into
The incrementing edge is determined by the source account. Therefore, it is necessary for T0CKI to have a
edge (T0SE) control bit (OPTION<4>). Clearing the period of at least 4TOSC (and a small RC delay of 40 ns)
T0SE bit selects the rising edge. Restrictions on the divided by the prescaler value. The only requirement
external clock input are discussed in detail in on T0CKI high and low time is that they do not violate
Section 6.2 “Using Timer0 with External Clock”. the minimum pulse width requirement of 10 ns. Refer to
The prescaler is shared between the Timer0 module parameters 40, 41 and 42 in the electrical specification
and the Watchdog Timer. The prescaler assignment is of the desired device. See Table 17-8.
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4,..., 1:256 are
selectable. Section 6.3 “Timer0 Prescaler” details
the operation of the prescaler.

6.1 Timer0 Interrupt

Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut
off during Sleep.

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6.3 Timer0 Prescaler The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog When assigned to the Timer0 module, all instructions
Timer. A prescaler assignment for the Timer0 module writing to the TMR0 register (e.g.,
means that there is no postscaler for the Watchdog ) will clear the prescaler. When
Timer, and vice-versa. assigned to WDT, a instruction will clear the
prescaler along with the Watchdog Timer. The prescaler
is not readable or writable.

FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT

FOSC/4 Data Bus

T0CKI SYNC
pin 2 TMR0 Reg
Cycles

T0SE
T0CS
Set flag bit T0IF
TMR1 Clock Source PSA on Overflow

0
WDT Postscaler/
Watchdog TMR0 Prescaler
1
Timer
8
PSA
8-to-1MUX PS<2:0>

WDT Enable bit

1
WDT
0 Time-out

PSA

Note: T0SE, T0CS, PSA,. PS<2:0> are bits in the Option Register.

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 PIC16F627A/628A/648A
6.3.1 SWITCHING PRESCALER To change prescaler from the WDT to the Timer0
ASSIGNMENT module, use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
EXAMPLE 6-2: CHANGING PRESCALER
program execution). Use the instruction sequences
(WDT TIMER0)
shown in Example 6-1 when changing the prescaler
assignment from Timer0 to WDT, to avoid an
unintended device Reset.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0 WDT)

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Value on
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other
POR
Resets
01h, 101h TMR0 Timer0 Module Register
0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
10Bh, 18Bh
81h, 181h OPTION(2) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: = Unimplemented locations, read as ‘ ’, = unchanged, = unknown. Shaded cells are not used for Timer0.
Note 1: Option is referred by in MPLAB® IDE Software.

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4.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for
The Option register is a readable and writable register,
TMR0, assign the prescaler to the WDT
which contains various control bits to configure the
(PSA = ). See Section 6.3.1 “Switching
TMR0/WDT prescaler, the external RB0/INT interrupt,
Prescaler Assignment”.
TMR0 and the weak pull-ups on PORTB.

REGISTER 4-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

= PORTB pull-ups are disabled
= PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
= Interrupt on rising edge of RB0/INT pin
= Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
= Transition on RA4/T0CKI/CMP2 pin
= Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
= Increment on high-to-low transition on RA4/T0CKI/CMP2 pin
= Increment on low-to-high transition on RA4/T0CKI/CMP2 pin
bit 3 PSA: Prescaler Assignment bit
= Prescaler is assigned to the WDT
= Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
1:2 1:1
1:4 1:2
1:8 1:4
1 : 16 1:8
1 : 32 1 : 16
1 : 64 1 : 32
1 : 128 1 : 64
1 : 256 1 : 128

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

2007 Microchip Technology Inc. DS40044F-page 23