ADC Programming

The ADC module in the LPC1768 uses the technique of

successive approximation to convert signals from analog to
digital values. The internal SAR (Successive Approximation
Register) is designed to take the input from a voltage
comparator of the internal module to give a 12-bit output
resulting in a high precision result.

Va = ( Vref/212 )* Dval
Successive Approximation
 ADC Registers

Register Description
ADCR A/D COntrol Register: Used for
Configuring the ADC
ADGDR A/D Global Data Register: This register
contains the ADC’s DONE bit and the
result of the most recent A/D conversion
ADINTEN A/D Interrupt Enable Register
ADDR0 - ADDR7 A/D Channel Data Register: Contains the
recent ADC value for respective channel
ADSTAT A/D Status Register: Contains DONE &
OVERRUN flag for all the ADC channels
ADCR – A/D Control Register :
• Bits[7:0] – SEL: Bit ‘x'(in this group) is used to select AD0.x
• Bits[15:8] – CLKDIV: ADC Peripheral clock i.e. PCLK_ADC0 is
divided by CLKDIV+1 to get the ADC clock.
• Bit[16] – BURST: Set to 1 for doing repeated conversions, else 0
for software controlled conversions. Note: START bits must be set
to 000 when BURST=1 or conversions will not start. The
conversion is started scanning through the pins selected by bits
set to ones in the SEL field. The first conversion corresponds to
the least-significant 1 in the SEL field, then higher numbered 1-
bits. Repeated conversions can be terminated by clearing this bit,
but the conversion that’s in progress when this bit is cleared will
be completed. If BURST is set to 1, the ADGINTEN bit in the
ADINTEN register must be set to 0.
• Bit[21] – PDN : Set it to 1 for powering up the ADC and
making it operational. Set it to 0 for bringing it in power down
mode.
• Bits[26:24] – START: These bits are used to control the start of
ADC conversion when BURST (bit 16) is set to 0. 000 = No
start, 001 = Start the conversion.
• Bit[27] – EDGE: Set this bit to 1 to start the conversion on
falling edge of the selected CAP/MAT signal and set this bit to
0 to start the conversion on rising edge of the selected signal.
(Note: This bit is of used only in the case when the START
contains a value between 010 to 111 as shown above.)
• Other bits are reserved
ADGDR – A/D Global Data Register : Contains the ADC’s flags and the
result of the most recent A/D conversion.
• Bits[15:4] – RESULT: When DONE bit = 1, these bits give a binary
fraction which represents the voltage on the pin AD0.x. Value of 0x0
indicates that voltage on the given pin was less than, equal to or
greater than VREFN. And a value of 0xFFF means that the input voltage
was close to, equal to or greater than the VREFP.
• Bits[26:24] – CHN: Represents the channel from which RESULT bits
were converted. 000= channel 0, 001= channel 1 and so on.
• Bit[30] – OVERRUN: In burst mode this bit is 1 in case of an Overrun
i.e. the result of previous conversion being lost(overwritten). This bit
will be cleared after reading ADGDR.
• Bit[31] – DONE: When ADC conversion completes this bit is 1. When
this register(ADGDR) is read and ADCR is written, this bit gets cleared
i.e. set to 0. If ADCR is written while a conversion is in progress then
this bit is set and a new conversion is started.
• Other bits are reserved.
 ADDR0 to ADDR7 – A/D Data registers : This register contains
the result of the most recent conversion completed on the
corresponding channel [0 to 7]. Its structure is same as ADGDR
except Bits[26:24] are not used/reserved.

Results of ADC conversion can be read in one of two ways.

• One is to use the A/D Global Data Register to read all data from the
ADC.
• Another is to use the A/D Channel Data Registers.
• It is important to use one method consistently because the DONE
and OVERRUN flags can otherwise get out of synch between the
ADGDR and the A/D Channel Data Registers, potentially causing
erroneous interrupts or DMA activity.
A/D Interrupt Enable register (ADINTEN )
• This register allows control over which A/D channels
generate an interrupt when a conversion is complete.
• Bits[7:0] : Enable or disable the generation of interrupt
upon the completion of a conversion on ADC channel
[7:0]. Bit = 1 enables the interrupt and 0 disables
• Bit 8: ADGINTEN: When set to 0, only the individual
ADC channels enabled by ADINTEN7:0 will generate
interrupts.
• Remark: This bit must be set to 0 in burst mode
• When set 1, only the global DONE flag in ADDR is
enabled to generate an interrupt.
• Other bits: Reserved
ADSTAT – A/D Status register : This register contains DONE and
OVERRUN flags for all of the A/D channels along with A/D interrupt
flag.
• Bits[7:0] – DONE[7 to 0]: Here xth bit mirrors DONEx status flag
from the result register for A/D channel x.
• Bits[15:8] – OVERRUN[7 to 0]: Even here the xth bit mirrors
OVERRUNx status flag from the result register for A/D channel x
• Bit 16 – ADINT: This bit represents the A/D interrupt flag. It is 1
when any of the individual A/D channel DONE flags is asserted and
enabled to contribute to the A/D interrupt via the ADINTEN(given
below) register.
• Other bits are reserved.
ADC modes in LPC1768:
1.Software controlled mode : In Software mode only one
conversion will be done at a time. To perform another
conversion we need to re-initiate the process. In software
mode, only 1 bit in the SEL field of ADCR can be 1 i.e. only 1
Channel(i.e. Pin) can be selected for conversion at a time.
Hence conversions can be done only any channel but one at a
time.
2. Burst or Hardware mode : In Burst or Hardware mode,
conversions are performed continuously on the selected
channels in round-robin fashion. Since the conversions
cannot be controlled by software, Overrun may occur in this
mode. Overrun is the case when a previous conversion result
is replaced by new conversion result without previous result
being read i.e. the conversion is lost. Usually an interrupt is
used in Burst mode to get the latest conversion results. This
interrupt is triggered when conversion in one of the selected
channel ends.
Setting up and configuring ADC Module for software controlled mode

• Configure the appropriate PINSEL register for the desired

function depending on the channel used.
• To power up the ADC first the corresponding bit PCONP register
must be set and then the PDN bit in ADCR must be set.
• Also the bit corresponding to the channel and the START bit must
be set
LPC_SC->PCONP |= (1<<12);
LPC_ADC->ADCR = (1<<4)|(1<<21)|(1<<24) // channel ADC0.4
Fetching the conversion result in software controlled
mode :
In software controlled mode we continuously monitor bit 31
in the corresponding channel data register ADDR. If bit 31
changes to 1 from 0, it means that current conversion has
been completed and the result is ready. For example, if we are
using channel 4 of AD0 then we monitor for changes in bit 31
as follows :

while(!(LPC_ADC->ADDR4 & 1<<31));

Then the result is extracted as follows:

adc_temp = (LPC_ADC->ADDR4>>4) & 0xFFF;
Setting up and configuring ADC Module for Burst mode

In burst mode the START bit in ADCR is not used.

In this case we can select multiple channels for
conversion when setting up ADCR. The
conversions start as soon the ADCR is setup.
First the PINSEL register must be configured. Then configure the ADCR
and ADINTEN as follows:
LPC_ADC->ADCR = (1 << 4 | 1 << 5 | 1 << 16 | 1 << 21); //AD0.4.
AD0.5, Burst, PDN
LPC_ADC->ADINTEN = (1 << 4 | 1 << 5); //Enable int
In Burst mode we use an ISR which triggers at the
completion of a conversion in any one of the channel.
Now, we just need to find the Channel for which the
conversion was done. For this we fetch the channel
number from ADGDR which also stores the conversion
result. This can be read as follows:

int channel= (LPC_ADC->ADGDR>>24) & 0x7; //Extract Channel

Number
After knowing the Channel number, we have 2 options to
fetch the conversion result from. Either we can fetch it from
ADGDR or from ADDRx of the corresponding channel.

unsigned long t = LPC_ADC->ADGDR

int currentResult = (t>>4) & 0xFFF; //Extract Conversion Result

Ref:
http://www.ocfreaks.com/lpc1768-adc-programming-tutorial/
https://www.exploreembedded.com/wiki/LPC1768:_ADC_Programming
Chapter 29 of User Manual (UM10360_LPC176x)
 Nested Vector Interrupt Control (NVIC)

In a microcontroller, interrupts serve as a way to

immediately divert the central processing unit from its
current task to another, more important task.

An interrupt can be triggered internally from the microcontroller

(MCU) or externally, by a peripheral. The interrupt alerts the central
processing unit (CPU) to an occurrence such as a time-based event a
change of state, or the start or end of a process.
Interrupts can be triggered internally – from a timer, for example –
or externally, from peripherals.
When an interrupt occurs, an interrupt signal is generated,
which causes the CPU to stop its current operation, save its
current state, and begin the processing program — referred
to as an interrupt service routine (ISR) or interrupt handler —
associated with the interrupt. When the interrupt
processing is complete, the CPU restores its previous state
and resumes where it left off.
• Nested vector interrupt control (NVIC) is a method of
prioritizing interrupts, improving the MCU’s performance and
reducing interrupt latency.
• NVIC also provides implementation schemes for handling
interrupts that occur when other interrupts are being
executed or when the CPU is in the process of restoring its
previous state and resuming its suspended process.
• The term “nested” refers to the fact that in NVIC, a number
of interrupts (up to several hundred in some processors) can
be defined, and each interrupt is assigned a priority, with “0”
being the highest priority. In addition, the most critical
interrupt can be made non-maskable, meaning it cannot be
disabled (masked).
One function of NVIC is to ensure that higher priority interrupts
are completed before lower-priority interrupts, even if the
lower-priority interrupt is triggered first. For example, if a lower-
priority interrupt is being registered or executed and a higher-
priority interrupt occurs, the CPU will stop the lower-priority
interrupt and process the higher-priority one first.
The term “vector” in nested vector interrupt control
refers to the way in which the CPU finds the program, or
ISR, to be executed when an interrupt occurs. Nested
vector interrupt control uses a vector table that contains
the addresses of the ISRs for each interrupt. When an
interrupt is triggered, the processor gets the address
from the vector table.
The prioritization and handling schemes of nested
vector interrupt control reduce the latency and
overhead that interrupts typically introduce and ensure
low power consumption, even with high interrupt
loading on the controller.
The Cortex-M3 processor uses a re-locatable vector table that
contains the address of the function to be executed for a
particular interrupt handler. On accepting an interrupt, the
processor fetches the address from the vector table through
the instruction bus interface. The vector table is located at
address zero at reset, but can be relocated by programming a
control register.

Ref:
https://www.motioncontroltips.com/what-is-nested-vector-interrupt-control-nvic/
 EXTERNAL INTERRUPTS
https://www.exploreembedded.com/wiki/LPC1768:_External_Interrupts