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CA Classes-236-240

The document discusses computer architecture topics including parallel computing, vector architecture, pipelining, and MIMD architecture. Vector machines operate on vectors through vector instructions and utilize vector registers and functional units. MIMD architectures allow multiple instructions across different processors. Key issues in scalable MIMD design are also covered.

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47 views5 pages

CA Classes-236-240

The document discusses computer architecture topics including parallel computing, vector architecture, pipelining, and MIMD architecture. Vector machines operate on vectors through vector instructions and utilize vector registers and functional units. MIMD architectures allow multiple instructions across different processors. Key issues in scalable MIMD design are also covered.

Uploaded by

SrinivasaRao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Architecture Unit 10

Terminal Questions
1. Parallel Computing is the simultaneous use of multiple compute
resources to solve a computational problem. Refer Section 10.2.
2. The core element of Parallel Processing is Cpus. The essential
computing process is the execution of sequence of instruction on Asset
of Data. Refer Section 10.3.
3. The Steven Unger Design Scheme is the initial base for the fine-grained
SIMD architectures. These are generally designed for low-level image
processing applications. Refer Section 10.4.
4. There are several technical difficulties that arise in completely fulfilling
the fine-grained SIMD ideal of one processor per data element. Thus, it
is better to begin with the coarse-grained approach and therefore,
develop a more rational architecture. Refer Section 10.5.
5. The connection machine family marketed by thinking machines inc. Has
been one of the most commercially successful examples of niche
marketing in the computing field in recent years (one other which
springs to mind is the cray family). Refer section 10.5.
References
 Sima, Fountain, T. & Kacsuk, P. (1997) Advanced Computer
Architectures: A Design Space Approach.
 Hwang, K. (1993) Advanced Computer Architecture, Parallelism,
Scalablility, Programmability, Mgh.
 Flynn, M. J. (1995) Computer Architecture, Pipelined & Parallel
Processor Design - Narosa.
 Hayes, J. P. (1998) Computer Architecture & Organisation, 3rd Edition
Mcgraw Hill.
 Carter; N. P. (2002) Schaum’s Outline Of Computer Architecture; Mc.
Graw-Hill Professional
E-references:
 http://www.lc3help.com/
 http://www.scribd.com/

Manipal University of Jaipur B1648 Page No. 236


Computer Architecture Unit 11

Unit 11 Vector Architecture and MIMD Architecture


Structure:
11.1 Introduction
Objectives
11.2 Vectorisation
11.3 Pipelining
11.4 MIMD Architectural Concepts
Multiprocessor
Multi-computer
11.5 Problems of Scalable Computers
11.6 Main Design Issues of Scalable MIMD Architecture
11.7 Summary
11.8 Glossary
11.9 Terminal Questions
11.10 Answers

11.1 Introduction
In the previous unit, you were introduced to data parallel architecture in
which you studied the SIMD part. You learned about SIMD architecture and
its various aspects like SIMD design space, fine-grained SMID architecture
and coarse gained SIMD architecture. In this unit we will progress a step
further to explain the MIMD architecture. Although we have covered vector
architecture in prior unit, we will throw some light on it as well so that the
concept of MIMD can be understood in a better way.
According to famous computer architect Jim Smith, the most efficient way to
execute a vectorisable application is a vector. Vector architectures are
responsible for collecting the group of data elements distributed in memory
and after that placing them in linear sequential register files. After placing,
operation starts on that data present in register files and the result is
dispersed again to the memory. On the other hand, MIMD architectures are
of great importance and may be used in numerous application areas such
as CAD (Computer Aided Design), CAM (Computer Aided Manufacturing),
modelling, simulation etc
In this unit, we are going to study different features of Vector architecture
and MIMD architecture such as pipelining, MIMD architectural concepts,

Manipal University of Jaipur B1648 Page No. 237


Computer Architecture Unit 11

problems of scalable computers, Main design issues of scalable MIMD


architecture.
Objectives:
After studying this unit, you should be able to:
 recall the concept of vector architecture
 discuss the concept of pipelining
 describe MIMD Architectural concepts
 differentiate between multiprocessor and multicomputer
 interpret the problems of scalable computers
 solve the problems of scalable computers
 recognise the main design issues of scalable MIMD architecture

11.2 Vectorisation
Vector machines are planned & designed to operate at the level of vectors.
Now, you will study the operation of vectors. Suppose there are 2 vectors, A
and B, both having 64 components. The components present in a vector are
the vector size. So our vector size is 64. Vector A and B are shown below:

Now we want to add these 2 vectors and keep the result in another vector
C. It is shown in the equation below. The rule for adding the vector is to add
the corresponding components.

We can also perform the addition by utilizing loops as in high level


languages. This loop iterates n times; n is the size of vector. Now you will
notice how this code can be written in C-language:
For(i=0; i<n; i++),
C[i] = A[i] + B[i];

The above loop iterates n number of time and is known as for loop. This
adding of vectors is referred as scalar operation. Vector operations are
defined by vector processor instruction. Such as, only 1 vector instruction is
required to add A and B vectors. Basically, a vector instruction defines 4
fields, 3 are registers and 1 is operation.
Manipal University of Jaipur B1648 Page No. 238
Computer Architecture Unit 11

which performs

Vd = Vs1 VOP Vs2


Here, VOP is the vector operation which is performed on registers Vs1 and
Vs2 and result is stored at Vd.
Architecture
As discussed in unit 9, both the scalar and vector unit is present in a vector
machine. The scalar unit has the same structural design as the conventional
processor and it works on scalars. Similarly vectors works on vector
operations. Advancements like moving from CISC to RISC designs, and
moving from the memory–memory architecture to the vector–register
architecture has been seen in vector architecture.
In the beginning, vector machines employed the memory-memory
architecture. In memory- memory architecture, input operands are received
by all vector operations from memory and the result is stored in memory.
The 1st vector machine CDC Star 100 utilized this architecture.
The vector-register architecture is like RISC architecture and is utilized in
numerous vector machines such as Hitachi, NEC etc.
The vector register contains vectors on which vector operations are
performed. After the operations are performed then the result also gets
stored in vector register. Through RISC processor, particular load and store
instruction moves the vector among memory and register of vector.
Figure 11.1 shows the vector processor architecture which is grounded on
Cray 1 system. There are 5 major components in this architecture:
 vector register
 vector load/store unit
 vector functional units
 scalar unit
 main memory,

Manipal University of Jaipur B1648 Page No. 239


Computer Architecture Unit 11

Figure 11.1: A Typical Vector Processor Architecture (Based on Cray 1)

Vector Registers: Vector registers carries the input and result vectors. 8
vector registers are present in Cray 1 and many other vector processors.
Every vector register contains 64 elements of 64 bits each. For example
Fijitsu VP 200 processor permits the space of 8k elements present in vector
register’s programmable set whose range is 8 to 256. As 8 vector register
carries 64 elements of 64 bits, but 256 register carry 32 elements.
Figure 11.1 contains 1 write port and 2 read port so that vector operations
can overlap on various vector registers. Scalar Registers: Vector
operations get the scalar inputs present in scalar registers. Such as a
scalar register results constant when elements are multiplied to matrix.
B=5*X+Y
In the above equation, 5 is a constant stored in scalar register and X and
vectors in 2 different vector register. Address calculation of vector load/store
unit is also done in this register. Vector Load/Store Unit: Data
moves
Manipal University of Jaipur B1648 Page No.
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