Computer Architecture Unit 5

Activity 1:
Visit a library and find out the features ofR2000, R3000, R4000, R4200
and R6000. Compare them in a chart.

5.3 Pipeline Instruction Processing

An Instruction pipeline operates on a stream of instructions by overlapping
and decomposing the three phases (fetch, decode and execute) of the
instruction cycle. It has been extensively used in RISC machine and many
high-end mainframes as one of the major contributor to achieve high
performance. A typical instruction execution in pipeline architecture consists
of a sequence of following operations:
1. Fetch instruction: In this operation, the next expected instruction is
read into a buffer from cache memory.
2. Decode instruction/register fetch: The Instruction Decoder reads the
next instruction from the memory, decode it, optimize the order of
execution and further sends the instruction to the destinations.
3. Calculate operand address: Now, the effective address of each source
operand is calculated.
4. Fetch operand/memory access: Then, the memory is accessed to
fetch each operand. For a load instruction, data returns from memory
and is placed in the Load Memory Data (LMD) register. If it is a store,
then data from register is written into memory. In both cases, the
operand address as computed in the prior cycle is used.
5. Execute instruction: In this operation, the ALU perform the indicated
operation on the operands prepared in the prior cycle and store the
result in the specified destination operand location.
6. Write back operand: Finally, the result into the register file is written or
stored into the memory.
These six stages of instruction pipeline are shown in a flowchart in
figure 5.4.

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Figure 5.4: Flowchart of an Instruction Pipeline

Self Assessment Questions

3. In ________________ the result into the register file is written or stored
into the memory.
4. In Decode Instruction/Register Fetch operation, the _______________
and the _______________ are determined and the register file is
accessed to read the registers.

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Computer Architecture Unit 5

5.4 Pipelined Execution of Integer and Boolean Instructions

Now let us discuss Pipelined execution of integer and Boolean instructions
with respect to the design space.
5.4.1 The design space
In this section, first we will overview the salient aspects of pipelined
execution of FX instructions. (In this section, the abbreviation FX will be
used to denote integer and Boolean.) With reference to figure 5.5 we
emphasise two basic aspects of the design space: how FX pipelines are laid
out logically and how they are implemented.

Figure 5.5: Design Space of the Pipelined Execution of FX instructions

A logical layout of an FX pipeline consists, first, of the specification of how

many stages an FX pipeline has and what tasks are to be performed in
these stages. These issues will be discussed in Section 5.4.2 for RISC and
CISC pipelines. The other key aspect of the design space is how FX
pipelines are implemented. In this respect we note that the term FX pipeline
can be interpreted in both a broader and a narrower sense. In the broader
sense, it covers the full task of instruction fetch, decode, execute and, if
required, write back. In this case, it is usually employed for the execution of
Local Store (LS) and branch instructions and is termed a master pipeline.
By contrast, in the narrower sense, an FX pipeline is understood to deal
only with the execution and writeback phases of the processing of FX

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instructions. Then, the preceding tasks of instruction fetch, decode and, in

the case of superscalar execution, instruction issue are performed by a
separate part of the processor.
5.4.2 Logical layout of FX pipelines
Integer and Boolean instructions account for a considerable proportion of
programs. Together, they amount to 30-40% of all executed instructions.
Therefore, the layout of FX pipelines is fundamental to obtaining a high-
performance processor.
In the following topic, we discuss how FX pipelines are laid out. However,
we describe the FX pipelines for RISC and C1SC processors separately,
since each type has a slightly different scope. While processing operates
instructions, RISC pipelines have to cope only with register operands. By
contrast, CISC pipelines must be able to deal with both register and memory
operands as well as destinations.
Pipeline in RISC architecture: Before discussing pipelines in RISC
machines, let us first discuss what is a RISC machine? The term RISC
stands for Reduced Instruction Set Computing. RISC computers reduce
chip complexity by using simpler instructions. As a result, RISC compilers
have to generate software routines to perform complex instructions that
would have been done in hardware by CISC (Complex Instruction Set
Computing) computers. The salient features of RISC architecture are as
follows:
 RISC architecture has instructions of uniform length.
 Instruction sets are streamlined to carry efficient and important
instructions.
 Memory addressing method is simplified. The complex references are
split up into various reduced instructions.
 The numbers of registers are increased. RISC processors can have
minimum 16 and maximum 64 registers. These registers get hold of
variables that are frequently used.
Pipelining is a standard feature in RISC processors. A typical RISC
processor pipeline operates in the following steps:
1. Fetch instructions from the memory
2. Read the registers and then decode instruction
3. Either execute instruction or compute the address
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4. Access the operand stored at that memory location

5. Write the calculated result into the register
RISC instructions are simpler as compared to the instructions used in CISC
processors. It is due to the pipelining feature used there. CISC instructions
are of variable length, while RISC instructions are of same length. RISC
instructions can be fetched in a single operation. Theoretically, one clock
cycle should be taken by each stage in RISC processor so that the
processor completes execution of one instruction in one clock cycle. But
practically, RISC processors take more than one cycle for one instruction.
The processor may sometimes stall due to branch instructions and data
dependencies. Data dependency takes place if an instruction waits for the
output of previous instruction. Delay can also be due to the reason that
instruction is waiting for some data which is not currently available in the
register. So, the processor cannot finish an instruction in one clock cycle.
Branch instructions are those that tell the processor to make a decision
about what the next instruction to be executed. They are generally based on
the results of another instruction. So, they can also create problems in a
pipeline if a branch is conditional on the results of an instruction, which has
not yet finished its path through the pipeline. In that case also, the processor
takes more than one clock cycle to finish one instruction.
Pipeline in CISC architecture: CISC is an acronym for Complex Instruction
Set Computer. The CISC machines are easy to program and make efficient
use of memory. Since the earliest machines were programmed in assembly
language and memory was slow and expensive, the CISC philosophy was
commonly implemented in large computers such as PDP-11. Most common
microprocessor designs such as the Intel 80x86 and Motorola 68K series
have followed the CISC philosophy. The CISC instructions sets have the
following main features:
 Two-operand format; here instructions have both source & destination.
 Register to register, memory to register and register to memory
commands.
 Multiple addressing modes for memory, having specialised modes for
indexing through arrays
 Depending upon the addressing mode, the instruction length varies
 Multiple clock cycles required by instructions to execute.

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