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CA Classes-86-90

The document discusses techniques to handle hazards in computer architecture pipelines. It describes data hazards that occur when instructions depend on results that are not ready yet, and control hazards that happen with branches when the instruction path is uncertain. The key technique discussed is forwarding, where results are passed directly from one part of the pipeline to another to avoid stalls.

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17 views5 pages

CA Classes-86-90

The document discusses techniques to handle hazards in computer architecture pipelines. It describes data hazards that occur when instructions depend on results that are not ready yet, and control hazards that happen with branches when the instruction path is uncertain. The key technique discussed is forwarding, where results are passed directly from one part of the pipeline to another to avoid stalls.

Uploaded by

SrinivasaRao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture Unit 4

back (WB) pipe stage, but the value is read by the SUB instruction during
the instruction decode (ID) stage (ID sub). This problem is referred to as the
data hazard because a wrong value is read by the sub instruction and an
attempt is made to use it.
The WB stage of ADD will get complete when an interrupt occurs between
the ADD and SUB instructions, and the value of R1 at that point will be the
outcome of the ADD.
As we can see in figure 4.4 and 4.5, AND instruction is also effected by data
hazard, the write of R1 does not finish till the end of clock cycle 5.
Therefore, AND instruction when executed at cycle 4 will not retrieve the
correct results.

Figure 4.4: Pipelined Execution of the Instruction

The SUB instruction reads the wrong value as it reads the data (cycle 3)
before the ADD instruction writes the value (cycle 5). The register read of
XOR instruction occurs in clock cycle 6. This is performed correctly as it is
done after the register write by ADD. The OR instruction can function
without any problem. To attain this, the register files reads are performed in
the second half of the cycle and writes in the first half. In cycle 5, the first of
the cycle performs the write to register file by ADD and the second half of
the cycle will perform the read of registers by OR.

Manipal University Jaipur B1648 Page No. 86


Computer Architecture Unit 4

Figure 4.5: Clock Cycles and Execution Order of Instructions

Self Assessment Questions


12. Pipelining has a major effect on changing the relative timing of
instructions by overlapping their execution. (True/False)
13. The register read of XOR instruction occurs in clock cycle
________________ .

4.6 Control Hazards


Control Hazards cause a greater performance failure for a pipeline as
compared to data hazards. On execution of a branch, the PC may or may
not change from 4 added to its current value. If the PC is changed by the
branch to its target address, then it is known as taken branch; else it is
known as not taken or untaken. Control hazards are also known as
Branching hazard and occur with branches. In this case, the processor will

Manipal University Jaipur B1648 Page No. 87


Computer Architecture Unit 4

not know the outcome of the branch when it needs to insert a new
instruction into the pipeline stage).
As soon as the branch is detected, the method used to deal with branches
is to stall the pipeline. Until the instruction is confirmed to be a branch, there
is no need to stall the pipeline. Thus, the stall does not occur until after the
ID stage. The pipelining behaviour looks as in figure 4.6.

Figure 4.6: Three-Cycle Stall in the Pipeline

The control hazard stall is not implemented in the same way as the data
hazard stall, since the instruction fetch (IF) cycle is to be repeated as soon
the branch cycle is known. Thus, the first IF cycle is definitely a stall, as it
never performs essential tasks. By setting the ID/IF to zero, we can
implement the stall for the three cycles. The repetition of the IF stage is not
required, if the branch is untaken, since the correct instruction may already
have been fetched.
Self Assessment Questions
14. __________ cause a greater performance failure for a pipeline than
_____________________.
15. If the PC is changed by the branch to its target address, then it is
known as ______________ branch; else it is known as ___________.

4.7 Techniques to Handle Hazards


In this section, we will discuss the techniques to handle data and control
hazards. Now, let us start with the concept of forwarding technique to
handle data hazard.

B1648 Page No. 88


Computer Architecture Unit 4

4.7.1 Minimising data hazard stalls by forwarding


The problem posed due to data hazards can be solved with a simple
hardware technique called forwarding (also called bypassing and
sometimes short-circuiting). This is a technique to handle data hazards. The
key insight in forwarding is that the result is not really needed by the SUB
instruction until after the ADD actually produces it. The only problem is to
make it available for SUB when it needs it. If the result can be moved from
where the ADD produces it (execute/memory access (EX/MEM) register), to
where it is required by the SUB (ALU input latch), then a stall requirement
can be ignored.
Using this study, the mechanism of forwarding is as follows:
1. The ALU result from the EX/MEM register is reversed backside to the
ALU input latches.
2. If it is detected by the forwarding hardware that the register
corresponding to a source for the current ALU operation is written by the
previous ALU operation, the forwarded result is selected as the ALU
input by the control logic rather than the register file reading the value.
If the SUB instruction is stalled, with forwarding, the ADD instruction will be
completed and the bypass is not made active. This is also true for the case
of a disruption between the two instructions.
Figure 4.5 shows that the results of not only the immediate previous
instruction are forwarded but also from an instruction initiated two cycles
earlier. The bypass paths and the highlights of the timing of the register
reads and writes are shown in figure 4.7. We can execute this code
sequence without stalls.

Manipal University Jaipur B1648 Page No. 89


Computer Architecture Unit 4

Figure 4.7: Example with the Bypass Paths in Place

We can generalise forwarding to take account of passing a result directly to


the functional unit that needs it. The output of one unit passes its result to
the input of another, rather than forwarding the result of a unit to the input of
the same unit. For example, let’s consider the following sequence:
By forwarding the result of R1 and R4 from the pipeline registers to the ALU
and data memory inputs, we can prevent a stall.
Store requires an operand during MEM, and forwarding of that operand is
shown in the given figure 4.8(a)

Manipal University Jaipur B1648 Page No. 90

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