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CA Classes-81-85

The document discusses computer architecture and pipelining. It describes an example pipeline with four segments and registers. It explains how the pipeline processes data over multiple clock cycles, overlapping operations to improve performance. It also discusses different types of pipelines and hazards that can occur in pipelines like structural hazards and data hazards.

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34 views5 pages

CA Classes-81-85

The document discusses computer architecture and pipelining. It describes an example pipeline with four segments and registers. It explains how the pipeline processes data over multiple clock cycles, overlapping operations to improve performance. It also discusses different types of pipelines and hazards that can occur in pipelines like structural hazards and data hazards.

Uploaded by

SrinivasaRao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture Unit 4

Now we will study an example of pipeline in figure 4.2.

An * Bn + Cn * Dn n = 1, 2, 3, . . . . . .

An Bn Cn Dn

R1 R2 R3 R4

Multiplier Multiplier

R5 R6

Adder

R7

Figure 4.2: Example of Pipeline Processing

In the figure, each segment has one or three registers with combinational
circuits. Each register is loaded with a new data on start of new time
segment. Refer table 4.2 for an example of contents of Registers in
Pipeline.
On 1st clock pulse, data is loaded in registers R1, R2, R3, and R4.
On 2nd clock pulse, product is stored in registers R5 and R6.
On 3rd clock pulse, the data in R5, R6 are added and stored in R7.
So it required a total of 3 clock periods only, to compute An* Bn + Cn* Dn.

Manipal University Jaipur B1648 Page No. 81


Computer Architecture Unit 4

Table 4.2: Contents of Registers in Pipeline Example

Clock Segment 1 Segment 2 Segment 3 Segment 4


Pulse R1 R2 R3 R4 R5 R6 R7

1 A1 B1 C1 D1 - -

2 A2 B2 C2 D2 A1*B1 C1*D1

3 A3 B3 C3 D3 A2*B2 C2*D2 A1*B1+C1*D1

4 - - - - A3*B3 C3*D3 A2*B2+C2*D2

5 - - - - - - A3*B3+C3*D3

An instruction pipeline functions on a flow of instructions by overlapping the


fetch decade and executes phases of the instruction cycle. High speed
computers usually consist of pipeline arithmetic units. The execution of
floating point operations, multiplication of fixed point numbers and similar
computations encountered in scientific problems are done through these
pipeline arithmetic units.
A pipeline multiplier is essentially an array multiplier with special address
designed to minimise the carry propagation time through the partial
products. Floating point operations are easily decomposed into sub
operations.
During the time when the previous instructions are being performed in other
sections, an instruction pipeline reads successive instructions from the
memory. Due to this, the instruction and execute phases have common
characteristics and perform synchronised operations. One possible
digression associated with such a scheme is that an instruction may cause
a branch other than the sequence. In that case, all the instructions that have
been read from memory after the branch instruction must be discarded and
the pipeline must be emptied.

Manipal University Jaipur B1648 Page No. 82


Computer Architecture Unit 4

The instruction fetch section can be applied by means of a first-in first-out


(FIFO) buffer. This forms a queue rather than a stack.
The instruction pipeline design will be most competent if the instruction
cycle is divided into segments of equal interval. The time taken by each step
to accomplish its job depends on the instruction and the manner in which it
is executed.
Self Assessment Questions
1. An implementation technique by which the execution of multiple
instructions can be overlapped is called _________.
2. Pipelining is also called _______________.
3. LMD is the short for ___________________.
4. The instruction fetch segment can be implemented by means of a
__________________.

4.3 Types of Pipelining


Pipelines are of two types - Linear and Non-linear.
a) Linear pipelines: These pipelines perform only one pre-defined fixed
functions at specific times in a forward direction from one stage to next
stage. A linear pipeline can be visualised as a collection of processing
segments, where each segment completes a part of an instruction. The
result obtained from the processing in each segment is transferred to
the next segment in the pipeline. As in these pipelines, repeated
evaluations of the same function are performed with different data for
some specified period of time, these pipelines are also called static
pipelines.
b) Non-linear pipelines: These pipelines can perform more than one
operation at a time as they have the provision to be reconfigured to
execute variable functions at different times. As these pipelines can
execute different functions at different times, they are called dynamic
pipelines.
An example of a non-linear pipeline is a three-stage pipeline that
performs subtraction and multiplication on different data at the same
time as illustrated in figure 4.3.

Manipal University Jaipur B1648 Page No. 83


Computer Architecture Unit 4

Latch Processing Latch Processing


Latch Processing
Unit unit unit
Input
First Stage Second Stage
Third Stage
Figure 4.3: An Example of a Non-Linear Pipeline

In this three-stage pipeline, the input data must go through stages 1, 2 and
3 to perform multiplication and through stages 1 and 3 only to perform
subtraction. Therefore, dynamic pipelines require feed forward and
feedback connections in addition to the streamline connections between the
stages.
Self Assessment Questions
5. ____________ pipelines perform only one pre-defined fixed functions
at specific times in a forward direction from one stage to next stage.
6. ________________ pipelines can perform more than one operation at
a time as they have the provision to be reconfigured to execute
variable functions at different times.
7. Non-Linear pipelines are also called ____________________ .

4.4 Pipelining Hazards


Hazards are the situations that stop the next instruction in the instruction
stream from being executed during its designated clock cycle. Hazards
reduce the performance from the ideal speedup gained by pipelining. In
general, there are three major categories of hazards that can affect normal
operation of a pipeline.
1. Structural hazards (also called resource conflicts): They occur from
resource conflicts when the hardware cannot support all possible
combinations of instructions in simultaneous overlapped execution.
These are caused by multiple accesses to memory performed by
segments. In most cases this problem can be resolved by using
separate instruction and data memories.
Manipal University Jaipur B1648 Page No. 84
Computer Architecture Unit 4

2. Data hazards (also called data dependency): They occur when an


instruction depends on the result of a previous instruction in a way that
is exposed by the overlapping of instructions in the pipeline. This
happens arise when an instruction requires the previous output and
output is not yet present. This is explained in detail in the section 4.5.
3. Control hazards (also called branch difficulties): Branch difficulties arise
from branch and other instructions that change the content of PC
(Program Counter). This is explained in detail in the section 4.6.
Stalling can become essential due to the hazards present in the pipelines.
The processor can stall on different events:
 A cache miss: Before and after the instruction ends up in a miss, a
cache miss stalls all the instructions on pipeline.
 A hazard in pipeline: When a hazard is removed, it allows some
instructions in the pipeline to proceed whereas some others are
delayed. Once an instruction is stalled, all the instructions following this
instruction are stalled. Instructions in the line preceding the stalled
instruction must keep going, or else the hazard will never clear.
Self Assessment Questions
8. _______________ are the situations that stop the next instruction in
the instruction stream from being executed during its designated clock
cycle.
9. Structural Hazards are also called ________________ .
10. Data Hazards are also called ____________________ .
11. Control Hazards are also called _______________.

4.5 Data Hazards


Pipelining has a major effect on changing the relative timing of instructions
by executing them at the same time. This leads to data and control hazards.
In pipelining, the data hazards arise when the sequence of read/write
accesses to operands thus, altering the sequence of the sequential
execution in an unpipelined machine. In simple terms, data hazard occurs
when attempted to use the data before it is ready. The pipelined execution
of such instructions is given below:
The instructions following the ADD make use of the end result of the ADD
instruction (in R1). The ADD instruction writes the value of R1 in the write

Manipal University Jaipur B1648 Page No. 85

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