484 Tutorial Problems

12 Integrated gate circuit Integrated Logic

Circuits
Part 1
Self-test

12.1 Which of the following is not a TTL circuit?

(a) 74F00 (b) 74AS00 (c) 74HC00 (d) 74ALS00

12.2 If two unused inputs of a LS TTL gate are connected to an input being driven by
another LS TTL gate, the total number of remaining unit loads that can be
driven by this gate is
(a) seven (b) eight (c) eighteen (d) unlimited

12.3 In a TTL circuit, if an excessive number of load gate inputs are connected,
(a) UOH(min) drops below UOH
(b) UOH drops below UOH(min)
(c) UOH exceeds UOH(min)
(d) UOH and UOH(min) are unaffected

12.4 An open-collector output requires ______________.

(a) a pull-down resistor
(b) a pull-up resistor
(c) no output resistor
(d) an output resistor

12.5 When the frequency of the input signal to a CMOS gate is increased, the average
power dissipation ______________.
(a) increases
(b) decreases
(c) does not change
(c) decreases exponentially

12.6 CMOS operates more reliably than TTL in a high-noise environment because of
its ______________.
(a) lower noise margin
(b) input capacitance
(c) higher noise margin
(d) smaller power dissipation

12.7 Which factor does not affect CMOS loading?

(a) Charging time associated with the output resistance of the driving gate
(b) Discharging time associated with the output resistance of the driving gate
(c) Output capacitance of the load gates
(d) Input capacitance of the load gates

12.8 Proper handling of a CMOS device is necessary because of ______________.

(a) fragile construction
(b) high noise margin

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 Problems 485

(c) susceptibility to electrostatic discharge

(d) low power dissipation

12.9 It is best not to leave unused TTL inputs unconnected (open) because of
TTL’s ______________.
(a) noise sensitivity
(b) low-current requirement
(c) open-collector outputs
(d) tristate construction

12.10 One output structure of a TTL gate is often referred to as a ______________.

(a) totem-pole arrangement
(b) diode arrangement
(c) JBT arrangement
(d) base, emitter, collector arrangement

12.11 A certain gate draws 1.8 µA when its output is HIGH and 3.3 µA when its output
is LOW. VCC is 5 V and the gate is operated on a 50% duty cycle. What is the
average power dissipation (PD)?
(a) 2.55 µW (b) 1.27 µW (c) 12.75 µW (d) 5 µW

12.12 If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static
(noncharging) HIGH output state, the power dissipation (PD) of the gate is
(a) 5.5 mW (b) 5.5 W (c) 5 mW (d) 1.1 mW

Part 2
Problems
12.1 A certain logic gate has a UOH(min) = 2.2 V, and it is driving a gate with a UIH(min)
= 2.5 V. Are these gates compatible for HIGH-state operation? Why?

12.2 A certain logic gate has a UOL(max) =0.45 V, and it is driving a gate with UIL(max) =
0.8 V. Are these gates compatible for LOW-state operation? Why?

12.3 Voltage specifications for three types of logic gates are given in the following
table. Which gates would you select for use in a high-noise industrial
environment?

UOH(min) UOL(max) UIH(min) UIL(max)

Gate A . V . V . V . V

Gate B . V . V V . V
Gate C . V . V . V . V

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486 12 Integrated gate circuit

12.4 A certain gate draws 1.8 µA when its output is HIGH and 3.3 µA when its output
is LOW. VCC is 5 V and the gate operates on a 50% duty cycle. What is the
average power dissipation (PD)?

12.5 Parameters for three types of gates are listed in the following table. Considering
the speed-power product, which one would you select for best performance? If
you wanted the gate to operate at the highest possible frequency, which gate
would you select?

tPLH tPHL PD

Gate A  ns . ns . mW

Gate B  ns  ns  mW
Gate C  ns  ns . mW

12.6 For a given circuit with five NAND gates in Figure P12.1, if the propagation of
gates G1, G2，G3 and G4 is 30 ns and the frequency of output F is 3.2 MHz,
determine the average propagation delay time, tpd5, of gate G5.

G1 G2 G3 G4 G5 F

Figure P12.1

12.7 Write the logic expression for each circuit in Figure P12.2.

CMOS TTL CMOS

A A
A B F2 B F3
F1

100kΩ 51Ω
10kΩ

(a) (b) (c)

TTL CMOS TTL

A A
B F4 B F5 A
F6
100kΩ 10kΩ B

100kΩ

(d) (e) (f)

Figure P12.2

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 Problems 487

12.8 Which TTL circuits in Figure P12.3 can implement NOT operation?

1 A
A A A
5V A
100Ω
1M
(a) (b) (c) (d) (e)

Figure P12.3

12.9 Which CMOS circuits in Figure P12.4 can implement NOT operation?

A A
A A B TG
VDD
1MΩ

(a) (b) (c) (d)

Figure P12.4

12.10 For each part of the circuits in Figure P12.5, determine whether each part can
implement the required logic expression. If not, indicate the change that
should be made to implement the required logic. All gates are standard TTL.

A
B F= AB+ CD
A
B F=A B C
C
C
D
(a) (b)

B
F= A X+B X
A X
B F=AB 100kΩ
1
A

(c) (d)

Figure P12.5

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488 12 Integrated gate circuit

12.11 The input waveforms are applied to the inputs of the TTL tristate circuits, as
shown in Figure P12.6. Show the output waveform in proper relation to the
inputs with timing diagram.

A
B A
C
F
B

(a) (b)

Figure P12.6

12.12 For a CMOS circuit in Figure P12.7 (a), the input waveforms in Figure P12.7 (b)
are applied to inputs A, B and C, and R = 10 kΩ. Show the output waveform in
proper relation to the inputs with timing diagram.

A
F A
B

B C

C R

(b)
(a)

Figure P12.7

12.13 Figure P12.8 (a) shows a circuit consisting of two transfer gates and an inverter.
uI1 = 10 V and uI2 = 5 V. If the input waveform in Figure P12.8 (b) is applied to the
input C, draw out the waveform of the output uO in proper relation to the inputs
with a timing diagram.

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 Problems 489

10V
uI1 uo
TG
O t
uO
uI2
TG

C
O t
(a) (b)

Figure P12.8

12.14 Write the logic expression of each part of logic circuit in Figure P12.9.

A A
F
C F
1
B B

(a) (b)

Figure P12.9

12.15 Write the logic expression for each of TTL circuits in Figure P12.10 (a) and (b). If
the input waveforms in Figure P12.10 (c) are applied to inputs A, B, and C, show
the output waveforms in proper relation to the inputs with a timing diagram.

A A A
F B
F B
B
C C C

(a) (b) (c)

Figure P12.10

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490 12 Integrated gate circuit

12.16 For a circuit in Figure P12.11 (a) to (g), input waveforms in figure (h) are applied
to input A and B. Determine the corresponding output waveforms in proper
relation to inputs with timing diagram.

TTL TTL CMOS CMOS

A A A A
B F1 B F2 B F3 B F4

100Ω 100KΩ 10Ω 100KΩ

(a) (b) (c) (d)

+5V
CMOS
A
F5 A
A F6
B
100 KΩ B

(e) (f) (g)

Figure P12.11

12.17 Write the logic expression for each of CMOS circuits in Figure P12.12, and
explain what the similarities are and what the difference is between the
two circuits.

VDD VDD

EN

A F1

F1
A

EN

(a) (b)

Figure P12.12

12.18 Design a CMOS circuit for implementing the logic expression as follows:

F = AB + C

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 Problems 491

12.19 In viewpoint of voltage level match, explain the function of RP for the TTL/
CMOS interface in Figure P12.13.

+5V

RP

uO
uI
TTL CMOS

Figure P12.13

12.20 Explain the reason why two CMOS inverters are in parallel in Figure P12.14.

VDD=VCC

uI uo
CMOS CMOS TTL

Figure P12.14

12.21 Determine which driving circuits in Figure P12.15 is wrong. Indicate the change
that should be made to get the correct driving circuit.

VCC
A A
B B
C
A D
B

(a) (b) (c)

Figure P12.15

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