0.

Preface

Gisselquist Daniel E. Gisselquist, Ph.D.

Technology, LLC
 Lesson Overview
Ź Lesson Overview Objectives
V–
Verilog subset ˝ Understand the Course philosophy
Style
Co-sim
˝ Check the Pre-requisites
Formal ˝ Getting Started
Debugging
Which board?
Minimum Board
Clear your desk, it’s time to get started!
Clear your desk
Test your board
Conclusion

2 / 13
 V–
Lesson Overview Verilog is a large language
Ź V–
Verilog subset ˝ Only some verilog is necessary for design
Style
Co-sim – Simulation verilog gets confused with synthesizable verilog
Formal
Debugging – Programmers turn Verilog into a programming language.
Which board?
Minimum Board
It’s not
Clear your desk – Verilog testbench language is inadequate for bug finding
Test your board
Conclusion
when compared with formal methods
We’ll be using SymbiYosys for formal verification
– Verilog testbenches are a poor substitute for a good
simulation language, such as C++
We’ll be using verilator and C++ for simulation

A better solution is needed!

3 / 13
 V–
Lesson Overview Verilog is a large language
V–
Ź Verilog subset ˝ Only some verilog is necessary for design
Style
Co-sim
˝ We’ll use synthesizable code only
Formal
Debugging – No A <= #10 B; statements
Which board?
Minimum Board
– No @posedge statements
Clear your desk – No $display, $monitor, or $final statements, etc.
Test your board
Conclusion
– No ’x values
– Only toplevel ports can be inouts
– We’ll use restricted forms for multiply and memory
– Avoid teaching loops as long as possible
– We will use initial statements
initial statements are appropriate for FPGA’s

4 / 13
 V–
Lesson Overview Verilog is a large language
V–
Verilog subset ˝ Only some verilog is necessary for design
Ź Style
˝ We’ll use synthesizable code only
Co-sim
Formal ˝ Safe style guide
Debugging
Which board?
Minimum Board
– One clock (initially)
Clear your desk – No logic generated clocks
Test your board
Conclusion
– We’ll use initial statements
– Reset values must match initial values

5 / 13
 V–
Lesson Overview Verilog is a large language
V–
Verilog subset ˝ Only some verilog is necessary for design
Style
Ź Co-sim
˝ We’ll use synthesizable code only
Formal ˝ Safe style guide
Debugging
Which board? ˝ Co-simulation is a must
Minimum Board
Clear your desk – External hardware peripheral simulations will be built in
Test your board
Conclusion
C++
– Goal is to create a design that looks, acts, and works as
though it were on the FPGA

6 / 13
 V–
Lesson Overview Verilog is a large language
V–
Verilog subset ˝ Only some verilog is necessary for design
Style
Co-sim
˝ We’ll use synthesizable code only
Ź Formal ˝ Safe style guide
Debugging
Which board? ˝ Co-simulation is a must
Minimum Board
Clear your desk
˝ Formal verification is great for bench testing
Test your board
Conclusion
– We’ll scratch the surface here

7 / 13
 V–
Lesson Overview Verilog is a large language
V–
Verilog subset ˝ Only some verilog is necessary for design
Style
Co-sim
˝ We’ll use synthesizable code only
Formal ˝ Safe style guide
Ź Debugging
Which board? ˝ Co-simulation is a must
Minimum Board
Clear your desk
˝ Formal verification is great for bench testing
Test your board ˝ Verilog instruction must include
Conclusion
– Formal methods, and
– Simulation
. . . from the beginning!

8 / 13
 Which board?
Lesson Overview This course is intended to be board-agnostic
V–
Verilog subset ˝ We’ll cover the basics and the mechanics
Style
Co-sim
˝ We’ll use Verilator extensively
Formal ˝ You don’t need a board to take this course
Debugging
Ź Which board? ˝ You may enjoy the course more with a board
Minimum Board
Clear your desk
˝ “Board bonus chapter appendices” may eventually
Test your board accompany the course
Conclusion

9 / 13
 Minimum Board
Lesson Overview Course designs depend upon a minimum capability
V–
Verilog subset ˝ One button/switch, one LED
Style
Co-sim – Many exercises use multiple LEDs
Formal
Debugging – While not necessary, if you want to build these in
Which board?
Ź Minimum Board
hardware you’ll need more than one LED on your board
Clear your desk
Test your board
˝ Serial port, both transmit/receive
Conclusion

10 / 13
 Clear your desk
Lesson Overview If you have an FPGA board, then
V–
Verilog subset ˝ Find and download the schematic, . . .
Style
Co-sim
˝ The data sheets for all of the components, . . .
Formal ˝ The board vendor’s master constraint file, and
Debugging
Which board? ˝ The board vendor’s demo code
Minimum Board
Ź Clear your desk Put these files in a project reference directory
Test your board
Conclusion
Do this before any project with a new FPGA board!

11 / 13
 Test your board
Lesson Overview Your board vendor should provide you with
V–
Verilog subset ˝ A demonstration design, and
Style
Co-sim
˝ The instructions necessary to build and load it
Formal
Debugging This design should verify that your hardware works
Which board?
Minimum Board
If you will be using hardware for this course, please verify that
Clear your desk your hardware passes this test first
Ź Test your board
Conclusion

12 / 13
 Conclusion
Lesson Overview ˝ Digital design can be hard, let’s not make it harder
V–
˝ Teach debugging tools with the language
Verilog subset
Style ˝ Are you ready to learn?
Co-sim
Formal
Debugging
Which board?
Minimum Board
Clear your desk
Test your board
Ź Conclusion

13 / 13