Third International Conference on Devices, Circuits and Systems (ICDCS'16) 295

DESIGN OF STATIC RANDOM ACCESS

MEMORY USING QCA TECHNOLOGY
D. Gracia Nirmala Rani1,M. Saranya2,T. Sivashankari3,N.Meenakshi4,R.Meena5, S.Rajaram6
Department of Electronics and Communication Engineering,
Thiagarajar College of Engineering, Madurai-625 015.

Abstract-Quantum dot Cellular Automata(QCA) is one of the cannot tunnel between two cells. Fig.1(a) shows a standard
emerging trends in the field of nanotechnology which helps to QCA cell with four dots at the corners. The polarization
overcome the limitations of CMOS technology. QCA can be used
to design memory circuits. Static Random Access Memory represents logic states that binary logic 0 and binary logic 1. If
( SRAM ) is one of the attractive application of QCA technology. the two electrons align in the lower left and upper right dots, it
The proposed design and simulation of memory cell based on represents logic ‘1’ state (fig.1(b)). If the two electrons align in
QCA with minimum area and complexity. This paper presents the the upper left and lower right dots, it represents logic ‘0’ state
design and simulation of 16-bit×32-bit SRAM in QCA with (fig.1(c)).
minimum number of majority gates and it will be simulated using
QCADesigner Tool. SRAM based QCA performance have been
compared with CMOS technology using Cadence tool. The
comparison results shows that the QCA SRAM circuit provides
high efficiency in terms of area, complexity and power
consumption.
I. INTRODUCTION
Feature size in CMOS has decreased after several decades;
however, some limitations still exit. This has caused the rapid
development of molecular plans on the nanoscale. QCA is one (a) (b) (c)
of the nanotechnology has been recently recognised and it is Figure 1. (a) QCA cell representation (b) Cell polarization = +1 (Logic ‘1’)
expected to achieve low area and power consumption and high (c) Cell Polarization = -1 (Logic ‘0’).
switching speed. QCA has no voltage source and the position A. Clocking in QCA
of electrons determines the logical values [2]. Static random A single QCA wire and the state of the array of cells of the
access memory (SRAM) represents an attractive application of same wire in different clock zone are shown. The four clock
the QCA technology. Its structure is veru suitable to fabrication zones of QCA are indicated as Clock 1: Green, Clock 2: 15
at the nanoscale [3]. [4] implemented memory as parallel Pink, Clock 3: Blue and Clock 4: White.The four clock phases
read/serial write. The design network width is 1 bit and it is not of QCA are: 1) switch; 2) hold; 3) release; and 4) relax. In the
possible to save multiple bit data as a data packet[3]. switch phase of the clock, the QCA cells are initially
The main objective of this paper is a practical compact unpolarized and their potential barriers are low. During the
memory cell in QCA. The area and delay of the QCA-based switch phase, the QCA cells polarize and barriers become high;
SRAM cell presented in this paper was compared with the in this phase computation occurs. During the hold phase,
SRAM cell based on CMOS and our Proposed structure of 16- barriers are held high. In the release phase, barriers become
to-1 mux used in the design of SRAM cell has efficiency in low and the QCA cells are unpolarized. In the relax phase,
terms of area and complexity when compared to [1].The results barriers remain low and the QCA cells remain unpolarized.
show that the proposed SRAM cell performs with a minimum Fig.2 shows the QCA clocking phase
consumed area.
The remainder of this paper is organized as follows. Section
II is a review of basic QCA elements , including quantum cells,
QCA clocking, inverter, majority gate. Then section III deals
the proposed design of QCA-based SRAM circuit. Section IV
provides the simulation results and discussion. Finally the
conclusion are in section V.
II. REVIEW OF QCA CELL
QCA cell is a square shape with four Quantum dots
positioned at its corners. There are two electrons in each cell
that can tunnel between two quantum dots in a cell, but they Figure 2. QCA clocking phase.

978-1-5090-2309-7/16/$31.00©2016 IEEE
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 296

B. Inverter consists of 1874 cells covering an area of 2.94 μm². Fig.5

A standard design of the QCA inverter in which the input is shows the implementation of 4-to-16 decoder in QCA.
given at one of the ends and the inverted output is obtained at
other end. The input wire splits into two parallel wires and
because of coloumbic attraction it polarizes the cell placed at
the end of these wires on right hand side to the opposite
polarization.
C. Majority Gate
A basic element of QCA circuit is Majority gate; as majority
logic can be used for implementing any logical function
instead of employing Boolean logical operators. A two input
AND function can be implemented by a three input majority
gate by fixing one of its inputs as logic zero whereas if one Figure 4. Block diagram of 4-to-16 decoder.
input of a majority gate set to logical one it acts like a two
input OR function. The basic QCA logic element is a majority
gate as shown in fig.3. It produces an output of one if the
majority of the inputs are one.

Figure 3. QCA majority gate.

III. IMPLEMENTATION OF 16-BIT×32-BIT SRAM ELEMENTS IN
QCA
This section presents the proposed structure of 16-bit×32-bit
SRAM and depicts their block diagram. The design of 16-
bit×32-bit SRAM requires 4 to 16 decoder and 16-to-1
multiplexer. Our proposed structure of 16-to-1 mux which is
necessary for designing the 16-bit×32-bit SRAM.It requires
fifteen 2-to-1 multiplexer and it is efficient in terms number of
cells and area when compared to 16-to-1 mux in [1]. First 4-to-
16 decoder is designed in QCA. Then the 16-to-1 mux using 2-
to-1 mux is designed and 1 bit memory cell is designed to
obtain the structure of 16-bit×32-bit SRAM. The result of QCA Figure 5. Design of 4-to-16 decoder in QCA.
designer tool is compared with cadence tool(which is based on B. 16-to-1 Multiplexer in QCA
the CMOS technology) in terms of area, cells and gates used in The Multiplexer is defined as “data selectors” because they
QCA technology The 180nm and 45 nm technology are used select one of several inputs to be logically connected to the
in Cadence tool for comparision. This paper had two main output. Here, we proposed a design of 16-to-1
objectives: 1) reduced consumed area 2)achieving minimum multiplexer(MUX) using 2-to-1 multiplxer which is necessary
complexity. to design 16-bit×32-bit SRAM.They can also be used
A. 4-to-16 Decoder in QCA to implement Boolean functions. The 16-to-1 MUX is
The 4-to-16 decoder in the first stage uses eight two-input composed of 24 three-input majority gates to implement two-
AND gates. The inputs of the AND gates are connected to input AND and OR gates and twelve three-input majority gates
input wires A, B, C, and D. The 4-to-16 decoder in the second to implement the two-input AND and OR gates and nine three-
stage uses eight two-input AND gates to enable or disable the input majority gates to implement the two-input AND and OR
output. The 16 outputs are generated by a 4 × 4 two-input gates in the first, second ,third and fourth stages respectively.
AND gate network. When EN input is inactive (EN = 0), all The inputs are I0…..I16, and the selection lines are S0, S1, S2,
output is passive and when EN is active (EN = 1), the outputs and S3. The structure of 16-to-1 mux consists of fifteen 2-to-1
appear in relation to inputs A, B, C, and D. The general block mux as shown in fig. 6. Fig. 7 shows the implementation of 16-
diagram is shown in fig.4.The proposed 4-to-16 decoder to-1 mux using 2-to-1 mux in QCA.
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 297

Figure 9. Simulated circuit of 1-bit memory cell in QCA.

D. 16-bit × 32-bit SRAM in QCA

In this memory cells are located in the 16-bit × 32-bit arrays,
as shown in fig. 10. As shown, the 4-to-16 decoder addresses
the 16 SRAM lanes which has four addressing lines that can
Figure 6. Design of 16-to-1 multiplexer. address up to 16 SRAM lanes. After selecting the desired
SRAM lane, in accordance with the R/W line, 32 bits of data
can be written or read. The read or write operation from one
32-bit SRAM lane is applied in accordance with the path
delays and occurs at the same clock. Data from the SRAM
lanes are transferred to the output by a 16-to-1 MUX in read
mode. The four lines of the addressing decoder are connected
to four switch lines of the MUX jointly and the output line of
the MUX is selected by the addressing decoder.
The decoders activate only one lane of SRAM with high
confidence. When read is enabled, the data stored in the 32-cell
memory are transferred by the 16-to-1 MUX to the output of
the SRAM. The R/W input determines the read or write mode
of the SRAM. An EN input connects to enable the decoder.
Decoders select each unit of memory cell having minimum
delay.
The logical activity of the circuit is as follows. When the
SRAM is selected by the enable input of a decoder (EN), if one
SRAM lane is selected by four addressing decoder lines
simultaneously, then it will be selected for R/W mode.
Otherwise, SRAM will remain inactive. When one memory
Figure 7. Design of 16-to-1 Multilplexer using QCA.
lane is selected, if the R/W line is in a high state, writing
C. Memory Cell in QCA occurs. Note that the R/W line and input data bus must reach
SRAM continues to be a fundamental and important their respective memory lane during one clock phase, because
memory technology. Fig. 8 shows the architecture of memory the memory ready to write the input data is inserted at the same
cell. In the memory cell when EN = 1, output is enabled and time. This is the pipeline feature of QCA. If the R/W line is
when EN = 0, output = 0. When R/W = 1, the write state is low, the data saved in the memory lane will be sent to the
enabled and the D value is saved in the memory loop. When output by the 16-to-1 MUX.
R/W = 0, the read state is enabled and the saved bit is placed on
the output.

Figure 8. Basic Memory cell. Figure 10. 16-bit × 32-bit SRAM layer schematic.
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 298

Figure 12. Simulation result of the memory cell.

Figure 11. Design of 16-bit×32-bit SRAM in QCA.

TABLE I
PARAMETERS MODEL IN QCA DESIGNER SIMULATOR

Parameter value
Cell width 18nm
Cell height 18nm
Dot diameter 5nm Figure 13. Simulation of 4-to-16 decoder in cadence tool.

Number of samples 50,000-1,000,000

Convergence tolerance 0.001
Radius of effect 65nm
Relative permittivity 12.9
Clock high 9.8e-23J
Clock low 3.8e-23J
Clock amplitude factor 2
Layer separation 11.5 nm
Maximum iteration per sample 100
Figure 14. Simulation of 16-to-1 mux in QCA.

IV. SIMULATION RESULT

The design and simulation of a 16-bit × 32-bit SRAM in the
QCA technology is presented in this project. The proposed
SRAM is a flexible and powerful structure using
programmable logic and interconnections. The design is
significantly improved because this SRAM has a 32-bit width.
In comparison with other studies, the presented memory cell
acts as a pipeline that decreases delays and increases operating
speed. The designs can be implemented using the QCA
Designer and simulated by the QCA Designer software tool
and also simulated using cadence RTL encounter tool. The
results showed that the proposed QCA based SRAM performs
a task with reduced area and complexity in terms of number of
cells when compared to CMOS based SRAM. Figure 15. Simulation of 16-to-1 mux in cadence tool.
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 299

TABLE II
COMPARISON OF ESTIMATION BETWEEN QCA AND CADENCE TOOL

CMOS Technology Implementation using Cadence QCA Technology using QCA

Tool Designer Tool
S.No Circuit
Component
Area Area Complexity Complexity
Area
(180nm) (45nm) (No. of Gates) (No. of Cells)

32 AND gate and 4 NOT

1 4-to-16 Decoder 323μm² 33 μm² 2.94 μm² 1874
gate.

16-to-1 Mux 30 AND gate,15 OR gate

2 359μm² 149 μm² 1.60 μm² 940
(Proposed) and 4 NOT gate.

8 AND gate, @ NOT

3 4-to-1 Mux 256 μm² 63 μm² 0.18 μm² 148
gate and 1 OR gate.

2 AND gate,2 NOR gate

4 2-to-4 Decoder 79.97 μm² 21 μm² 0.13 μm² 110
and 1 NOT gate.

TABLE III
COMPARISON OF AREA ESTIMATION BETWEEN MOEIN AND REZAL [1] AND
OUR PROPOSED METHOD REFERENCES
[1] M. Kianpour and R. Sabbaghi-Nadooshan, “A Novel Quantum-Dot
S.No Circuit Moein and Rezal Our Porposed Method Cellular Automata X-bit × 32-bit SRAM”, IEEE Transaction on VLSI,
Component [ 1] 2015.
[2] I. Amlani, A. O. Orlov, G. Toth, G. H. Bernstein, C. S. Lent, and G. L.
Area Complexity Area Complexity Snider, “Digital logic gate using quantum-dot cellular automata,”
(μm²) (No. of cells) (μm²) (No of cells) Science, vol. 284, no. 5412, pp. 289–291, 1999.
1 16-to-1 6.09 3873 1.60 940 [3] V. Vankamamidi, M. Ottavi, and F. Lombardi, “A serial memory by
quantum-dot cellular automata (QCA),” IEEE Trans. Comput., vol.
Multiplexer 57,no. 5, pp. 606–618, May 2008.
[4] M. Ottavi, S. Pontarelli, V. Vankamamidi, A. Salsano, and F. Lombardi,
2 4-to-16 2.94 1874 2.94 1874 “QCA memory with parallel read/serial write: Design and analysis,” IEE
Decoder Proc. Circuits, Devices Syst., vol. 153, no. 3, pp. 199–206, Jun. 2006.
[5] C. R. Graunke, D. I. Wheeler, D. Tougaw, and J. D.Will,
3 16bit×32bit 56.03 31003 56.03 31003 “Implementation of a crossbar network using quantum-dot cellular
automata,” IEEE Trans. Nanotechnology, vol. 4, no. 4, pp. 435–440,
SRAM July. 2005.
[6] S. Hashemi and K. Navi, “New robust QCA D flip flop and memory
structures,” Microelectron. J., vol. 43, no. 12, pp. 929–940, 2012.
V. CONCLUSION [7] Cho and E. E. Swartzlander, “Adder and multiplier design in quantum-
dot cellular automata,” IEEE Trans. Comput., vol. 58, no. 6, pp. 721–727,
The results showed that the proposed QCA based SRAM Jun. 2009.
performs a task with reduced area and complexity in terms of [8] R. Sabbaghi-Nadooshan and M. Kianpour, “A novel QCA
number of cells when compared to CMOS based SRAM. implementation of MUX-based universal shift register,” J. Comput.
Electron., vol. 13, no. 1, pp. 198–210, 2014.
TABLE III shows the comparison between QCA and Cadence [9] S. Perri, P. Corsonello, and G. Cocorullo, “Area-delay efficient binary
tool. It is a significant improved in terms of area about adders in QCA,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.
1.60 for 16-to-1 MUX and 2.94 for 4-to-16 Decoder. 22, no. 5, pp. 1174–1179, May 2014.
[10] Douglas Tougaw and Mahfuza Khatun.” A Scalable Signal Distribution
TABLE II shows that our proposed structure of 16-to-1 mux Network for Quantum-Dot Cellular Automata” IEEE Transactions on
has efficient in terms of area and complexity.Thus our Nanotechnology, vol. 12, no. 2, March 2013.
proposed paper have overcome the problems in CMOS [11] M. Kianpour and R. Sabbaghi-Nadooshan, “A conventional design
for CLB implementation of a FPGA in quantum-dot cellular automata
technology on nanoscale. It is expected that the reduction (QCA),” in Proc. IEEE Int. Symp. Nanoarch, July 2012.
method presented in this work would produced significant [12] Hemant Balijepalli, “ Design, implementation, and test of novel
hardware savings for many future QCA architectures. quantum-dot cellular automata FPGAs for the beyond CMOS era”The
university of Toledo, May 2012.