TMS320F28P550SJ, TMS320F28P559SJ-Q1

SPRSP85 – APRIL 2024

TMS320F28P55x Real-Time Microcontrollers

– 5V failsafe and tolerant capability on 4 GPIOs
1 Features for PMBUS/I2C support
• Real-time processing: – Configurable 1.35V VIH on 4 GPIOs
– 150MHz C28x 32-bit DSP CPU • System peripherals
– Equivalent to 300MHz Arm® Cortex®-M7 – 6-channel Direct Memory Access (DMA)
based device on real-time signal chain controller
performance (see the Real-time Benchmarks – 91 individually programmable multiplexed
Showcasing C2000™ Control MCU's Optimized General-Purpose Input/Output (GPIO) pins
Signal Chain Application Note (22 shared with Analog)
– IEEE 754 single-precision Floating-Point Unit – 17 digital inputs on analog pins
(FPU32) – Enhanced Peripheral Interrupt Expansion
– Trigonometric Math Unit (TMU) (ePIE)

ADVANCE INFORMATION
• Support for Nonlinear Proportional Integral – Multiple low-power mode (LPM) support
Derivative (NLPID) control • Communications peripherals
– Neural-Network Processing Unit (NNPU) – One Power-Management Bus (PMBus)
– CRC Engine and Instructions (VCRC) interface
• Programmable Control Law Accelerator (CLA) • Fast Plus Mode Support - 1MHz SCL
– 150MHz • 5V/3.3V/1.35V VIH support on select pins
– Equivalent to 200MHz Arm® Cortex®-M7 – Two Inter-integrated Circuit (I2C) interfaces
based device on real-time signal chain – Two Controller Area Network with Flexible
performance (see the Real-time Benchmarks Data-Rate (CAN FD/MCAN) bus port
Showcasing C2000™ Control MCU's Optimized • 4KB message RAM per MCAN module,
Signal Chain Application Note independent of system memory
– IEEE 754 single-precision floating-point • Ability to re-use RAM for CPU data variables
instructions if MCAN is not used
– Executes code independently of main CPU – One Universal Serial Bus (USB 2.0 MAC +
• On-chip memory PHY)
– 1088KB of flash (ECC-protected) across five – Two Serial Peripheral Interface (SPI) ports
independent banks – Three UART-compatible Serial Communication
• Four 256KB banks Interface (SCI)
• One 64KB bank, ideal of LFU/Bootloaders/ – One UART-compatible Local Interconnect
data Network (LIN) interface
– 8KB of OTP (One Time Programmable flash • Analog system
memory) – Five 3.9MSPS, 12-bit Analog-to-Digital
– 133KB of RAM (ECC/Parity protected) Converters (ADCs)
• Security • Up to 39 external channels (includes one
– Secure Boot gpdac output)
– JTAG Lock • Four integrated Post-Processing Blocks
– Advanced Encryption Standard (AES) (PPB) per ADC
accelerator – Four windowed comparators (CMPSS) with
– Unique Identification (UID) number 12-bit reference Digital-to-Analog Converters
• Clock and system control (DACs)
– Two internal 10MHz oscillators • Digital glitch filters
– Crystal oscillator or external clock input • Low DAC output to pin capability on
– Windowed watchdog timer module CMPSS1
– Missing clock detection circuitry – One 12-bit buffered DAC output
– Dual-clock Comparator (DCC) – Three Programmable Gain Amplifiers (PGAs)
• 3.3V I/O design • Unity gain support
– Internal VREG generation allows for single- • Inverting and non-inverting gain mode
supply design support
– Brownout reset (BOR) circuit • Programmable output filtering

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
 TMS320F28P550SJ, TMS320F28P559SJ-Q1
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• Enhanced control peripherals • Linear motor transport systems

– 24 ePWM channels with 16 channels that have – Linear motor power stage
high-resolution capability (150ps resolution) • Single & multi axis servo drives
• Integrated dead-band support – Servo drive position feedback
• Integrated hardware trip zones (TZs) – Servo drive power stage module
– Two Enhanced Capture (eCAP) modules • Speed controlled BLDC drives
– Three Enhanced Quadrature Encoder Pulse – AC-input BLDC motor drive
(eQEP) modules with support for CW/CCW – DC-input BLDC motor drive
operation modes • Factory automation
– Embedded Pattern Generator (EPG) – Robot servo drive
• Configurable Logic Block (CLB) – Mobile robot motor control
– 2 tiles – Position sensor
– Augments existing peripheral capability • Industrial power
– Supports position manager solutions – Industrial AC-DC
ADVANCE INFORMATION

• Live Firmware Update (LFU) • UPS

• Diagnostic features – Three-phase UPS
– Memory Power-On Self-Test (MPOST) – Single-phase online UPS
• Functional Safety-Compliant targeted • Telecom & server power
– Developed for functional safety applications – Merchant DC/DC
– Documentation available to aid ISO 26262 and – Merchant network & server PSU
IEC 61508 system design – Merchant telecom rectifiers
– Systematic capability up to ASIL D and SIL 3 • Hybrids, electric & powertrain systems
targeted – DC/DC converter
– Hardware integrity up to ASIL B targeted – Inverter & motor control
• Safety-related certification – On-board (OBC) & wireless charger
– ISO 26262 certification up to ASIL B by TÜV – Virtual engine sound system (VESS)
SÜD planned – Engine fan
• Package options: – eTurbo/charger
– 128-pin Thin Quad Flatpack (TQFP) – Pump
[PDT suffix] – Electric power steering (EPS)
– 100-pin Low-profile Quad Flatpack (LQFP) • Infotainment and cluster
[PZ suffix] – Head-up display
– 80-pin TQFP [PNA suffix] – Automotive head unit
– 64-pin LQFP [PM suffix] – Automotive external amplifier
– 56-pin Very Thin Quad Flatpack No-Lead • Body electronics & lighting
(VQFN) [RSH suffix] – Automotive HVAC compressor module
• Temperature options: – DC/AC inverter
– Junction (TJ): –40°C to 150°C – Headlight
2 Applications • ADAS
– Mechanically scanning LIDAR
• Appliances • EV charging infrastructure
– Air conditioner outdoor unit – AC charging (pile) station
• Building automation – DC charging (pile) station
– Door operator drive control – EV charging station power module
• Industrial machine & machine tools – Wireless EV charging station
– Automated sorting equipment • Renewable energy storage
– Textile machine – Energy storage power conversion system
• AC inverter & VF drives (PCS)
– AC drive control module – Portable Power Station
– AC drive position feedback
– AC drive power stage module

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• Solar energy – Solar arc protection

– Central inverter – Rapid shutdown
– Micro inverter – String inverter
– Solar power optimizer
3 Description
The TMS320F28P55x (F28P55x) is a member of the C2000™ real-time microcontroller family of scalable,
ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power
density, high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
• Motor drives
• Appliances
• Hybrid, electric & powertrain systems

ADVANCE INFORMATION
• Solar & EV charging
• Digital power
• Body electronics & lighting
• Test & measurement
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 150MHz of signal-
processing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The
C28x CPU is further boosted by the Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and VCRC
(Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control
systems.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent
32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The F28P55x supports up to 1088KB of flash memory divided into four 256KB banks plus one 64KB bank, which
enable programming one bank and execution in another bank in parallel. Up to 133KB of on-chip SRAM is also
available to supplement the flash memory.
The Live Firmware Update hardware enhancements on F28P55x allow fast context switching from the old
firmware to the new firmware to minimize application downtime when updating the device firmware.
High-performance analog blocks are integrated on the F28P55x real-time microcontroller (MCU) and are closely
coupled with the processing and PWM units to provide optimal real-time signal chain performance. Twenty-four
PWM channels, all supporting frequency-independent resolution modes, enable control of various power stages
from a 3-phase inverter to power factor correction and advanced multilevel power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,
LIN, and CAN FD) and offers multiple pin-muxing options for optimal signal placement.
Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control
system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the
C2000™ real-time control MCUs page.
The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all
aspects of development with C2000 devices from hardware to support resources. In addition to key reference
documents, each section provides relevant links and resources to further expand on the information covered.
Ready to get started? Check out the TMDSCNCD28P55X evaluation board or the LAUNCHXL-F28P55X
development kit, and download C2000Ware.

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Package Information
PART NUMBER(1) PACKAGE(2) PACKAGE SIZE(3)
PDT (QFP, 128) 16mm x 16mm
PZ (QFP, 100) 16mm x 16mm
TMS320F28P559SJ-Q1
PNA (QFP, 80) 12mm x 12mm
PM (QFP, 64) 12mm x 12mm
PDT (QFP, 128) 16mm x 16mm
PZ (QFP, 100) 16mm x 16mm
TMS320F28P550SJ PNA (QFP, 80) 12mm x 12mm
PM (QFP, 64) 12mm x 12mm
RSH (VQFN, 56) 7mm x 7mm
PDT (QFP, 128) 16mm x 16mm
ADVANCE INFORMATION

PZ (QFP, 100) 16mm x 16mm

TMS320F28P559SG-Q1
PNA (QFP, 80) 12mm x 12mm
PM (QFP, 64) 12mm x 12mm
PDT (QFP, 128) 16mm x 16mm
PZ (QFP, 100) 16mm x 16mm
TMS320F28P550SG PNA (QFP, 80) 12mm x 12mm
PM (QFP, 64) 12mm x 12mm
RSH (VQFN, 56) 7mm x 7mm
PZ (QFP, 100) 16mm x 16mm
PNA (QFP, 80) 12mm x 12mm
TMS320F28P550SD
PM (QFP, 64) 12mm x 12mm
RSH (VQFN, 56) 7mm x 7mm

(1) For more information on these devices, see the Device Comparison table.
(2) For more information, see the Mechanical, Packaging and Orderable Information section.
(3) Package size (length x width) is a nominal value and includes pins, where applicable

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3.1 Functional Block Diagram

C28x CPU
(150 MHz)
FPU32 CLA
Boot ROM
TMU (150 MHz)
VCRC
Secure ROM

Flash Bank0
128 Sectors, 256KB CLA to CPU MSG RAM
SYSTEM CONTROL
CPU Timers
XTAL Flash Bank1 CPU to CLA MSG RAM
INTOSC1, INTOSC2 128 Sectors, 256KB
PLL
ePIE
Windowed WD Flash Bank2 CLA Data ROM
NMI WD 128 Sectors, 256KB
CLA Program ROM
Flash Bank3
128 Sectors, 256KB
SECURITY
JTAG Lock Flash Bank4 CLA to DMA MSG RAM

ADVANCE INFORMATION
Secure Boot 32 Sectors, 64 KB
DMA to CLA MSG RAM

M0-M1 RAM
4KB
DIAGNOSTICS Buses Legend
DCC
MPOST LS0-LS9 RAM CPU
ERAD 64KB
NNPU CLA
JTAG/cJTAG
DMA

GS0-GS3 RAM NNPU

64KB DMA
OTHERS
EPG 6 Channels Secure Memories Shown in Red

PF1 PF3 PF4 PF2 PF7 PF8 PF9 PF10 PF11 PF12

Result Data 1x PMBUS 2x CAN FD 1x LIN 3x SCI 2x CLB 1x USB 1x AES LFU
24x ePWM Channels
4x CMPSS NNPU 2x I2C
(16Ch Hi-Res Capable) 5x 12-Bit ADC 65x GPIO 2x SPI
1x FSI RX
Input XBAR
2x eCAP 1x Buffered DAC 1x FSI TX
Output XBAR
ePWM XBAR
3x eQEP CLB XBAR
3x PGA
(CW/CCW Support)
CLB Input XBAR
CLB Output XBAR

A. The internal DAC from one of the CMPSS modules can be configured as an output DAC.
B. The LIN module can also be used as a SCI module.

Figure 3-1. Functional Block Diagram

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Table of Contents
1 Features............................................................................1 6.16 Communications Peripherals................................ 170
2 Applications..................................................................... 2 7 Detailed Description....................................................203
3 Description.......................................................................3 7.1 Overview................................................................. 203
3.1 Functional Block Diagram........................................... 5 7.2 Functional Block Diagram....................................... 204
4 Device Comparison......................................................... 7 7.3 Memory................................................................... 205
4.1 Related Products........................................................ 9 7.4 Identification............................................................217
5 Pin Configuration and Functions.................................10 7.5 Bus Architecture – Peripheral Connectivity.............218
5.1 Pin Diagrams............................................................ 10 7.6 C28x Processor...................................................... 219
5.2 Pin Attributes.............................................................15 7.7 Control Law Accelerator (CLA)............................... 221
5.3 Signal Descriptions................................................... 40 7.8 Embedded Real-Time Analysis and Diagnostic
5.4 Pin Multiplexing.........................................................52 (ERAD)...................................................................... 223
5.5 Pins With Internal Pullup and Pulldown.................... 61 7.9 Direct Memory Access (DMA).................................224
5.6 Connections for Unused Pins................................... 62 7.10 Device Boot Modes...............................................225
ADVANCE INFORMATION

6 Specifications................................................................ 64 7.11 Security................................................................. 232

6.1 Absolute Maximum Ratings...................................... 64 7.12 Watchdog.............................................................. 233
6.2 ESD Ratings – Commercial...................................... 65 7.13 C28x Timers..........................................................234
6.3 ESD Ratings – Automotive....................................... 66 7.14 Dual-Clock Comparator (DCC)............................. 235
6.4 Recommended Operating Conditions.......................66 7.15 Configurable Logic Block (CLB)............................236
6.5 Power Consumption Summary................................. 67 8 Applications, Implementation, and Layout............... 238
6.6 Electrical Characteristics...........................................73 8.1 TI Reference Design............................................... 238
6.7 Thermal Resistance Characteristics for PDT 9 Device and Documentation Support..........................239
Package...................................................................... 75 9.1 Device Nomenclature..............................................239
6.8 Thermal Resistance Characteristics for PZ 9.2 Markings................................................................. 240
Package...................................................................... 75 9.3 Tools and Software................................................. 243
6.9 Thermal Resistance Characteristics for PNA 9.4 Documentation Support.......................................... 244
Package...................................................................... 75 9.5 Support Resources................................................. 245
6.10 Thermal Resistance Characteristics for PM 9.6 Trademarks............................................................. 246
Package...................................................................... 76 9.7 Electrostatic Discharge Caution..............................246
6.11 Thermal Resistance Characteristics for RSH 9.8 Glossary..................................................................246
Package...................................................................... 76 10 Revision History........................................................ 246
6.12 Thermal Design Considerations..............................76 11 Mechanical, Packaging, and Orderable
6.13 System.................................................................... 77 Information.................................................................. 248
6.14 Analog Peripherals................................................120 TAPE AND REEL INFORMATION................................ 249
6.15 Control Peripherals............................................... 159 TRAY.............................................................................251

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4 Device Comparison
Table 4-1. Device Comparison
FEATURE(1) (4) F28P559SJ-Q1(3) F28P550SJ F28P559SG-Q1(3) F28P550SG F28P550SD
C28x Subsystem
Frequency (MHz) 150
32-bit Floating-Point Unit (FPU) Yes
C28x VCRC Yes
TMU - Type 1 Yes - Type 1 - NLPID Instruction Supported
1: F28P559SJ9- 1: F28P559SG9-
Q1, F28P559SJ6- Q1,F28P559SG8-
Number Q1 1 Q1 1
CLA - Type 2 0: F28P559SJ2- 0: F28P559SG2-
Q1 Q1
Frequency (MHz) 150
6-Channel DMA - Type 0 1

ADVANCE INFORMATION
External Interrupts 5
MIPS 300 (CPU + CLA)
Memory
256KB (2 x
Main Array 1MB (4 x 256KB Banks) 512KB (2 x 256KB Banks) 128KB
Banks)
Flash
F28P559SJ9-Q1, F28P550SJ9, F28P559SJ6-Q1, F28P550SJ6,
64KB Bank -
F28P559SG9-Q1, F28P550SG9
User OTP 8KB 2KB
Dedicated 4KB
Local Shared RAM 64KB 32KB
RAM Message 1KB
Global Shared RAM 64KB 32KB
Total RAM 133KB 101KB 69KB
C28x CPUs and CLAs 512 bytes (256 bytes per direction)
Message RAM Types
DMAs and CLAs 512 bytes (256 bytes per direction)
ECC FLASH, Mx RAM
Parity ROM, CAN RAM, Message RAM, LSx RAM, GSx RAM
System
2 tiles - F28P559SJ9-Q1, F28P559SJ6-Q1, F28P550SJ9, F28P550SJ6, F28P559SG9-Q1,
Configurable Logic Block (CLB)
F28P550SG9, F28P559SG8-Q1, F28P550SG8, F28P550SD7
Neural-Network Processing Unit (NNPU) 1 - F28P559SJ9-Q1, F28P550SJ9, F28P559SG9-Q1, F28P550SG9 -
Embedded Pattern Generator (EPG) 1
32-bit CPU Timers 3
Advanced Encryption Standard (AES) Accelerator 1
Live Firmware Update (LFU) Support Yes, with enhancements and flash bank erase time improvements
Security for on-chip flash and RAM Yes
Zero-pin Boot Yes
Secure Boot Yes
JTAG Lock Yes

MPOST Yes

Embedded Real-time Analysis and Diagnostic (ERAD) - Type 2 1

Non-maskable Interrupt Watchdog (NMIWD) timers 1
Watchdog (WD) timers 1
Crystal oscillator/External clock input 1
Internal Oscillator (Optional External Precision Resistor) 2

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Table 4-1. Device Comparison (continued)

FEATURE(1) (4) F28P559SJ-Q1(3) F28P550SJ F28P559SG-Q1(3) F28P550SG F28P550SD
Digital and Analog Pin Counts
128-pin PDT 65 65 - F28P559SG9-Q1, F28P550SG9 -
100-pin PZ 43
80-pin PNA 32
GPIO
64-pin PM 17
56-pin RSH - 15 - 15
Additional GPIO 4 (2 from cJTAG and 2 from X1/X2)
128-pin PDT 17 17 - F28P559SG9-Q1, F28P550SG9 -
100-pin PZ 16 16
AIO (analog with digital inputs) 80-pin PNA 12
64-pin PM 12
56-pin RSH - 12 - 12
128-pin PDT 22 22 - F28P559SG9-Q1, F28P550SG9 -
ADVANCE INFORMATION

100-pin PZ 19
AGPIO (analog with digital inputs and outputs) 80-pin PNA 16
64-pin PM 16
56-pin RSH - 14 - 14
C28x Analog Peripherals(5)
Number of ADCs 5
MSPS 3.9
Analog-to-Digital Converter (ADC) (12-bit) - Type 6
Conversion Time
187
(ns)(2)
128-pin PDT 39 39 - F28P559SG9-Q1, F28P550SG9 -
100-pin PZ 35
ADC Input channels (single-ended) (includes the two DAC outputs) 80-pin PNA 28
64-pin PM 28
56-pin RSH 26 26
PGA - Type 2 3
Temperature Sensor 1
Comparator subsystem (CMPSS) (each CMPSS has two comparators and two internal
4
DACs) - Type 6
Buffered Digital-to-Analog Converter (DAC) - Type 2 1
DAC Out from CMPSS 1
C28x Control Peripherals(5)
eCAP - Type 2 Total inputs 2
24
- F28P559SJ9- 24 -
Q1,F28P559SJ6- F28P559SG9-Q1,
Total channels 24 24
Q1 F28P559SG8-Q1
16 - F28P559J2- 16 - F28P559SG2
ePWM/HRPWM - Type 4 Q1
12- F28P559SJ9-
12 -
Q1,F28P559SJ6-
F28P559SG9-Q1,
Channels with high-resolution capability Q1 12 12
F28P559SG8-Q1
8 - F28P559SJ2-
8 - F28P559SG2
Q1
eQEP modules - Type 2 3
C28x Communications Peripherals(5)
CAN with Flexible Data-Rate (CAN-FD) - Type 2 2
Fast Serial Interface (FSI) RX - Type 2 1
Fast Serial Interface (FSI) TX - Type 2 1
Inter-Integrated Circuit (I2C) - Type 2 2
Local Interconnect Network (LIN) - Type 1 1
Power Management Bus (PMBus) - Type 1 1
Serial Communications Interface (SCI) - Type 0 (UART-compatible) 3
Serial Peripheral Interface (SPI) - Type 2 2
1 - F28P559SJ9-Q1, F28P550SJ9,
Universal Serial Bus (USB) - Type 0 1 - F28P559SG9-Q1, F28P550SG9 -
F28P559SJ6-Q1, F28P550SJ6

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Table 4-1. Device Comparison (continued)

FEATURE(1) (4) F28P559SJ-Q1(3) F28P550SJ F28P559SG-Q1(3) F28P550SG F28P550SD
Temperature and Qualification
Junction temperature (TJ) -40°C to 150°C
Free-Air temperature (TA) -40°C to 125°C
F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9,
128-pin PDT -
F28P550SJ6, F28P559SG9-Q1, F28P550SG9
F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
100-pin PZ F28P559SG9-Q1,F28P559SG8-Q1, F28P559SG2-Q1, F28P550SG9, F28P550SG8,
F28P550SD7
F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
80-pin PNA F28P559SG9-Q1, F28P559SG8-Q1, F28P559SG2-Q1, F28P550SG9, F28P550SG8,
Package Options
F28P550SD7
F28P559SJ9-Q1, F28P559SJ6-Q1, F28P559SJ2-Q1, F28P550SJ9, F28P550SJ6,
64-pin PM F28P559SG9-Q1, F28P559SG8-Q1, F28P559SG2-Q1, F28P550SG9, F28P550SG8,
F28P550SD7
F28P550SJ9,
F28P550SG9, F28P550SG8,
56-pin RSH - F28P550SJ6, -

ADVANCE INFORMATION
F28P550SD7
F28P550SG9

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) The suffix -Q1 refers to AEC Q100 qualification for automotive applications.
(4) "-" on the feature entry indicates that the corresponding package type in not available.
(5) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number.

4.1 Related Products

TMS320F280013x Real-Time Microcontrollers
The F280013x has common pinouts with the F28P55x series of devices. The F28P55x series adds CLA and
DMA support, in addition to faster CPU clock speed and increased memory size. Additionally the F28P55x has
Programmable Gain Amplifiers(PGA), USB, CLB and supports live FW update.
TMS320F28015x Real-Time Microcontrollers
The F280015x has common pinouts with the F28P55x series of devices. The F28P55x series adds CLA and
DMA support, in addition to faster CPU clock speed and increased memory size. Additionally the F28P55x
has Programmable Gain Amplifiers(PGA), USB, CLB and supports live FW update. The F280015x series has
lockstep C28x CPUs for safety related systems.
TMS320F28003x Real-Time Microcontrollers
The F28003x has common pinouts with the F28P55x series of devices. The F28P55x series has a faster overall
CPU clock and increased memory options in addition to Programmable Gain Amplifiers(PGA) and USB support.
The F28003x series offers SDFM support, along with BGCRC and HWBIST.

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5 Pin Configuration and Functions

5.1 Pin Diagrams
Figure 5-1 shows the pin assignments on the 128-pin PDT thin quad flatpack. Figure 5-2 shows the pin
assignments on the 100-pin PZ low-profile quad flatpack. Figure 5-3 shows the pin assignments on the 80-pin
PNA thin quad flatpack. Figure 5-4 shows the pin assignments on the 64-pin PM low-profile quad flatpack.
Figure 5-5 shows the pin assignments on the 56-pin RSH very thin quad flatpack no-lead.

GPIO23,USB0DM
GPIO41,USB0DP
ADVANCE INFORMATION

GPIO31

GPIO30

GPIO14

GPIO15

GPIO34

GPIO10

GPIO59

GPIO61

GPIO81

GPIO80

GPIO79

GPIO78

GPIO77

GPIO76

GPIO75

GPIO45

GPIO44

GPIO22

GPIO40
VDDIO
GPIO6

GPIO9

GPIO5

GPIO7

GPIO0

GPIO1

GPIO2

GPIO3
VDD

VSS
128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97
GPIO29 1 96 GPIO4

A16,B16,C16,GPIO28 2 95 GPIO8

XRSn 3 94 GPIO42

GPIO46 4 93 VREGENZ

VDDIO 5 92 VSS

VDD 6 91 GPIO43

VSS 7 90 VDD

GPIO47 8 89 VDDIO

GPIO66 9 88 GPIO19,X1

GPIO67 10 87 GPIO18,X2

GPIO48 11 86 GPIO74

GPIO49 12 85 GPIO73

GPIO50 13 84 GPIO72

GPIO51 14 83 GPIO71

GPIO52 15 82 GPIO58

GPIO53 16 81 GPIO57

GPIO54 17 80 GPIO56

A6,D14,E14,GPIO228 18 79 GPIO32

B2,C6,E12,GPIO226 19 78 GPIO35/TDI

A3,B3,C5,GPIO242,PGA2_INP 20 77 TMS

A2,B6,C9,GPIO224,PGA1_INP 21 76 GPIO37/TDO

A15,B9,C7,PGA1_INM 22 75 TCK

C25,D5,E5 23 74 GPIO70

A26,D6,E6 24 73 GPIO69

B26,D7,E7 25 72 GPIO68

A14,B14,C4,PGA1_OUT 26 71 GPIO27

A11,B10,C0,PGA2_OUT 27 70 GPIO26

A5,B12,C2,PGA2_INM 28 69 GPIO25

A1,B7,D11,DACB_OUT 29 68 B25,D4,E4,GPIO24

A0,B15,C15,DACA_OUT 30 67 A25,D3,E3,GPIO17

D20,E20,VREFHI 31 66 C24,D2,E2,GPIO16

D20,E20,VREFHI 32 65 B24,D1,E1,GPIO33
33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

Not to scale
A13,B13,C13,D13,E13,VREFLO

A13,B13,C13,D13,E13,VREFLO

A12,C1,E11,PGA3_INP

B11,D16,E16,PGA3_INM

A7,B30,C3,D12,E30

B5,D15,E15,PGA3_OUT

A8,B0,C11

VSSA

VDDA

A4,B8,C14

C26,D8,E8,GPIO211

A27,D9,E9,GPIO212

B27,D10,E10,GPIO213

C27,D18,E18,GPIO214

A28,D19,E19,GPIO215

A9,GPIO227

B4,C8,GPIO236

A10,B1,C10,GPIO230

GPIO55

GPIO60

VSS

VDD

VDDIO

GPIO64

GPIO65

GPIO62

GPIO63

A17,B17,C17,GPIO20

A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

A20,B20,C20,GPIO12

A24,D0,E0,GPIO11

A. Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-1. 128-pin PDT Thin Quad Flatpack (Top View)

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GPIO23,USB0DM
GPIO41,USB0DP
GPIO29

GPIO31

GPIO30

GPIO14

GPIO15

GPIO34

GPIO10

GPIO59

GPIO61

GPIO44

GPIO22

GPIO40
VDDIO
GPIO6

GPIO9

GPIO5

GPIO7

GPIO0

GPIO1

GPIO2

GPIO3
VDD

VSS
100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76
A16,B16,C16,GPIO28 1 75 GPIO4

XRSn 2 74 GPIO8

VDDIO 3 73 VREGENZ

VDD 4 72 VSS

ADVANCE INFORMATION
VSS 5 71 VDD

GPIO47 6 70 VDDIO

GPIO48 7 69 GPIO19,X1

GPIO49 8 68 GPIO18,X2

GPIO50 9 67 GPIO58

GPIO51 10 66 GPIO57

GPIO52 11 65 GPIO56

GPIO53 12 64 GPIO32

GPIO54 13 63 GPIO35/TDI

A6,D14,E14,GPIO228 14 62 TMS

B2,C6,E12,GPIO226 15 61 GPIO37/TDO

B3,GPIO242,PGA2_INP 16 60 TCK

A2,B6,C9,GPIO224,PGA1_INP 17 59 GPIO27

A3,B9,C7,PGA1_INM 18 58 GPIO26

A14,B14,C4,PGA1_OUT 19 57 GPIO25

A11,B10,C0,PGA2_OUT 20 56 B25,D4,E4,GPIO24

B12,C2,PGA2_INM 21 55 A25,D3,E3,GPIO17

A1,B7,D11,DACB_OUT 22 54 C24,D2,E2,GPIO16

A0,B15,C15,DACA_OUT 23 53 B24,D1,E1,GPIO33

D20,E20,VREFHI 24 52 A24,D0,E0,GPIO11

D20,E20,VREFHI 25 51 A20,B20,C20,GPIO12
26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Not to scale
A13,B13,C13,D13,E13,VREFLO

A13,B13,C13,D13,E13,VREFLO

A12,C5

C1,E11,PGA3_INP

B11,D16,E16,PGA3_INM

A7,B30,C3,D12,E30

B5,D15,E15,PGA3_OUT

VSSA

VDDA

A5

A4,B8

A8

A9,GPIO227

B4,C8,GPIO236

A10,B1,C10,GPIO230

B0,C11,GPIO253

C14,GPIO247

GPIO55

GPIO60

VSS

GPIO62

GPIO63

A17,B17,C17,GPIO20

A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

A. Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-2. 100-Pin PZ Low-Profile Quad Flatpack (Top View)

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GPIO23,USB0DM
GPIO41,USB0DP
GPIO14

GPIO15

GPIO34

GPIO10

GPIO45

GPIO44

GPIO22

GPIO40
VDDIO
GPIO6

GPIO9

GPIO5

GPIO7

GPIO0

GPIO1

GPIO2
VDD

VSS
80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61
GPIO30 1 60 GPIO3

GPIO31 2 59 GPIO4
ADVANCE INFORMATION

GPIO29 3 58 GPIO8

A16,B16,C16,GPIO28 4 57 GPIO42

XRSn 5 56 VREGENZ

GPIO46 6 55 VSS

VDDIO 7 54 GPIO43

VDD 8 53 VDD

VSS 9 52 VDDIO

A6,D14,E14,GPIO228 10 51 GPIO19,X1

B2,C6,E12,GPIO226 11 50 GPIO18,X2

A3,B3,C5,GPIO242,PGA2_INP 12 49 GPIO32

A2,B6,C9,GPIO224,PGA1_INP 13 48 GPIO35/TDI

A15,B9,C7,PGA1_INM 14 47 TMS

A14,B14,C4,PGA1_OUT 15 46 GPIO37/TDO

A11,B10,C0,PGA2_OUT 16 45 TCK

A5,B12,C2,PGA2_INM 17 44 GPIO27

A1,B7,D11,DACB_OUT 18 43 GPIO26

A0,B15,C15,DACA_OUT 19 42 GPIO25

D20,E20,VREFHI 20 41 B25,D4,E4,GPIO24
21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

Not to scale
A13,B13,C13,D13,E13,VREFLO

A12,C1,E11,PGA3_INP

A7,B30,C3,D12,E30,PGA3_INM

A8,B0,C11,PGA3_OUT

VSSA

VDDA

A4,B8,C14

A9,B4,C8,GPIO227,GPIO236

A10,B1,C10,GPIO230

VSS

GPIO62

GPIO63

A17,B17,C17,GPIO20

A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

A20,B20,C20,GPIO12

A24,D0,E0,GPIO11

B24,D1,E1,GPIO33

C24,D2,E2,GPIO16

A25,D3,E3,GPIO17

A. Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-3. 80-Pin PNA Thin Quad Flatpack (Top View)

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GPIO23,USB0DM
GPIO41,USB0DP
GPIO10

GPIO22

GPIO40
VDDIO
GPIO6

GPIO9

GPIO5

GPIO7

GPIO0

GPIO1

GPIO2

GPIO3
VDD

VSS
64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49
GPIO29 1 48 GPIO4

ADVANCE INFORMATION
A16,B16,C16,GPIO28 2 47 GPIO8

XRSn 3 46 VREGENZ

VDD 4 45 VSS

VSS 5 44 VDD

A6,D14,E14,GPIO228 6 43 VDDIO

B2,C6,E12,GPIO226 7 42 GPIO19,X1

A3,B3,C5,GPIO242,PGA2_INP 8 41 GPIO18,X2

A2,B6,C9,GPIO224,PGA1_INP 9 40 GPIO32

A15,B9,C7,PGA1_INM 10 39 GPIO35/TDI

A14,B14,C4,PGA1_OUT 11 38 TMS

A11,B10,C0,PGA2_OUT 12 37 GPIO37/TDO

A5,B12,C2,PGA2_INM 13 36 TCK

A1,B7,D11,DACB_OUT 14 35 B25,D4,E4,GPIO24

A0,B15,C15,DACA_OUT 15 34 A25,D3,E3,GPIO17

D20,E20,VREFHI 16 33 C24,D2,E2,GPIO16
17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Not to scale
A13,B13,C13,D13,E13,VREFLO

A12,C1,E11,PGA3_INP

A7,B30,C3,D12,E30,PGA3_INM

A8,B0,C11,PGA3_OUT

VSSA

VDDA

A4,B8,C14

A9,B4,C8,GPIO227,GPIO236

A10,B1,C10,GPIO230

VSS

A17,B17,C17,GPIO20

A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

A20,B20,C20,GPIO12

A24,D0,E0,GPIO11

B24,D1,E1,GPIO33

A. Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-4. 64-Pin PM Low-Profile Quad Flatpack (Top View)

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GPIO23,USB0DM
GPIO41,USB0DP
GPIO22

GPIO40
VDDIO
GPIO9

GPIO5

GPIO7

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4
VDD
56

55

54

53

52

51

50

49

48

47

46

45

44

43
GPIO6 1 42 VREGENZ
ADVANCE INFORMATION

GPIO29 2 41 VDD

A16,B16,C16,GPIO28 3 40 VDDIO

XRSn 4 39 GPIO19,X1

VDD 5 38 GPIO18,X2

A3,B3,C5,GPIO242,PGA2_INP 6 37 GPIO32

A2,B6,C9,GPIO224,PGA1_INP 7 36 GPIO35/TDI
VSS
A15,B9,C7,PGA1_INM 8 35 TMS

A14,B14,C4,PGA1_OUT 9 34 GPIO37/TDO

A11,B10,C0,PGA2_OUT 10 33 TCK

A5,B12,C2,PGA2_INM 11 32 B25,D4,E4,GPIO24

A1,B7,D11,DACB_OUT 12 31 A25,D3,E3,GPIO17

A0,B15,C15,DACA_OUT 13 30 C24,D2,E2,GPIO16

D20,E20,VREFHI 14 29 B24,D1,E1,GPIO33
15

16

17

18

19

20

21

22

23

24

25

26

27

28
A13,B13,C13,D13,E13,VREFLO

A12,C1,E11,PGA3_INP

A7,B30,C3,D12,E30,PGA3_INM

A8,B0,C11,PGA3_OUT

VSSA

VDDA

A4,B8,C14

A9,B4,C8,GPIO227,GPIO236

A10,B1,C10,GPIO230

A17,B17,C17,GPIO20

A18,B18,C18,GPIO21

A19,B19,C19,GPIO13

A20,B20,C20,GPIO12

A24,D0,E0,GPIO11

Not to scale

A. Only the GPIO function is shown on GPIO pins. See the Pin Attributes table for the complete, muxed signal name.

Figure 5-5. 56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View)

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5.2 Pin Attributes

Table 5-1. Pin Attributes
128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
ANALOG
A0 I ADC-A Input 0
B15 I ADC-B Input 15
C15 I ADC-C Input 15
CMP3_HP2 30 23 19 15 13 I CMPSS-3 High Comparator Positive Input 2
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2
DACA_OUT O Buffered DAC-A Output.
AIO231 0, 4, 8, 12 I Analog Pin Used For Digital Input 231
A1 I ADC-A Input 1

ADVANCE INFORMATION
B7 I ADC-B Input 7
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4
CMP1_LP4 29 22 18 14 12 I CMPSS-1 Low Comparator Positive Input 4
D11 I ADC-D Input 11
DACB_OUT O Buffered DAC-B Output.
AIO232 0, 4, 8, 12 I Analog Pin Used For Digital Input 232
A2 I ADC-A Input 2
B6 I ADC-B Input 6
C9 I ADC-C Input 9
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0
21 17 13 9 7
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0
General-Purpose Input Output 224 This pin also has
GPIO224 I/O digital mux functions which are described in the GPIO
section of this table.
PGA1_INP I PGA-1 Plus
A3 I ADC-A Input 3
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5
18
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5
AIO229 0, 4, 8, 12 I Analog Pin Used For Digital Input 229
A3 I ADC-A Input 3
CMP3_HP5 20 12 8 6 I CMPSS-3 High Comparator Positive Input 5
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5
A4 I ADC-A Input 4
B8 I ADC-B Input 8
CMP2_HP0 42 36 27 23 21 I CMPSS-2 High Comparator Positive Input 0
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0
AIO225 0, 4, 8, 12 I Analog Pin Used For Digital Input 225
A5 I ADC-A Input 5
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5
35
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5
AIO249 0, 4, 8, 12 I Analog Pin Used For Digital Input 249
A5 I ADC-A Input 5
CMP2_HP5 28 17 13 11 I CMPSS-2 High Comparator Positive Input 5
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
A6 I ADC-A Input 6
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2
D14 18 14 10 6 I ADC-D Input 14
E14 I ADC-E Input 14
General-Purpose Input Output 228 This pin also has
GPIO228 I/O digital mux functions which are described in the GPIO
section of this table.
A7 I ADC-A Input 7
B30 I ADC-B Input 30
C3 I ADC-C Input 3
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1
ADVANCE INFORMATION

CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1

37 31 23 19 17
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1
D12 I ADC-D Input 12
E30 I ADC-E Input 30
AIO245 0, 4, 8, 12 I Analog Pin Used For Digital Input 245
A8 I ADC-A Input 8
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
37
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO240 0, 4, 8, 12 I Analog Pin Used For Digital Input 240
A8 I ADC-A Input 8
B0 I ADC-B Input 0
C11 I ADC-C Input 11
39 24 20 18
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4
AIO241 0, 4, 8, 12 I Analog Pin Used For Digital Input 241
A9 I ADC-A Input 9
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2
CMP2_LP2 48 38 28 24 22 I CMPSS-2 Low Comparator Positive Input 2
General-Purpose Input Output 227 This pin also has
GPIO227 I/O digital mux functions which are described in the GPIO
section of this table.
A10 I ADC-A Input 10
B1 I ADC-B Input 1
C10 I ADC-C Input 10
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0
CMP2_HP3 50 40 29 25 23 I CMPSS-2 High Comparator Positive Input 3
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
General-Purpose Input Output 230 This pin also has
GPIO230 I/O digital mux functions which are described in the GPIO
section of this table.

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
A11 I ADC-A Input 11
B10 I ADC-B Input 10
C0 I ADC-C Input 0
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1
CMP1_HP1 27 20 16 12 10 I CMPSS-1 High Comparator Positive Input 1
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1
PGA2_OUT O PGA-2 Output
AIO237 0, 4, 8, 12 I Analog Pin Used For Digital Input 237
A12 I ADC-A Input 12
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1

ADVANCE INFORMATION
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1
35 28 22 18 16
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1
AIO238 0, 4, 8, 12 I Analog Pin Used For Digital Input 238
A13 I ADC-A Input 13
B13 I ADC-B Input 13
C13 I ADC-C Input 13
D13 34 26 21 17 15 I ADC-D Input 13
E13 I ADC-E Input 13
VREFLO I ADC Low Reference
AIO235 0, 4, 8, 12 I Analog Pin Used For Digital Input 235
A13 I ADC-A Input 13
B13 I ADC-B Input 13
C13 I ADC-C Input 13
D13 33, 34 26, 27 21 17 15 I ADC-D Input 13
E13 I ADC-E Input 13
VREFLO I ADC Low Reference
AIO235 ALT I Analog Pin Used For Digital Input 235
A14 I ADC-A Input 14
B14 I ADC-B Input 14
C4 I ADC-C Input 4
CMP3_HP4 26 19 15 11 9 I CMPSS-3 High Comparator Positive Input 4
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4
PGA1_OUT O PGA-1 Output
AIO239 0, 4, 8, 12 I Analog Pin Used For Digital Input 239
A15 I ADC-A Input 15
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3
22 14 10 8
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3
AIO233 0, 4, 8, 12 I Analog Pin Used For Digital Input 233
A16 I ADC-A Input 16
B16 I ADC-B Input 16
C16 2 1 4 2 3 I ADC-C Input 16
General-Purpose Input Output 28 This pin also has
GPIO28 I/O digital mux functions which are described in the GPIO
section of this table.

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
A17 I ADC-A Input 17
B17 I ADC-B Input 17
C17 60 48 33 27 24 I ADC-C Input 17
General-Purpose Input Output 20 This pin also has
GPIO20 I/O digital mux functions which are described in the GPIO
section of this table.
A18 I ADC-A Input 18
B18 I ADC-B Input 18
C18 61 49 34 28 25 I ADC-C Input 18
General-Purpose Input Output 21 This pin also has
GPIO21 I/O digital mux functions which are described in the GPIO
section of this table.
ADVANCE INFORMATION

A19 I ADC-A Input 19

B19 I ADC-B Input 19
C19 62 50 35 29 26 I ADC-C Input 19
General-Purpose Input Output 13 This pin also has
GPIO13 I/O digital mux functions which are described in the GPIO
section of this table.
A20 I ADC-A Input 20
B20 I ADC-B Input 20
C20 63 51 36 30 27 I ADC-C Input 20
General-Purpose Input Output 12 This pin also has
GPIO12 I/O digital mux functions which are described in the GPIO
section of this table.
A24 I ADC-A Input 24
D0 I ADC-D Input 0
E0 64 52 37 31 28 I ADC-E Input 0
General-Purpose Input Output 11 This pin also has
GPIO11 I/O digital mux functions which are described in the GPIO
section of this table.
A25 I ADC-A Input 25
D3 I ADC-D Input 3
E3 67 55 40 34 31 I ADC-E Input 3
General-Purpose Input Output 17 This pin also has
GPIO17 I/O digital mux functions which are described in the GPIO
section of this table.
A26 I ADC-A Input 26
D6 I ADC-D Input 6
24
E6 I ADC-E Input 6
AIO209 0, 4, 8, 12 I Analog Pin Used For Digital Input 209
A27 I ADC-A Input 27
AIO227 I Analog Pin Used For Digital Input 227
44
D9 I ADC-D Input 9
E9 I ADC-E Input 9
A28 I ADC-A Input 28
AIO243 I Analog Pin Used For Digital Input 243
47
D19 I ADC-D Input 19
E19 I ADC-E Input 19
B0 I ADC-B Input 0
C11 I ADC-C Input 11
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3
41
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3
General-Purpose Input Output 231 This pin also has
GPIO231 I/O digital mux functions which are described in the GPIO
section of this table.

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
B2 I ADC-B Input 2
C6 I ADC-C Input 6
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0
CMP3_LP0 19 15 11 7 I CMPSS-3 Low Comparator Positive Input 0
E12 I ADC-E Input 12
General-Purpose Input Output 226 This pin also has
GPIO226 I/O digital mux functions which are described in the GPIO
section of this table.
B3 I ADC-B Input 3
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0

ADVANCE INFORMATION
20 16 12 8 6
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3
General-Purpose Input Output 242 This pin also has
GPIO242 I/O digital mux functions which are described in the GPIO
section of this table.
PGA2_INP I PGA-2 Plus
B4 I ADC-B Input 4
C8 I ADC-C Input 8
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0
49 39 28 24 22
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0
General-Purpose Input Output 236 This pin also has
GPIO236 0, 4, 8, 12 I/O digital mux functions which are described in the GPIO
section of this table.
B5 I ADC-B Input 5
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5
38 32
D15 I ADC-D Input 15
E15 I ADC-E Input 15
AIO252 0, 4, 8, 12 I Analog Pin Used For Digital Input 252
B9 I ADC-B Input 9
C7 22 18 14 10 8 I ADC-C Input 7
PGA1_INM I PGA-1 Minus
B11 I ADC-B Input 11
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5
36 30
D16 I ADC-D Input 16
E16 I ADC-E Input 16
AIO251 0, 4, 8, 12 I Analog Pin Used For Digital Input 251
B12 I ADC-B Input 12
C2 I ADC-C Input 2
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1
28 21 17 13 11
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1
PGA2_INM I PGA-2 Minus
AIO244 0, 4, 8, 12 I Analog Pin Used For Digital Input 244
B24 I ADC-B Input 24
D1 I ADC-D Input 1
E1 65 53 38 32 29 I ADC-E Input 1
General-Purpose Input Output 33 This pin also has
GPIO33 I/O digital mux functions which are described in the GPIO
section of this table.

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
B25 I ADC-B Input 25
D4 I ADC-D Input 4
E4 68 56 41 35 32 I ADC-E Input 4
General-Purpose Input Output 24 This pin also has
GPIO24 I/O digital mux functions which are described in the GPIO
section of this table.
B26 I ADC-B Input 26
D7 I ADC-D Input 7
25
E7 I ADC-E Input 7
AIO210 0, 4, 8, 12 I Analog Pin Used For Digital Input 210
AIO228 I Analog Pin Used For Digital Input 228
B27 I ADC-B Input 27
ADVANCE INFORMATION

45
D10 I ADC-D Input 10
E10 I ADC-E Input 10
C1 I ADC-C Input 1
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2
35 29 22 18 16
E11 I ADC-E Input 11
PGA3_INP I PGA-3 Plus
AIO248 0, 4, 8, 12 I Analog Pin Used For Digital Input 248
C5 20 28 12 8 6 I ADC-C Input 5
C14 I ADC-C Input 14
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 42 I CMPSS-4 Low Comparator Negative Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
General-Purpose Input Output 247 This pin also has
GPIO247 I/O digital mux functions which are described in the GPIO
section of this table.
C14 I ADC-C Input 14
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0
CMP4_HP3 42 27 23 21 I CMPSS-4 High Comparator Positive Input 3
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3
C24 I ADC-C Input 24
D2 I ADC-D Input 2
E2 66 54 39 33 30 I ADC-E Input 2
General-Purpose Input Output 16 This pin also has
GPIO16 I/O digital mux functions which are described in the GPIO
section of this table.
AIO253 I Analog Pin Used For Digital Input 253
C25 I ADC-C Input 25
D5 23 I ADC-D Input 5
E5 I ADC-E Input 5
AIO208 0, 4, 8, 12 I Analog Pin Used For Digital Input 208
AIO226 I Analog Pin Used For Digital Input 226
C26 I ADC-C Input 26
43
D8 I ADC-D Input 8
E8 I ADC-E Input 8

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
AIO242 I Analog Pin Used For Digital Input 242
C27 I ADC-C Input 27
46
D18 I ADC-D Input 18
E18 I ADC-E Input 18
D20 I ADC-D Input 20
E20 I ADC-E Input 20
ADC High Reference. In external reference mode,
externally drive the high reference voltage onto this
31 24 20 16 14 pin. In internal reference mode, a voltage is driven
VREFHI I onto this pin by the device. In either mode, place at
least a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
between the VREFHI and VREFLO pins.

ADVANCE INFORMATION
AIO234 0, 4, 8, 12 I Analog Pin Used For Digital Input 234
D20 I ADC-D Input 20
E20 I ADC-E Input 20
ADC High Reference. In external reference mode,
externally drive the high reference voltage onto this
32 25 20 16 14 pin. In internal reference mode, a voltage is driven
VREFHI I onto this pin by the device. In either mode, place at
least a 2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as possible
between the VREFHI and VREFLO pins.
AIO234 ALT I Analog Pin Used For Digital Input 234
PGA3_INM 36 30 23 19 17 I PGA-3 Minus
PGA3_OUT 38 32 24 20 18 O PGA-3 Output
GPIO
General-Purpose Input Output 236 This pin also has
GPIO236 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EPWM7_A 1 49 39 28 24 22 O ePWM-7 Output A
EQEP1_INDEX 5 I/O eQEP-1 Index
EPWM12_A 9 O ePWM-12 Output A
GPIO0 0, 4, 8, 12 I/O General-Purpose Input Output 0
EPWM1_A 1 O ePWM-1 Output A
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_RX 5 I SCI-A Receive Data
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SPIA_PTE 7 100 79 63 52 47 I/O SPI-A Peripheral Transmit Enable (PTE)
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANA_RX 10 I CAN/CAN FD Receive
CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8
EQEP1_INDEX 13 I/O eQEP-1 Index
EPWM3_A 15 O ePWM-3 Output A
GPIO1 0, 4, 8, 12 I/O General-Purpose Input Output 1
EPWM1_B 1 O ePWM-1 Output B
SCIA_TX 5 O SCI-A Transmit Data
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_POCI 7 I/O SPI-A Peripheral Out, Controller In (POCI)
99 78 62 51 46
EQEP1_STROBE 9 I/O eQEP-1 Strobe
MCANA_TX 10 O CAN/CAN FD Transmit
CLB_OUTPUTXBAR7 11 O CLB Output X-BAR Output 7
EPWM10_B 13 O ePWM-10 Output B
EPWM3_B 15 O ePWM-3 Output B

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO2 0, 4, 8, 12 I/O General-Purpose Input Output 2
EPWM2_A 1 O ePWM-2 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
SCIA_TX 9 98 77 61 50 45 O SCI-A Transmit Data
FSIRXA_D1 10 I FSIRX-A Optional Additional Data Input
I2CB_SDA 11 I/OD I2C-B Open-Drain Bidirectional Data
EPWM10_A 13 O ePWM-10 Output A
MCANB_TX 14 O CAN/CAN FD Transmit
EPWM4_A 15 O ePWM-4 Output A
ADVANCE INFORMATION

GPIO3 0, 4, 8, 12 I/O General-Purpose Input Output 3

EPWM2_B 1 O ePWM-2 Output B
OUTPUTXBAR2 2, 5 O Output X-BAR Output 2
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIA_CLK 7 I/O SPI-A Clock
97 76 60 49 44
SCIA_RX 9 I SCI-A Receive Data
FSIRXA_D0 10 I FSIRX-A Primary Data Input
I2CB_SCL 11 I/OD I2C-B Open-Drain Bidirectional Clock
MCANB_RX 14 I CAN/CAN FD Receive
EPWM4_B 15 O ePWM-4 Output B
GPIO4 0, 4, 8, 12 I/O General-Purpose Input Output 4
EPWM3_A 1 O ePWM-3 Output A
I2CA_SCL 2 I/OD I2C-A Open-Drain Bidirectional Clock
MCANA_TX 3 O CAN/CAN FD Transmit
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIB_CLK 7 I/O SPI-B Clock
96 75 59 48 43
EQEP2_STROBE 9 I/O eQEP-2 Strobe
FSIRXA_CLK 10 I FSIRX-A Input Clock
CLB_OUTPUTXBAR6 11 O CLB Output X-BAR Output 6
EPWM11_B 13 O ePWM-11 Output B
SPIA_POCI 14 I/O SPI-A Peripheral Out, Controller In (POCI)
EPWM1_A 15 O ePWM-1 Output A
GPIO5 0, 4, 8, 12 I/O General-Purpose Input Output 5
EPWM3_B 1 O ePWM-3 Output B
I2CA_SDA 2 I/OD I2C-A Open-Drain Bidirectional Data
OUTPUTXBAR3 3 O Output X-BAR Output 3
MCANA_RX 5 I CAN/CAN FD Receive
118 89 74 61 55
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5 10 O CLB Output X-BAR Output 5
SCIA_RX 11 I SCI-A Receive Data
EPWM1_B 15 O ePWM-1 Output B

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO6 0, 4, 8, 12 I/O General-Purpose Input Output 6
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR4 2 O Output X-BAR Output 4
SYNCOUT 3 O External ePWM Synchronization Pulse
EQEP1_A 5 I eQEP-1 Input A
126 97 80 64 1
SPIB_POCI 7 I/O SPI-B Peripheral Out, Controller In (POCI)
FSITXA_D0 9 O FSITX-A Primary Data Output
FSITXA_D1 11 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR8 14 O CLB Output X-BAR Output 8
EPWM2_A 15 O ePWM-2 Output A
GPIO7 0, 4, 8, 12 I/O General-Purpose Input Output 7

ADVANCE INFORMATION
EPWM4_B 1 O ePWM-4 Output B
EPWM2_A 2 O ePWM-2 Output A
OUTPUTXBAR5 3 O Output X-BAR Output 5
EQEP1_B 5 I eQEP-1 Input B
SPIB_PICO 7 105 84 68 57 52 I/O SPI-B Peripheral In, Controller Out (PICO)
FSITXA_CLK 9 O FSITX-A Output Clock
CLB_OUTPUTXBAR2 10 O CLB Output X-BAR Output 2
SCIA_TX 11 O SCI-A Transmit Data
MCANA_TX 14 O CAN/CAN FD Transmit
EPWM2_B 15 O ePWM-2 Output B
GPIO8 0, 4, 8, 12 I/O General-Purpose Input Output 8
EPWM5_A 1 O ePWM-5 Output A
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIA_TX 6 O SCI-A Transmit Data
95 74 58 47
SPIA_PICO 7 I/O SPI-A Peripheral In, Controller Out (PICO)
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D1 10 O FSITX-A Optional Additional Data Output
CLB_OUTPUTXBAR5 11 O CLB Output X-BAR Output 5
EPWM11_A 13 O ePWM-11 Output A
GPIO9 0, 4, 8, 12 I/O General-Purpose Input Output 9
EPWM5_B 1 O ePWM-5 Output B
SCIB_TX 2 O SCI-B Transmit Data
OUTPUTXBAR6 3 O Output X-BAR Output 6
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIA_RX 6 I SCI-A Receive Data
SPIA_CLK 7 119 90 75 62 56 I/O SPI-A Clock
I2CA_SCL 9 I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D0 10 O FSITX-A Primary Data Output
LINA_RX 11 I LIN-A Receive
PMBUSA_SCL 13 I/OD PMBus-A Open-Drain Bidirectional Clock
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
EQEP3_B 15 I eQEP-3 Input B

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO10 0, 4, 8, 12 I/O General-Purpose Input Output 10
EPWM6_A 1 O ePWM-6 Output A
ADCSOCBO 3 O ADC Start of Conversion B for External ADC
EQEP1_A 5 I eQEP-1 Input A
SCIB_TX 6 O SCI-B Transmit Data
SPIA_POCI 7 122 93 76 63 I/O SPI-A Peripheral Out, Controller In (POCI)
I2CA_SDA 9 I/OD I2C-A Open-Drain Bidirectional Data
FSITXA_CLK 10 O FSITX-A Output Clock
LINA_TX 11 O LIN-A Transmit
EQEP3_STROBE 13 I/O eQEP-3 Strobe
CLB_OUTPUTXBAR4 15 O CLB Output X-BAR Output 4
ADVANCE INFORMATION

General-Purpose Input Output 11 This pin also has

GPIO11 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EPWM6_B 1 O ePWM-6 Output B
MCANA_RX 2 I CAN/CAN FD Receive
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SCIB_RX 6 64 52 37 31 28 I SCI-B Receive Data
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
LINA_RX 10 I LIN-A Receive
EQEP2_A 11 I eQEP-2 Input A
SPIA_PICO 13 I/O SPI-A Peripheral In, Controller Out (PICO)
EQEP3_INDEX 15 I/O eQEP-3 Index
General-Purpose Input Output 12 This pin also has
GPIO12 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EPWM7_A 1 O ePWM-7 Output A
MCANA_RX 3 I CAN/CAN FD Receive
EQEP1_STROBE 5 I/O eQEP-1 Strobe
63 51 36 30 27
SCIB_TX 6 O SCI-B Transmit Data
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 7 I/O
Output
FSIRXA_D0 9 I FSIRX-A Primary Data Input
LINA_TX 10 O LIN-A Transmit
SPIA_CLK 11 I/O SPI-A Clock
General-Purpose Input Output 13 This pin also has
GPIO13 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EPWM7_B 1 O ePWM-7 Output B
MCANA_TX 3 O CAN/CAN FD Transmit
EQEP1_INDEX 5 I/O eQEP-1 Index
62 50 35 29 26
SCIB_RX 6 I SCI-B Receive Data
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
FSIRXA_CLK 9 I FSIRX-A Input Clock
LINA_RX 10 I LIN-A Receive
SPIA_POCI 11 I/O SPI-A Peripheral Out, Controller In (POCI)

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO14 0, 4, 8, 12 I/O General-Purpose Input Output 14
EPWM8_A 1 O ePWM-8 Output A
SCIB_TX 2 O SCI-B Transmit Data
I2CB_SDA 5 I/OD I2C-B Open-Drain Bidirectional Data
OUTPUTXBAR3 6 O Output X-BAR Output 3
PMBUSA_SDA 7 125 96 79 I/OD PMBus-A Open-Drain Bidirectional Data
SPIB_CLK 9 I/O SPI-B Clock
EQEP2_A 10 I eQEP-2 Input A
LINA_TX 11 O LIN-A Transmit
EPWM3_A 13 O ePWM-3 Output A
CLB_OUTPUTXBAR7 14 O CLB Output X-BAR Output 7

ADVANCE INFORMATION
GPIO15 0, 4, 8, 12 I/O General-Purpose Input Output 15
EPWM8_B 1 O ePWM-8 Output B
SCIB_RX 2 I SCI-B Receive Data
I2CB_SCL 5 I/OD I2C-B Open-Drain Bidirectional Clock
OUTPUTXBAR4 6 O Output X-BAR Output 4
PMBUSA_SCL 7 124 95 78 I/OD PMBus-A Open-Drain Bidirectional Clock
SPIB_PTE 9 I/O SPI-B Peripheral Transmit Enable (PTE)
EQEP2_B 10 I eQEP-2 Input B
LINA_RX 11 I LIN-A Receive
EPWM3_B 13 O ePWM-3 Output B
CLB_OUTPUTXBAR6 14 O CLB Output X-BAR Output 6
General-Purpose Input Output 16 This pin also has
GPIO16 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM9_A 5 O ePWM-9 Output A
SCIA_TX 6 O SCI-A Transmit Data
EQEP1_STROBE 9 66 54 39 33 30 I/O eQEP-1 Strobe
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
External Clock Output. This pin outputs a divided-
XCLKOUT 11 O down version of a chosen clock signal from within the
device.
EQEP2_B 13 I eQEP-2 Input B
SPIB_POCI 14 I/O SPI-B Peripheral Out, Controller In (POCI)
EQEP3_STROBE 15 I/O eQEP-3 Strobe
General-Purpose Input Output 17 This pin also has
GPIO17 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM9_B 5 O ePWM-9 Output B
67 55 40 34 31
SCIA_RX 6 I SCI-A Receive Data
EQEP1_INDEX 9 I/O eQEP-1 Index
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
MCANA_TX 11 O CAN/CAN FD Transmit
EPWM6_A 14 O ePWM-6 Output A

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO18 0, 4, 8, 12 I/O General-Purpose Input Output 18
SPIA_CLK 1 I/O SPI-A Clock
SCIB_TX 2 O SCI-B Transmit Data
MCANB_RX 3 I CAN/CAN FD Receive
EPWM6_A 5 O ePWM-6 Output A
I2CA_SCL 6 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP2_A 9 I eQEP-2 Input A
87 68 50 41 38
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 10 I/O
Output
External Clock Output. This pin outputs a divided-
XCLKOUT 11 O down version of a chosen clock signal from within the
device.
ADVANCE INFORMATION

LINA_TX 13 O LIN-A Transmit

EQEP3_INDEX 15 I/O eQEP-3 Index
X2 ALT I/O Crystal oscillator output.
GPIO19 0, 4, 8, 12 I/O General-Purpose Input Output 19
SPIA_PTE 1 I/O SPI-A Peripheral Transmit Enable (PTE)
SCIB_RX 2 I SCI-B Receive Data
MCANB_TX 3 O CAN/CAN FD Transmit
EPWM6_B 5 O ePWM-6 Output B
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
EQEP2_B 9 I eQEP-2 Input B
88 69 51 42 39
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
CLB_OUTPUTXBAR1 11 O CLB Output X-BAR Output 1
LINA_RX 13 I LIN-A Receive
Crystal oscillator input or single-ended clock input. The
device initialization software must configure this pin
before the crystal oscillator is enabled. To use this
X1 ALT I/O
oscillator, a quartz crystal circuit must be connected
to X1 and X2. This pin can also be used to feed a
single-ended 3.3-V level clock.
General-Purpose Input Output 20 This pin also has
GPIO20 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EQEP1_A 1 I eQEP-1 Input A
EPWM12_A 5 O ePWM-12 Output A
SPIB_PICO 6 60 48 33 27 24 I/O SPI-B Peripheral In, Controller Out (PICO)
MCANA_TX 9 O CAN/CAN FD Transmit
ADCE_EXTMUXSEL0 10 O ADCE external mux selection pin for position 0
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
SCIC_TX 15 O SCI-C Transmit Data
General-Purpose Input Output 21 This pin also has
GPIO21 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EQEP1_B 1 I eQEP-1 Input B
EPWM12_B 5 O ePWM-12 Output B
SPIB_POCI 6 61 49 34 28 25 I/O SPI-B Peripheral Out, Controller In (POCI)
MCANA_RX 9 I CAN/CAN FD Receive
ADCE_EXTMUXSEL1 10 O ADCE external mux selection pin for position 1
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
SCIC_RX 15 I SCI-C Receive Data

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO22 0, 4, 8, 12 I/O General-Purpose Input Output 22
EQEP1_STROBE 1 I/O eQEP-1 Strobe
SCIB_TX 3 O SCI-B Transmit Data
SPIB_CLK 6 I/O SPI-B Clock
104 83 67 56 51
LINA_TX 9, 11 O LIN-A Transmit
CLB_OUTPUTXBAR1 10 O CLB Output X-BAR Output 1
EPWM4_A 14 O ePWM-4 Output A
EQEP3_A 15 I eQEP-3 Input A
GPIO23 0, 4, 8, 12 I/O General-Purpose Input Output 23
EQEP1_INDEX 1 I/O eQEP-1 Index
SCIB_RX 3 I SCI-B Receive Data

ADVANCE INFORMATION
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
LINA_RX 9, 11 102 81 65 54 49 I LIN-A Receive
CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3
EPWM12_A 13 O ePWM-12 Output A
EPWM4_B 14 O ePWM-4 Output B
USB0DM ALT O USB-0 PHY differential data
General-Purpose Input Output 24 This pin also has
GPIO24 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
OUTPUTXBAR1 1 O Output X-BAR Output 1
EQEP2_A 2 I eQEP-2 Input A
SPIA_PTE 3 I/O SPI-A Peripheral Transmit Enable (PTE)
EPWM8_A 5 O ePWM-8 Output A
68 56 41 35 32
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
LINA_TX 9 O LIN-A Transmit
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
SCIA_TX 11 O SCI-A Transmit Data
Error Status Output. This signal requires an external
ERRORSTS 13 O
pulldown.
EPWM9_A 14 O ePWM-9 Output A
GPIO25 0, 4, 8, 12 I/O General-Purpose Input Output 25
OUTPUTXBAR2 1 O Output X-BAR Output 2
EQEP2_B 2 I eQEP-2 Input B
EQEP1_A 5 I eQEP-1 Input A
SPIB_POCI 6 69 57 42 I/O SPI-B Peripheral Out, Controller In (POCI)
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
SCIA_RX 11 I SCI-A Receive Data
EQEP3_A 13 I eQEP-3 Input A
GPIO26 0, 4, 8, 12 I/O General-Purpose Input Output 26
OUTPUTXBAR3 1, 5 O Output X-BAR Output 3
EQEP2_INDEX 2 I/O eQEP-2 Index
SPIB_CLK 6 I/O SPI-B Clock
FSITXA_D0 9 70 58 43 O FSITX-A Primary Data Output
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 10 I/O
Output
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
EQEP3_B 13 I eQEP-3 Input B

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO27 0, 4, 8, 12 I/O General-Purpose Input Output 27
OUTPUTXBAR4 1, 5 O Output X-BAR Output 4
EQEP2_STROBE 2 I/O eQEP-2 Strobe
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
71 59 44
FSITXA_CLK 9 O FSITX-A Output Clock
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP3_STROBE 13 I/O eQEP-3 Strobe
General-Purpose Input Output 28 This pin also has
GPIO28 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
SCIA_RX 1 I SCI-A Receive Data
ADVANCE INFORMATION

EPWM7_A 3 O ePWM-7 Output A

OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 2 1 4 2 3 I eQEP-1 Input A
EQEP2_STROBE 9 I/O eQEP-2 Strobe
LINA_TX 10 O LIN-A Transmit
SPIB_CLK 11 I/O SPI-B Clock
Error Status Output. This signal requires an external
ERRORSTS 13 O
pulldown.
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
GPIO29 0, 4, 8, 12 I/O General-Purpose Input Output 29
SCIA_TX 1 O SCI-A Transmit Data
EPWM7_B 3 O ePWM-7 Output B
OUTPUTXBAR6 5 O Output X-BAR Output 6
EQEP1_B 6 I eQEP-1 Input B
EQEP2_INDEX 9 I/O eQEP-2 Index
1 100 3 1 2
LINA_RX 10 I LIN-A Receive
SPIB_PTE 11 I/O SPI-B Peripheral Transmit Enable (PTE)
Error Status Output. This signal requires an external
ERRORSTS 13 O
pulldown.
I2CB_SCL 14 I/OD I2C-B Open-Drain Bidirectional Clock
AUXCLKIN ALT I Auxilary Clock Input
GPIO30 0, 4, 8, 12 I/O General-Purpose Input Output 30
SPIB_PICO 3 I/O SPI-B Peripheral In, Controller Out (PICO)
OUTPUTXBAR7 5 O Output X-BAR Output 7
EQEP1_STROBE 6 I/O eQEP-1 Strobe
127 98 1
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANA_RX 10 I CAN/CAN FD Receive
EPWM1_A 11 O ePWM-1 Output A
EQEP3_INDEX 13 I/O eQEP-3 Index
GPIO31 0, 4, 8, 12 I/O General-Purpose Input Output 31
SPIB_POCI 3 I/O SPI-B Peripheral Out, Controller In (POCI)
OUTPUTXBAR8 5 O Output X-BAR Output 8
EQEP1_INDEX 6 128 99 2 I/O eQEP-1 Index
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
MCANA_TX 10 O CAN/CAN FD Transmit
EPWM1_B 11 O ePWM-1 Output B

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO32 0, 4, 8, 12 I/O General-Purpose Input Output 32
I2CA_SDA 1 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_INDEX 2 I/O eQEP-1 Index
SPIB_CLK 3 I/O SPI-B Clock
EPWM8_B 5 O ePWM-8 Output B
79 64 49 40 37
LINA_TX 6 O LIN-A Transmit
FSIRXA_D0 9 I FSIRX-A Primary Data Input
MCANB_TX 10 O CAN/CAN FD Transmit
PMBUSA_SDA 11 I/OD PMBus-A Open-Drain Bidirectional Data
ADCSOCBO 13 O ADC Start of Conversion B for External ADC
General-Purpose Input Output 33 This pin also has

ADVANCE INFORMATION
GPIO33 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
SPIB_PTE 3 I/O SPI-B Peripheral Transmit Enable (PTE)
OUTPUTXBAR4 5 O Output X-BAR Output 4
LINA_RX 6 65 53 38 32 29 I LIN-A Receive
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANB_RX 10 I CAN/CAN FD Receive
EQEP2_B 11 I eQEP-2 Input B
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
SCIC_RX 15 I SCI-C Receive Data
GPIO34 0, 4, 8, 12 I/O General-Purpose Input Output 34
OUTPUTXBAR1 1 O Output X-BAR Output 1
123 94 77
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data
GPIO35 0, 4, 8, 12 I/O General-Purpose Input Output 35
SCIA_RX 1 I SCI-A Receive Data
SPIA_POCI 2 I/O SPI-A Peripheral Out, Controller In (POCI)
I2CA_SDA 3 I/OD I2C-A Open-Drain Bidirectional Data
MCANB_RX 5 I CAN/CAN FD Receive
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
LINA_RX 7 I LIN-A Receive
78 63 48 39 36
EQEP1_A 9 I eQEP-1 Input A
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 10 I/O
Output
EPWM5_B 11 O ePWM-5 Output B
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled by
TDI 15 I default. The internal pullup should be enabled or an
external pullup added on the board if this pin is used
as JTAG TDI to avoid a floating input.

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO37 0, 4, 8, 12 I/O General-Purpose Input Output 37
OUTPUTXBAR2 1 O Output X-BAR Output 2
SPIA_PTE 2 I/O SPI-A Peripheral Transmit Enable (PTE)
I2CA_SCL 3 I/OD I2C-A Open-Drain Bidirectional Clock
SCIA_TX 5 O SCI-A Transmit Data
MCANB_TX 6 O CAN/CAN FD Transmit
LINA_TX 7 O LIN-A Transmit
EQEP1_B 9 76 61 46 37 34 I eQEP-1 Input B
PMBUSA_ALERT 10 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
EPWM5_A 11 O ePWM-5 Output A
JTAG Test Data Output (TDO) - TDO is the default
ADVANCE INFORMATION

mux selection for the pin. The internal pullup is

disabled by default. The TDO function will be in a tri-
TDO 15 O state condition when there is no JTAG activity, leaving
this pin floating; the internal pullup should be enabled
or an external pullup added on the board to avoid a
floating GPIO input.
GPIO40 0, 4, 8, 12 I/O General-Purpose Input Output 40
SPIB_PICO 1 I/O SPI-B Peripheral In, Controller Out (PICO)
EPWM2_B 5 O ePWM-2 Output B
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data
FSIRXA_D0 7 I FSIRX-A Primary Data Input
101 80 64 53 48
SCIB_TX 9 O SCI-B Transmit Data
EQEP1_A 10 I eQEP-1 Input A
LINA_TX 11 O LIN-A Transmit
CLB_OUTPUTXBAR4 14 O CLB Output X-BAR Output 4
EQEP3_STROBE 15 I/O eQEP-3 Strobe
GPIO41 0, 4, 8, 12 I/O General-Purpose Input Output 41
EPWM7_A 1 O ePWM-7 Output A
EPWM2_A 5 O ePWM-2 Output A
PMBUSA_SCL 6 I/OD PMBus-A Open-Drain Bidirectional Clock
FSIRXA_D1 7 I FSIRX-A Optional Additional Data Input
SCIB_RX 9 103 82 66 55 50 I SCI-B Receive Data
EQEP1_B 10 I eQEP-1 Input B
LINA_RX 11 I LIN-A Receive
EPWM12_B 13 O ePWM-12 Output B
SPIB_POCI 14 I/O SPI-B Peripheral Out, Controller In (POCI)
USB0DP ALT O USB-0 PHY differential data
GPIO42 0, 4, 8, 12 I/O General-Purpose Input Output 42
LINA_RX 2 I LIN-A Receive
OUTPUTXBAR5 3 O Output X-BAR Output 5
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 5 I/O
94 57 Output
I2CA_SDA 6 I/OD I2C-A Open-Drain Bidirectional Data
SCIC_RX 7 I SCI-C Receive Data
EQEP1_STROBE 10 I/O eQEP-1 Strobe
CLB_OUTPUTXBAR3 11 O CLB Output X-BAR Output 3

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO43 0, 4, 8, 12 I/O General-Purpose Input Output 43
OUTPUTXBAR6 3 O Output X-BAR Output 6
PMBUSA_ALERT 5, 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I2CA_SCL 6 91 54 I/OD I2C-A Open-Drain Bidirectional Clock
SCIC_TX 7 O SCI-C Transmit Data
EQEP1_INDEX 10 I/O eQEP-1 Index
CLB_OUTPUTXBAR4 11 O CLB Output X-BAR Output 4
GPIO44 0, 4, 8, 12 I/O General-Purpose Input Output 44
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_A 5 I eQEP-1 Input A
PMBUSA_SDA 6 I/OD PMBus-A Open-Drain Bidirectional Data

ADVANCE INFORMATION
FSITXA_CLK 7 O FSITX-A Output Clock
106 85 69
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 9 I/O
Output
CLB_OUTPUTXBAR3 10 O CLB Output X-BAR Output 3
FSIRXA_D0 11 I FSIRX-A Primary Data Input
LINA_TX 14 O LIN-A Transmit
GPIO45 0, 4, 8, 12 I/O General-Purpose Input Output 45
OUTPUTXBAR8 3 O Output X-BAR Output 8
FSITXA_D0 7 110 73 O FSITX-A Primary Data Output
PMBUSA_ALERT 9 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
CLB_OUTPUTXBAR4 10 O CLB Output X-BAR Output 4
GPIO46 0, 4, 8, 12 I/O General-Purpose Input Output 46
LINA_TX 3 O LIN-A Transmit
MCANA_TX 5 4 6 O CAN/CAN FD Transmit
FSITXA_D1 7 O FSITX-A Optional Additional Data Output
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO47 0, 4, 8, 12 I/O General-Purpose Input Output 47
LINA_RX 3 I LIN-A Receive
MCANA_RX 5 8 6 I CAN/CAN FD Receive
CLB_OUTPUTXBAR2 7 O CLB Output X-BAR Output 2
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO48 0, 4, 8, 12 I/O General-Purpose Input Output 48
OUTPUTXBAR3 1 O Output X-BAR Output 3
MCANA_TX 5 11 7 O CAN/CAN FD Transmit
SCIA_TX 6 O SCI-A Transmit Data
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO49 0, 4, 8, 12 I/O General-Purpose Input Output 49
OUTPUTXBAR4 1 O Output X-BAR Output 4
MCANA_RX 5 I CAN/CAN FD Receive
12 8
SCIA_RX 6 I SCI-A Receive Data
LINA_RX 9 I LIN-A Receive
FSITXA_D0 14 O FSITX-A Primary Data Output
GPIO50 0, 4, 8, 12 I/O General-Purpose Input Output 50
EQEP1_A 1 I eQEP-1 Input A
MCANA_TX 5 O CAN/CAN FD Transmit
13 9
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
I2CB_SDA 9 I/OD I2C-B Open-Drain Bidirectional Data
FSITXA_D1 14 O FSITX-A Optional Additional Data Output

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO51 0, 4, 8, 12 I/O General-Purpose Input Output 51
EQEP1_B 1 I eQEP-1 Input B
MCANA_RX 5 I CAN/CAN FD Receive
14 10
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
I2CB_SCL 9 I/OD I2C-B Open-Drain Bidirectional Clock
FSITXA_CLK 14 O FSITX-A Output Clock
GPIO52 0, 4, 8, 12 I/O General-Purpose Input Output 52
EQEP1_STROBE 1 I/O eQEP-1 Strobe
CLB_OUTPUTXBAR5 5 O CLB Output X-BAR Output 5
15 11
SPIB_CLK 6 I/O SPI-B Clock
SYNCOUT 9 O External ePWM Synchronization Pulse
ADVANCE INFORMATION

FSIRXA_D0 14 I FSIRX-A Primary Data Input

GPIO53 0, 4, 8, 12 I/O General-Purpose Input Output 53
EQEP1_INDEX 1 I/O eQEP-1 Index
CLB_OUTPUTXBAR6 5 O CLB Output X-BAR Output 6
SPIB_PTE 6 16 12 I/O SPI-B Peripheral Transmit Enable (PTE)
ADCSOCAO 9 O ADC Start of Conversion A for External ADC
MCANB_RX 10 I CAN/CAN FD Receive
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input
GPIO54 0, 4, 8, 12 I/O General-Purpose Input Output 54
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
EQEP2_A 5 I eQEP-2 Input A
OUTPUTXBAR2 6 17 13 O Output X-BAR Output 2
ADCSOCBO 9 O ADC Start of Conversion B for External ADC
LINA_TX 10 O LIN-A Transmit
FSIRXA_CLK 14 I FSIRX-A Input Clock
GPIO55 0, 4, 8, 12 I/O General-Purpose Input Output 55
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
EQEP2_B 5 I eQEP-2 Input B
OUTPUTXBAR3 6 51 43 O Output X-BAR Output 3
Error Status Output. This signal requires an external
ERRORSTS 9 O
pulldown.
LINA_RX 10 I LIN-A Receive
GPIO56 0, 4, 8, 12 I/O General-Purpose Input Output 56
SPIA_CLK 1 I/O SPI-A Clock
CLB_OUTPUTXBAR7 2 O CLB Output X-BAR Output 7
MCANA_TX 3 O CAN/CAN FD Transmit
EQEP2_STROBE 5 I/O eQEP-2 Strobe
80 65
SCIB_TX 6 O SCI-B Transmit Data
SPIB_PICO 9 I/O SPI-B Peripheral In, Controller Out (PICO)
I2CA_SDA 10 I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_A 11 I eQEP-1 Input A
FSIRXA_D1 14 I FSIRX-A Optional Additional Data Input

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO57 0, 4, 8, 12 I/O General-Purpose Input Output 57
SPIA_PTE 1 I/O SPI-A Peripheral Transmit Enable (PTE)
CLB_OUTPUTXBAR8 2 O CLB Output X-BAR Output 8
MCANA_RX 3 I CAN/CAN FD Receive
EQEP2_INDEX 5 I/O eQEP-2 Index
81 66
SCIB_RX 6 I SCI-B Receive Data
SPIB_POCI 9 I/O SPI-B Peripheral Out, Controller In (POCI)
I2CA_SCL 10 I/OD I2C-A Open-Drain Bidirectional Clock
EQEP1_B 11 I eQEP-1 Input B
FSIRXA_CLK 14 I FSIRX-A Input Clock
GPIO58 0, 4, 8, 12 I/O General-Purpose Input Output 58

ADVANCE INFORMATION
OUTPUTXBAR1 5 O Output X-BAR Output 1
SPIB_CLK 6 I/O SPI-B Clock
LINA_TX 9 82 67 O LIN-A Transmit
MCANB_TX 10 O CAN/CAN FD Transmit
EQEP1_STROBE 11 I/O eQEP-1 Strobe
FSIRXA_D0 14 I FSIRX-A Primary Data Input
GPIO59 0, 4, 8, 12 I/O General-Purpose Input Output 59
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIB_PTE 6 I/O SPI-B Peripheral Transmit Enable (PTE)
121 92
LINA_RX 9 I LIN-A Receive
MCANB_RX 10 I CAN/CAN FD Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
GPIO60 0, 4, 8, 12 I/O General-Purpose Input Output 60
EPWM12_B 1 O ePWM-12 Output B
MCANA_TX 3 52 44 O CAN/CAN FD Transmit
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
GPIO61 0, 4, 8, 12 I/O General-Purpose Input Output 61
MCANA_RX 3 I CAN/CAN FD Receive
OUTPUTXBAR4 5 120 91 O Output X-BAR Output 4
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
MCANB_RX 14 I CAN/CAN FD Receive
GPIO62 0, 4, 8, 12 I/O General-Purpose Input Output 62
EPWM10_A 1 O ePWM-10 Output A
OUTPUTXBAR3 2 O Output X-BAR Output 3
58 46 31
MCANA_TX 5 O CAN/CAN FD Transmit
SCIA_TX 6 O SCI-A Transmit Data
PMBUSA_SDA 9 I/OD PMBus-A Open-Drain Bidirectional Data
GPIO63 0, 4, 8, 12 I/O General-Purpose Input Output 63
EPWM10_B 1 O ePWM-10 Output B
OUTPUTXBAR4 2 O Output X-BAR Output 4
59 47 32
MCANA_RX 5 I CAN/CAN FD Receive
SCIA_RX 6 I SCI-A Receive Data
LINA_RX 9 I LIN-A Receive

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO64 0, 4, 8, 12 I/O General-Purpose Input Output 64
SCIA_RX 1 I SCI-A Receive Data
EPWM11_A 2 O ePWM-11 Output A
EPWM7_A 3 O ePWM-7 Output A
OUTPUTXBAR5 5 O Output X-BAR Output 5
EQEP1_A 6 I eQEP-1 Input A
56
EQEP2_STROBE 9 I/O eQEP-2 Strobe
LINA_TX 10 O LIN-A Transmit
SPIB_CLK 11 I/O SPI-B Clock
Error Status Output. This signal requires an external
ERRORSTS 13 O
pulldown.
ADVANCE INFORMATION

I2CB_SDA 14 I/OD I2C-B Open-Drain Bidirectional Data

GPIO65 0, 4, 8, 12 I/O General-Purpose Input Output 65
EQEP1_A 1 I eQEP-1 Input A
EPWM11_B 2 O ePWM-11 Output B
57
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
MCANA_TX 9 O CAN/CAN FD Transmit
I2CA_SCL 11 I/OD I2C-A Open-Drain Bidirectional Clock
GPIO66 0, 4, 8, 12 I/O General-Purpose Input Output 66
EQEP1_B 1 I eQEP-1 Input B
EPWM12_A 2 O ePWM-12 Output A
9
SPIB_POCI 6 I/O SPI-B Peripheral Out, Controller In (POCI)
MCANA_RX 9 I CAN/CAN FD Receive
I2CA_SDA 11 I/OD I2C-A Open-Drain Bidirectional Data
GPIO67 0, 4, 8, 12 I/O General-Purpose Input Output 67
EPWM7_B 1 O ePWM-7 Output B
EPWM12_B 2 O ePWM-12 Output B
MCANA_TX 3 O CAN/CAN FD Transmit
EQEP1_INDEX 5 I/O eQEP-1 Index
SCIB_RX 6 10 I SCI-B Receive Data
PMBUSA_ALERT 7 I/OD PMBus-A Open-Drain Bidirectional Alert Signal
FSIRXA_CLK 9 I FSIRX-A Input Clock
LINA_RX 10 I LIN-A Receive
SPIA_POCI 11 I/O SPI-A Peripheral Out, Controller In (POCI)
SCIC_RX 15 I SCI-C Receive Data
GPIO68 0, 4, 8, 12 I/O General-Purpose Input Output 68
EPWM7_A 1 O ePWM-7 Output A
EPWM3_A 2 O ePWM-3 Output A
MCANA_RX 3 I CAN/CAN FD Receive
EQEP1_STROBE 5 I/O eQEP-1 Strobe
SCIB_TX 6 O SCI-B Transmit Data
72
PMBus-A Control Signal - Target Input/Controller
PMBUSA_CTL 7 I/O
Output
FSIRXA_D0 9 I FSIRX-A Primary Data Input
LINA_TX 10 O LIN-A Transmit
SPIA_CLK 11 I/O SPI-A Clock
SCIC_TX 15 O SCI-C Transmit Data

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO69 0, 4, 8, 12 I/O General-Purpose Input Output 69
EPWM6_B 1 O ePWM-6 Output B
EPWM3_B 2 O ePWM-3 Output B
OUTPUTXBAR7 3 O Output X-BAR Output 7
EQEP1_B 5 I eQEP-1 Input B
SCIB_RX 6 I SCI-B Receive Data
73
SPIA_PTE 7 I/O SPI-A Peripheral Transmit Enable (PTE)
FSIRXA_D1 9 I FSIRX-A Optional Additional Data Input
LINA_RX 10 I LIN-A Receive
EQEP2_A 11 I eQEP-2 Input A
SPIA_PICO 13 I/O SPI-A Peripheral In, Controller Out (PICO)

ADVANCE INFORMATION
EQEP3_INDEX 15 I/O eQEP-3 Index
GPIO70 0, 4, 8, 12 I/O General-Purpose Input Output 70
I2CA_SCL 1 I/OD I2C-A Open-Drain Bidirectional Clock
SPIB_PTE 3 I/O SPI-B Peripheral Transmit Enable (PTE)
OUTPUTXBAR4 5 O Output X-BAR Output 4
LINA_RX 6 I LIN-A Receive
74
FSIRXA_CLK 9 I FSIRX-A Input Clock
MCANA_RX 10 I CAN/CAN FD Receive
EQEP2_B 11 I eQEP-2 Input B
ADCSOCAO 13 O ADC Start of Conversion A for External ADC
EQEP3_A 15 I eQEP-3 Input A
GPIO71 0, 4, 8, 12 I/O General-Purpose Input Output 71
SPIA_PICO 1 I/O SPI-A Peripheral In, Controller Out (PICO)
EPWM4_B 2 O ePWM-4 Output B
OUTPUTXBAR7 3 O Output X-BAR Output 7
EPWM9_A 5 O ePWM-9 Output A
SCIA_TX 6 O SCI-A Transmit Data
EQEP1_STROBE 9 83 I/O eQEP-1 Strobe
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
External Clock Output. This pin outputs a divided-
XCLKOUT 11 O down version of a chosen clock signal from within the
device.
EQEP2_INDEX 13 I/O eQEP-2 Index
SPIB_POCI 14 I/O SPI-B Peripheral Out, Controller In (POCI)
EQEP3_STROBE 15 I/O eQEP-3 Strobe
GPIO72 0, 4, 8, 12 I/O General-Purpose Input Output 72
SPIA_POCI 1 I/O SPI-A Peripheral Out, Controller In (POCI)
EPWM5_A 2 O ePWM-5 Output A
OUTPUTXBAR8 3 O Output X-BAR Output 8
EPWM9_B 5 O ePWM-9 Output B
SCIA_RX 6 84 I SCI-A Receive Data
EQEP1_INDEX 9 I/O eQEP-1 Index
PMBUSA_SDA 10 I/OD PMBus-A Open-Drain Bidirectional Data
MCANA_TX 11 O CAN/CAN FD Transmit
EPWM6_A 14 O ePWM-6 Output A
EQEP3_B 15 I eQEP-3 Input B

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO73 0, 4, 8, 12 I/O General-Purpose Input Output 73
OUTPUTXBAR1 1 O Output X-BAR Output 1
EPWM5_B 2 O ePWM-5 Output B
SPIA_PTE 3 I/O SPI-A Peripheral Transmit Enable (PTE)
EPWM8_A 5 O ePWM-8 Output A
SPIB_PICO 6 I/O SPI-B Peripheral In, Controller Out (PICO)
85
LINA_TX 9 O LIN-A Transmit
PMBUSA_SCL 10 I/OD PMBus-A Open-Drain Bidirectional Clock
SCIA_TX 11 O SCI-A Transmit Data
Error Status Output. This signal requires an external
ERRORSTS 13 O
pulldown.
ADVANCE INFORMATION

EPWM9_A 14 O ePWM-9 Output A

GPIO74 0, 4, 8, 12 I/O General-Purpose Input Output 74
EPWM2_B 1 O ePWM-2 Output B
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
86
MCANA_TX 5 O CAN/CAN FD Transmit
SPIA_POCI 6 I/O SPI-A Peripheral Out, Controller In (POCI)
EQEP1_B 11 I eQEP-1 Input B
GPIO75 0, 4, 8, 12 I/O General-Purpose Input Output 75
EPWM1_B 1 O ePWM-1 Output B
LINA_RX 3 I LIN-A Receive
EPWM6_A 5 111 O ePWM-6 Output A
SPIA_CLK 6 I/O SPI-A Clock
EQEP1_STROBE 11 I/O eQEP-1 Strobe
SCIC_RX 14 I SCI-C Receive Data
GPIO76 0, 4, 8, 12 I/O General-Purpose Input Output 76
EPWM4_A 1 O ePWM-4 Output A
OUTPUTXBAR2 5 O Output X-BAR Output 2
112
SPIA_PTE 6 I/O SPI-A Peripheral Transmit Enable (PTE)
MCANA_RX 10 I CAN/CAN FD Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
GPIO77 0, 4, 8, 12 I/O General-Purpose Input Output 77
EPWM1_A 1 O ePWM-1 Output A
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIA_PICO 6 113 I/O SPI-A Peripheral In, Controller Out (PICO)
MCANA_TX 10 O CAN/CAN FD Transmit
EQEP1_A 11 I eQEP-1 Input A
SCIC_TX 14 O SCI-C Transmit Data
GPIO78 0, 4, 8, 12 I/O General-Purpose Input Output 78
EPWM8_A 2 O ePWM-8 Output A
EPWM3_A 3 O ePWM-3 Output A
114
OUTPUTXBAR1 5 O Output X-BAR Output 1
EPWM2_B 6 O ePWM-2 Output B
FSITXA_CLK 9 O FSITX-A Output Clock

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
GPIO79 0, 4, 8, 12 I/O General-Purpose Input Output 79
EPWM8_B 2 O ePWM-8 Output B
EPWM3_B 3 O ePWM-3 Output B
MCANA_RX 5 115 I CAN/CAN FD Receive
EPWM2_A 6 O ePWM-2 Output A
I2CA_SDA 7 I/OD I2C-A Open-Drain Bidirectional Data
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock
GPIO80 0, 4, 8, 12 I/O General-Purpose Input Output 80
EPWM1_A 1 O ePWM-1 Output A
OUTPUTXBAR7 3 O Output X-BAR Output 7
SCIA_RX 5 I SCI-A Receive Data

ADVANCE INFORMATION
I2CB_SDA 6 I/OD I2C-B Open-Drain Bidirectional Data
SPIA_PTE 7 116 I/O SPI-A Peripheral Transmit Enable (PTE)
FSITXA_D0 9 O FSITX-A Primary Data Output
MCANA_RX 10 I CAN/CAN FD Receive
CLB_OUTPUTXBAR8 11 O CLB Output X-BAR Output 8
EQEP1_INDEX 13 I/O eQEP-1 Index
EPWM3_A 15 O ePWM-3 Output A
GPIO81 0, 4, 8, 12 I/O General-Purpose Input Output 81
EPWM1_B 1 O ePWM-1 Output B
OUTPUTXBAR6 2 O Output X-BAR Output 6
SCIC_RX 3 I SCI-C Receive Data
SPIB_CLK 5 117 I/O SPI-B Clock
I2CB_SCL 6 I/OD I2C-B Open-Drain Bidirectional Clock
FSITXA_D1 9 O FSITX-A Optional Additional Data Output
MCANA_TX 10 O CAN/CAN FD Transmit
EQEP3_INDEX 11 I/O eQEP-3 Index
GPIO211 0, 4, 8, 12 I/O General-Purpose Input Output 211
EPWM10_A 1 43 O ePWM-10 Output A
EQEP3_A 5 I eQEP-3 Input A
GPIO212 0, 4, 8, 12 I/O General-Purpose Input Output 212
EPWM10_B 1 44 O ePWM-10 Output B
EQEP3_B 5 I eQEP-3 Input B
GPIO213 0, 4, 8, 12 I/O General-Purpose Input Output 213
EPWM11_A 1 45 O ePWM-11 Output A
EQEP3_STROBE 5 I/O eQEP-3 Strobe
GPIO214 0, 4, 8, 12 I/O General-Purpose Input Output 214
EPWM11_B 1 46 O ePWM-11 Output B
EQEP3_INDEX 5 I/O eQEP-3 Index
GPIO215 0, 4, 8, 12 I/O General-Purpose Input Output 215
EPWM7_B 1 47 O ePWM-7 Output B
EQEP2_A 5 I eQEP-2 Input A

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
General-Purpose Input Output 224 This pin also has
GPIO224 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EPWM11_B 1 O ePWM-11 Output B
OUTPUTXBAR3 5 O Output X-BAR Output 3
SPIA_PICO 6 I/O SPI-A Peripheral In, Controller Out (PICO)
21 17 13 9 7
EPWM1_A 9 O ePWM-1 Output A
MCANA_TX 10 O CAN/CAN FD Transmit
EQEP1_A 11 I eQEP-1 Input A
ADCE_EXTMUXSEL3 13 O ADCE external mux selection pin for position 3
SCIC_TX 14 O SCI-C Transmit Data
General-Purpose Input Output 226 This pin also has
ADVANCE INFORMATION

GPIO226 0, 4, 8, 12 I/O analog functions which are described in the ANALOG

section of this table.
EPWM10_B 1 O ePWM-10 Output B
LINA_RX 3 I LIN-A Receive
EPWM6_A 5 O ePWM-6 Output A
19 15 11 7
SPIA_CLK 6 I/O SPI-A Clock
EPWM1_B 9 O ePWM-1 Output B
EQEP1_STROBE 11 I/O eQEP-1 Strobe
ADCE_EXTMUXSEL1 13 O ADCE external mux selection pin for position 1
SCIC_RX 14 I SCI-C Receive Data
General-Purpose Input Output 227 This pin also has
GPIO227 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
I2CB_SCL 1 I/OD I2C-B Open-Drain Bidirectional Clock
48 38 28 24 22
EPWM3_A 3 O ePWM-3 Output A
OUTPUTXBAR1 5 O Output X-BAR Output 1
EPWM2_B 6 O ePWM-2 Output B
General-Purpose Input Output 228 This pin also has
GPIO228 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EPWM10_A 1 O ePWM-10 Output A
ADCSOCAO 3 O ADC Start of Conversion A for External ADC
MCANA_TX 5 18 14 10 6 O CAN/CAN FD Transmit
SPIA_POCI 6 I/O SPI-A Peripheral Out, Controller In (POCI)
EPWM2_B 9 O ePWM-2 Output B
EQEP1_B 11 I eQEP-1 Input B
ADCE_EXTMUXSEL0 13 O ADCE external mux selection pin for position 0
General-Purpose Input Output 230 This pin also has
GPIO230 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
I2CB_SDA 1 I/OD I2C-B Open-Drain Bidirectional Data
EPWM3_B 3 O ePWM-3 Output B
50 40 29 25 23
MCANA_RX 5 I CAN/CAN FD Receive
EPWM2_A 6 O ePWM-2 Output A
I2CA_SDA 7 I/OD I2C-A Open-Drain Bidirectional Data
PMBUSA_SCL 9 I/OD PMBus-A Open-Drain Bidirectional Clock

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Table 5-1. Pin Attributes (continued)

128 100 64 PIN
SIGNAL NAME MUX POSITION 80 PNA 56 RSH DESCRIPTION
PDT PZ PM TYPE
General-Purpose Input Output 242 This pin also has
GPIO242 0, 4, 8, 12 I/O analog functions which are described in the ANALOG
section of this table.
EPWM11_A 1 O ePWM-11 Output A
OUTPUTXBAR2 5 O Output X-BAR Output 2
SPIA_PTE 6 20 16 12 8 6 I/O SPI-A Peripheral Transmit Enable (PTE)
EPWM4_A 9 O ePWM-4 Output A
MCANA_RX 10 I CAN/CAN FD Receive
EQEP1_INDEX 11 I/O eQEP-1 Index
ADCE_EXTMUXSEL2 13 O ADCE external mux selection pin for position 2
General-Purpose Input Output 247 This pin also has
GPIO247 0, 4, 8, 12 I/O analog functions which are described in the ANALOG

ADVANCE INFORMATION
42 section of this table.
EPWM12_B 1 O ePWM-12 Output B
GPIO253 0, 4, 8, 12 I/O General-Purpose Input Output 253
41
EPWM12_A 1 O ePWM-12 Output A
TEST, JTAG, AND RESET
TCK 75 60 45 36 33 I JTAG test clock with internal pullup.
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK. This device does not have a
TMS 77 62 47 38 35 I/O TRSTn pin. An external pullup resistor (recommended
2.2 kΩ) on the TMS pin to VDDIO should be placed
on the board to keep JTAG in reset during normal
operation.
Device Reset (in) and Watchdog Reset (out). During
a power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by the
MCU when a watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for the watchdog
reset duration of 512 OSCCLK cycles. A resistor
between 2.2 kΩ and 10 kΩ should be placed between
XRSn 3 2 5 3 4 I/OD
XRSn and VDDIO. If a capacitor is placed between
XRSn and VSS for noise filtering, it should be 100
nF or smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within 512
OSCCLK cycles when the watchdog reset is asserted.
This pin is an open-drain output with an internal pullup.
If this pin is driven by an external device, it should be
done using an open-drain device.
POWER AND GROUND
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD pin with
6, 54, 4, 71, 8, 53, 4, 44, 5, 41,
VDD a minimum total capacitance of approximately 10 µF.
90, 108 87 71 59 53
It is also recommended that all VDD pins be externally
connected to each other when internal VREG is used.
3.3-V Analog Power Pins. Place a minimum 2.2-µF
VDDA 41 34 26 22 20
decoupling capacitor on each pin.
5, 55, 3, 70, 7, 52, 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
VDDIO 43, 60 40, 54
89, 109 88 72 decoupling capacitor on each pin.
Internal voltage regulator enable with internal
VREGENZ 93 73 56 46 42 I pulldown. Tie low to VSS to enable internal VREG. Tie
high to VDDIO to use an external supply.
7, 53, 5, 45, 9, 30, 5, 26,
VSS PAD Digital Ground
92, 107 72, 86 55, 70 45, 58
VSSA 40 33 25 21 19 Analog Ground

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5.3 Signal Descriptions

5.3.1 Analog Signals
Table 5-2. Analog Signals
PIN
SIGNAL NAME DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
A0 I ADC-A Input 0 30 23 19 15 13
A1 I ADC-A Input 1 29 22 18 14 12
A2 I ADC-A Input 2 21 17 13 9 7
A3 I ADC-A Input 3 20 18 12 8 6
A4 I ADC-A Input 4 42 36 27 23 21
A5 I ADC-A Input 5 28 35 17 13 11
A6 I ADC-A Input 6 18 14 10 6
ADVANCE INFORMATION

A7 I ADC-A Input 7 37 31 23 19 17
A8 I ADC-A Input 8 39 37 24 20 18
A9 I ADC-A Input 9 48 38 28 24 22
A10 I ADC-A Input 10 50 40 29 25 23
A11 I ADC-A Input 11 27 20 16 12 10
A12 I ADC-A Input 12 35 28 22 18 16
A13 I ADC-A Input 13 33, 34 26, 27 21 17 15
A14 I ADC-A Input 14 26 19 15 11 9
A15 I ADC-A Input 15 22 14 10 8
A16 I ADC-A Input 16 2 1 4 2 3
A17 I ADC-A Input 17 60 48 33 27 24
A18 I ADC-A Input 18 61 49 34 28 25
A19 I ADC-A Input 19 62 50 35 29 26
A20 I ADC-A Input 20 63 51 36 30 27
A24 I ADC-A Input 24 64 52 37 31 28
A25 I ADC-A Input 25 67 55 40 34 31
A26 I ADC-A Input 26 24
A27 I ADC-A Input 27 44
A28 I ADC-A Input 28 47
AIO208 I Analog Pin Used For Digital Input 208 23
AIO209 I Analog Pin Used For Digital Input 209 24
AIO210 I Analog Pin Used For Digital Input 210 25
AIO225 I Analog Pin Used For Digital Input 225 42 36 27 23 21
AIO226 I Analog Pin Used For Digital Input 226 43
AIO227 I Analog Pin Used For Digital Input 227 44
AIO228 I Analog Pin Used For Digital Input 228 45
AIO229 I Analog Pin Used For Digital Input 229 18
AIO231 I Analog Pin Used For Digital Input 231 30 23 19 15 13
AIO232 I Analog Pin Used For Digital Input 232 29 22 18 14 12
AIO233 I Analog Pin Used For Digital Input 233 22 14 10 8
AIO234 I Analog Pin Used For Digital Input 234 31, 32 24, 25 20 16 14
AIO235 I Analog Pin Used For Digital Input 235 33, 34 26, 27 21 17 15
AIO237 I Analog Pin Used For Digital Input 237 27 20 16 12 10
AIO238 I Analog Pin Used For Digital Input 238 35 28 22 18 16
AIO239 I Analog Pin Used For Digital Input 239 26 19 15 11 9

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Table 5-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
AIO240 I Analog Pin Used For Digital Input 240 37
AIO241 I Analog Pin Used For Digital Input 241 39 24 20 18
AIO242 I Analog Pin Used For Digital Input 242 46
AIO243 I Analog Pin Used For Digital Input 243 47
AIO244 I Analog Pin Used For Digital Input 244 28 21 17 13 11
AIO245 I Analog Pin Used For Digital Input 245 37 31 23 19 17
AIO248 I Analog Pin Used For Digital Input 248 35 29 22 18 16
AIO249 I Analog Pin Used For Digital Input 249 35
AIO251 I Analog Pin Used For Digital Input 251 36 30
AIO252 I Analog Pin Used For Digital Input 252 38 32

ADVANCE INFORMATION
AIO253 I Analog Pin Used For Digital Input 253 23
B0 I ADC-B Input 0 39 41 24 20 18
B1 I ADC-B Input 1 50 40 29 25 23
B2 I ADC-B Input 2 19 15 11 7
B3 I ADC-B Input 3 20 16 12 8 6
B4 I ADC-B Input 4 49 39 28 24 22
B5 I ADC-B Input 5 38 32
B6 I ADC-B Input 6 21 17 13 9 7
B7 I ADC-B Input 7 29 22 18 14 12
B8 I ADC-B Input 8 42 36 27 23 21
B9 I ADC-B Input 9 22 18 14 10 8
B10 I ADC-B Input 10 27 20 16 12 10
B11 I ADC-B Input 11 36 30
B12 I ADC-B Input 12 28 21 17 13 11
B13 I ADC-B Input 13 33, 34 26, 27 21 17 15
B14 I ADC-B Input 14 26 19 15 11 9
B15 I ADC-B Input 15 30 23 19 15 13
B16 I ADC-B Input 16 2 1 4 2 3
B17 I ADC-B Input 17 60 48 33 27 24
B18 I ADC-B Input 18 61 49 34 28 25
B19 I ADC-B Input 19 62 50 35 29 26
B20 I ADC-B Input 20 63 51 36 30 27
B24 I ADC-B Input 24 65 53 38 32 29
B25 I ADC-B Input 25 68 56 41 35 32
B26 I ADC-B Input 26 25
B27 I ADC-B Input 27 45
B30 I ADC-B Input 30 37 31 23 19 17
C0 I ADC-C Input 0 27 20 16 12 10
C1 I ADC-C Input 1 35 29 22 18 16
C2 I ADC-C Input 2 28 21 17 13 11
C3 I ADC-C Input 3 37 31 23 19 17
C4 I ADC-C Input 4 26 19 15 11 9
C5 I ADC-C Input 5 20 28 12 8 6
C6 I ADC-C Input 6 19 15 11 7

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Table 5-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
C7 I ADC-C Input 7 22 18 14 10 8
C8 I ADC-C Input 8 49 39 28 24 22
C9 I ADC-C Input 9 21 17 13 9 7
C10 I ADC-C Input 10 50 40 29 25 23
C11 I ADC-C Input 11 39 41 24 20 18
C13 I ADC-C Input 13 33, 34 26, 27 21 17 15
C14 I ADC-C Input 14 42 42 27 23 21
C15 I ADC-C Input 15 30 23 19 15 13
C16 I ADC-C Input 16 2 1 4 2 3
C17 I ADC-C Input 17 60 48 33 27 24
ADVANCE INFORMATION

C18 I ADC-C Input 18 61 49 34 28 25

C19 I ADC-C Input 19 62 50 35 29 26
C20 I ADC-C Input 20 63 51 36 30 27
C24 I ADC-C Input 24 66 54 39 33 30
C25 I ADC-C Input 25 23
C26 I ADC-C Input 26 43
C27 I ADC-C Input 27 46
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 22 14 10 8
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 27 20 16 12 10
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0 21 17 13 9 7
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1 27 20 16 12 10
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 18 14 10 6
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3 22 14 10 8
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4 29 22 18 14 12
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 38 32
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 22 14 10 8
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 27 20 16 12 10
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0 21 17 13 9 7
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1 27 20 16 12 10
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 18 14 10 6
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3 22 14 10 8
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4 29 22 18 14 12
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 38 32
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0 50 40 29 25 23
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1 35 28 22 18 16
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0 42 36 27 23 21
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1 35 28 22 18 16
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2 48 38 28 24 22
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 50 40, 41 29 25 23
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5 28 35 17 13 11
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0 50 40 29 25 23
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1 35 28 22 18 16
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0 42 36 27 23 21
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1 35 28 22 18 16

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Table 5-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2 48 38 28 24 22
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 50 40, 41 29 25 23
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5 28 35 17 13 11
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0 20 16 12 8 6
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1 28 21 17 13 11
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0 19 15 11 7
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1 28 21 17 13 11
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2 30 23 19 15 13
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3 20 16 12 8 6
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4 26 19 15 11 9

ADVANCE INFORMATION
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5 20 18 12 8 6
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0 20 16 12 8 6
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1 28 21 17 13 11
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0 19 15 11 7
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1 28 21 17 13 11
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2 30 23 19 15 13
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3 20 16 12 8 6
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4 26 19 15 11 9
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5 20 18 12 8 6
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 42 42 27 23 21
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1 37 31 23 19 17
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0 49 39 28 24 22
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1 37 31 23 19 17
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2 35 29 22 18 16
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3 42 42 27 23 21
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4 39 37 24 20 18
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5 36 30
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0 42 42 27 23 21
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1 37 31 23 19 17
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0 49 39 28 24 22
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1 37 31 23 19 17
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2 35 29 22 18 16
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3 42 42 27 23 21
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4 39 37 24 20 18
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5 36 30
D0 I ADC-D Input 0 64 52 37 31 28
D1 I ADC-D Input 1 65 53 38 32 29
D2 I ADC-D Input 2 66 54 39 33 30
D3 I ADC-D Input 3 67 55 40 34 31
D4 I ADC-D Input 4 68 56 41 35 32
D5 I ADC-D Input 5 23
D6 I ADC-D Input 6 24
D7 I ADC-D Input 7 25
D8 I ADC-D Input 8 43

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Table 5-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
D9 I ADC-D Input 9 44
D10 I ADC-D Input 10 45
D11 I ADC-D Input 11 29 22 18 14 12
D12 I ADC-D Input 12 37 31 23 19 17
D13 I ADC-D Input 13 33, 34 26, 27 21 17 15
D14 I ADC-D Input 14 18 14 10 6
D15 I ADC-D Input 15 38 32
D16 I ADC-D Input 16 36 30
D18 I ADC-D Input 18 46
D19 I ADC-D Input 19 47
ADVANCE INFORMATION

D20 I ADC-D Input 20 31, 32 24, 25 20 16 14

DACA_OUT O Buffered DAC-A Output. 30 23 19 15 13
DACB_OUT O Buffered DAC-B Output. 29 22 18 14 12
E0 I ADC-E Input 0 64 52 37 31 28
E1 I ADC-E Input 1 65 53 38 32 29
E2 I ADC-E Input 2 66 54 39 33 30
E3 I ADC-E Input 3 67 55 40 34 31
E4 I ADC-E Input 4 68 56 41 35 32
E5 I ADC-E Input 5 23
E6 I ADC-E Input 6 24
E7 I ADC-E Input 7 25
E8 I ADC-E Input 8 43
E9 I ADC-E Input 9 44
E10 I ADC-E Input 10 45
E11 I ADC-E Input 11 35 29 22 18 16
E12 I ADC-E Input 12 19 15 11 7
E13 I ADC-E Input 13 33, 34 26, 27 21 17 15
E14 I ADC-E Input 14 18 14 10 6
E15 I ADC-E Input 15 38 32
E16 I ADC-E Input 16 36 30
E18 I ADC-E Input 18 46
E19 I ADC-E Input 19 47
E20 I ADC-E Input 20 31, 32 24, 25 20 16 14
E30 I ADC-E Input 30 37 31 23 19 17
PGA1_INM I PGA-1 Minus 22 18 14 10 8
PGA1_INP I PGA-1 Plus 21 17 13 9 7
PGA1_OUT O PGA-1 Output 26 19 15 11 9
PGA2_INM I PGA-2 Minus 28 21 17 13 11
PGA2_INP I PGA-2 Plus 20 16 12 8 6
PGA2_OUT O PGA-2 Output 27 20 16 12 10
PGA3_INM I PGA-3 Minus 36 30 23 19 17
PGA3_INP I PGA-3 Plus 35 29 22 18 16
PGA3_OUT O PGA-3 Output 38 32 24 20 18

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Table 5-2. Analog Signals (continued)

PIN
SIGNAL NAME DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
TYPE
ADC High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by
VREFHI I the device. In either mode, place at least a 31, 32 24, 25 20 16 14
2.2-µF capacitor on this pin. This capacitor
should be placed as close to the device as
possible between the VREFHI and VREFLO
pins.
VREFLO I ADC Low Reference 33, 34 26, 27 21 17 15

ADVANCE INFORMATION

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5.3.2 Digital Signals

Table 5-3. Digital Signals
PIN 56
SIGNAL NAME DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM
TYPE RSH
ADCE_EXTMUXSEL0 O ADCE external mux selection pin for position 0 20, 228 18, 60 14, 48 10, 33 6, 27 24
ADCE_EXTMUXSEL1 O ADCE external mux selection pin for position 1 21, 226 19, 61 15, 49 11, 34 7, 28 25
ADCE_EXTMUXSEL2 O ADCE external mux selection pin for position 2 242 20 16 12 8 6
ADCE_EXTMUXSEL3 O ADCE external mux selection pin for position 3 224 21 17 13 9 7
8, 33, 53, 70, 74, 16, 18, 65, 74, 86, 6, 32,
ADCSOCAO O ADC Start of Conversion A for External ADC 12, 14, 53, 74 10, 38, 58 29
228 95 47
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32, 54 17, 79, 122 13, 64, 93 49, 76 40, 63 37
AUXCLKIN I Auxilary Clock Input 29 1 100 3 1 2
CLB_OUTPUTXBAR1 O CLB Output X-BAR Output 1 19, 22 88, 104 69, 83 51, 67 42, 56 39, 51
CLB_OUTPUTXBAR2 O CLB Output X-BAR Output 2 7, 47 8, 105 6, 84 68 57 52
CLB_OUTPUTXBAR3 O CLB Output X-BAR Output 3 23, 42, 44 94, 102, 106 81, 85 57, 65, 69 54 49
ADVANCE INFORMATION

54, 64, 73,

CLB_OUTPUTXBAR4 O CLB Output X-BAR Output 4 10, 40, 43, 45 91, 101, 110, 122 80, 93 53, 63 48
76
CLB_OUTPUTXBAR5 O CLB Output X-BAR Output 5 5, 8, 52 15, 95, 118 11, 74, 89 58, 74 47, 61 55
CLB_OUTPUTXBAR6 O CLB Output X-BAR Output 6 4, 15, 53 16, 96, 124 12, 75, 95 59, 78 48 43
CLB_OUTPUTXBAR7 O CLB Output X-BAR Output 7 1, 14, 56 80, 99, 125 65, 78, 96 62, 79 51 46
CLB_OUTPUTXBAR8 O CLB Output X-BAR Output 8 0, 6, 57, 80 81, 100, 116, 126 66, 79, 97 63, 80 52, 64 1, 47
21, 96, 100, 113, 1, 13, 59, 9, 48, 7, 43,
EPWM1_A O ePWM-1 Output A 0, 4, 30, 77, 80, 224 17, 75, 79, 98
116, 127 63 52 47
19, 99, 111, 117, 2, 11, 62, 7, 51,
EPWM1_B O ePWM-1 Output B 1, 5, 31, 75, 81, 226 15, 78, 89, 99 46, 55
118, 128 74 61
25, 50, 1, 23,
50, 98, 103, 105, 40, 77, 82, 84, 29, 61, 66,
EPWM2_A O ePWM-2 Output A 2, 6, 7, 41, 79, 230 55, 57, 45, 50,
115, 126 97 68, 80
64 52
6, 24,
3, 7, 40, 74, 78, 18, 48, 86, 97, 101, 14, 38, 76, 80, 10, 28, 60, 22, 44,
EPWM2_B O ePWM-2 Output B 49, 53,
227, 228 105, 114 84 64, 68 48, 52
57
0, 4, 14, 68, 78, 80, 48, 72, 96, 100, 114, 28, 59, 63, 24, 48, 22, 43,
EPWM3_A O ePWM-3 Output A 38, 75, 79, 96
227 116, 125 79 52 47
50, 73, 99, 115, 118, 29, 62, 74, 25, 51, 23, 46,
EPWM3_B O ePWM-3 Output B 1, 5, 15, 69, 79, 230 40, 78, 89, 95
124 78 61 55
12, 61, 67, 8, 50, 1, 6,
EPWM4_A O ePWM-4 Output A 2, 6, 22, 76, 242 20, 98, 104, 112, 126 16, 77, 83, 97
80 56, 64 45, 51
49, 54, 44, 49,
EPWM4_B O ePWM-4 Output B 3, 7, 23, 71 83, 97, 102, 105 76, 81, 84 60, 65, 68
57 52
EPWM5_A O ePWM-5 Output A 8, 37, 72 76, 84, 95 61, 74 46, 58 37, 47 34
EPWM5_B O ePWM-5 Output B 9, 35, 73 78, 85, 119 63, 90 48, 75 39, 62 36, 56
10, 17, 18, 72, 75, 19, 67, 84, 87, 111, 11, 40, 50, 7, 34,
EPWM6_A O ePWM-6 Output A 15, 55, 68, 93 31, 38
226 122 76 41, 63
EPWM6_B O ePWM-6 Output B 11, 19, 69 64, 73, 88 52, 69 37, 51 31, 42 28, 39
12, 28, 41, 64, 68, 2, 49, 56, 63, 72, 4, 28, 36, 2, 24, 3, 22,
EPWM7_A O ePWM-7 Output A 1, 39, 51, 82
236 103 66 30, 55 27, 50
EPWM7_B O ePWM-7 Output B 13, 29, 67, 215 1, 10, 47, 62 50, 100 3, 35 1, 29 2, 26
EPWM8_A O ePWM-8 Output A 14, 24, 73, 78 68, 85, 114, 125 56, 96 41, 79 35 32
EPWM8_B O ePWM-8 Output B 15, 32, 79 79, 115, 124 64, 95 49, 78 40 37
EPWM9_A O ePWM-9 Output A 16, 24, 71, 73 66, 68, 83, 85 54, 56 39, 41 33, 35 30, 32
EPWM9_B O ePWM-9 Output B 17, 72 67, 84 55 40 34 31
EPWM10_A O ePWM-10 Output A 2, 62, 211, 228 18, 43, 58, 98 14, 46, 77 10, 31, 61 6, 50 45
EPWM10_B O ePWM-10 Output B 1, 63, 212, 226 19, 44, 59, 99 15, 47, 78 11, 32, 62 7, 51 46
EPWM11_A O ePWM-11 Output A 8, 64, 213, 242 20, 45, 56, 95 16, 74 12, 58 8, 47 6
EPWM11_B O ePWM-11 Output B 4, 65, 214, 224 21, 46, 57, 96 17, 75 13, 59 9, 48 7, 43
24, 27, 22, 24,
EPWM12_A O ePWM-12 Output A 20, 23, 66, 236, 253 9, 49, 60, 102 39, 41, 48, 81 28, 33, 65
54 49
EPWM12_B O ePWM-12 Output B 21, 41, 60, 67, 247 10, 52, 61, 103 42, 44, 49, 82 34, 66 28, 55 25, 50
6, 10, 20, 25, 28, 2, 13, 21, 56, 57, 60, 1, 9, 17, 48, 4, 13, 33, 2, 9, 27, 1, 3, 7,
EQEP1_A I eQEP-1 Input A 35, 40, 44, 50, 56, 69, 78, 80, 101, 106, 57, 63, 65, 80, 42, 48, 64, 39, 53, 24, 36,
64, 65, 77, 224 113, 122, 126 85, 93, 97 69, 76, 80 63, 64 48
7, 11, 21, 29, 37, 1, 9, 14, 18, 61, 64, 10, 14, 49, 52, 3, 10, 34, 1, 6, 28, 2, 25,
EQEP1_B I eQEP-1 Input B 41, 51, 57, 66, 69, 73, 76, 81, 86, 103, 61, 66, 82, 84, 37, 46, 66, 31, 37, 28, 34,
74, 228 105 100 68 55, 57 50, 52

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Table 5-3. Digital Signals (continued)

PIN 56
SIGNAL NAME DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM
TYPE RSH
10, 16, 20, 49, 62, 2, 12, 28, 8, 24, 6, 22,
0, 9, 13, 17, 23, 31, 12, 16, 39, 50,
67, 79, 84, 91, 100, 35, 40, 49, 29, 34, 26, 31,
EQEP1_INDEX I/O eQEP-1 Index 32, 43, 53, 59, 67, 55, 64, 79, 81,
102, 112, 116, 119, 54, 63, 65, 40, 52, 37, 47,
72, 76, 80, 236, 242 90, 92, 99
121, 128 75 54, 62 49, 56
1, 8, 12, 16, 22, 30, 15, 19, 63, 66, 72, 11, 15, 51, 54, 1, 11, 36, 7, 30,
27, 30,
EQEP1_STROBE I/O eQEP-1 Strobe 42, 52, 58, 68, 71, 82, 83, 94, 95, 99, 67, 74, 78, 83, 39, 57, 58, 33, 47,
46, 51
75, 226 104, 111, 127 98 62, 67 51, 56
11, 14, 18, 24, 54, 17, 47, 64, 68, 73, 13, 52, 56, 68, 37, 41, 50, 31, 35, 28, 32,
EQEP2_A I eQEP-2 Input A
69, 215 87, 125 96 79 41 38
15, 16, 19, 25, 33, 51, 65, 66, 69, 74, 43, 53, 54, 57, 38, 39, 42, 32, 33, 29, 30,
EQEP2_B I eQEP-2 Input B
55, 70 88, 124 69, 95 51, 78 42 39
EQEP2_INDEX I/O eQEP-2 Index 26, 29, 57, 71 1, 70, 81, 83 58, 66, 100 3, 43 1 2
EQEP2_STROBE I/O eQEP-2 Strobe 4, 27, 28, 56, 64 2, 56, 71, 80, 96 1, 59, 65, 75 4, 44, 59 2, 48 3, 43
EQEP3_A I eQEP-3 Input A 22, 25, 70, 211 43, 69, 74, 104 57, 83 42, 67 56 51
EQEP3_B I eQEP-3 Input B 9, 26, 72, 212 44, 70, 84, 119 58, 90 43, 75 62 56

ADVANCE INFORMATION
11, 18, 30, 69, 81, 46, 64, 73, 87, 117,
EQEP3_INDEX I/O eQEP-3 Index 52, 68, 98 1, 37, 50 31, 41 28, 38
214 127
10, 16, 27, 40, 71, 45, 66, 71, 83, 101, 39, 44, 64, 33, 53,
EQEP3_STROBE I/O eQEP-3 Strobe 54, 59, 80, 93 30, 48
213 122 76 63
Error Status Output. This signal requires an external 24, 28, 29, 55, 64,
ERRORSTS O 1, 2, 51, 56, 68, 85 1, 43, 56, 100 3, 4, 41 1, 2, 35 2, 3, 32
pulldown. 73
0, 4, 13, 30, 33, 54, 10, 17, 62, 65, 74, 13, 50, 53, 66, 1, 35, 38, 29, 32, 26, 29,
FSIRXA_CLK I FSIRX-A Input Clock
57, 67, 70 81, 96, 100, 127 75, 79, 98 59, 63 48, 52 43, 47
3, 12, 32, 40, 44, 15, 63, 72, 79, 82, 11, 51, 64, 67, 36, 49, 60, 30, 40, 27, 37,
FSIRXA_D0 I FSIRX-A Primary Data Input
52, 58, 68 97, 101, 106 76, 80, 85 64, 69 49, 53 44, 48
2, 11, 31, 41, 53, 16, 64, 73, 80, 98, 12, 52, 65, 77, 2, 37, 61, 31, 50, 28, 45,
FSIRXA_D1 I FSIRX-A Optional Additional Data Input
56, 69 103, 128 82, 99 66 55 50
14, 71, 105, 106, 10, 59, 84, 85, 44, 68, 69,
FSITXA_CLK O FSITX-A Output Clock 7, 10, 27, 44, 51, 78 57, 63 52
114, 122 93 76
12, 70, 110, 116, 43, 73, 75,
FSITXA_D0 O FSITX-A Primary Data Output 6, 9, 26, 45, 49, 80 8, 58, 90, 97 62, 64 1, 56
119, 126 80
5, 6, 8, 25, 46, 50, 4, 13, 69, 95, 117, 9, 57, 74, 89, 6, 42, 58, 47, 61,
FSITXA_D1 O FSITX-A Optional Additional Data Output 1, 55
81 118, 126 97 74, 80 64
GPIO0 I/O General-Purpose Input Output 0 0 100 79 63 52 47
GPIO1 I/O General-Purpose Input Output 1 1 99 78 62 51 46
GPIO2 I/O General-Purpose Input Output 2 2 98 77 61 50 45
GPIO3 I/O General-Purpose Input Output 3 3 97 76 60 49 44
GPIO4 I/O General-Purpose Input Output 4 4 96 75 59 48 43
GPIO5 I/O General-Purpose Input Output 5 5 118 89 74 61 55
GPIO6 I/O General-Purpose Input Output 6 6 126 97 80 64 1
GPIO7 I/O General-Purpose Input Output 7 7 105 84 68 57 52
GPIO8 I/O General-Purpose Input Output 8 8 95 74 58 47
GPIO9 I/O General-Purpose Input Output 9 9 119 90 75 62 56
GPIO10 I/O General-Purpose Input Output 10 10 122 93 76 63
GPIO11 I/O General-Purpose Input Output 11 11 64 52 37 31 28
GPIO12 I/O General-Purpose Input Output 12 12 63 51 36 30 27
GPIO13 I/O General-Purpose Input Output 13 13 62 50 35 29 26
GPIO14 I/O General-Purpose Input Output 14 14 125 96 79
GPIO15 I/O General-Purpose Input Output 15 15 124 95 78
GPIO16 I/O General-Purpose Input Output 16 16 66 54 39 33 30
GPIO17 I/O General-Purpose Input Output 17 17 67 55 40 34 31
GPIO18 I/O General-Purpose Input Output 18 18 87 68 50 41 38
GPIO19 I/O General-Purpose Input Output 19 19 88 69 51 42 39
GPIO20 I/O General-Purpose Input Output 20 20 60 48 33 27 24
GPIO21 I/O General-Purpose Input Output 21 21 61 49 34 28 25
GPIO22 I/O General-Purpose Input Output 22 22 104 83 67 56 51
GPIO23 I/O General-Purpose Input Output 23 23 102 81 65 54 49
GPIO24 I/O General-Purpose Input Output 24 24 68 56 41 35 32
GPIO25 I/O General-Purpose Input Output 25 25 69 57 42
GPIO26 I/O General-Purpose Input Output 26 26 70 58 43

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Table 5-3. Digital Signals (continued)

PIN 56
SIGNAL NAME DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM
TYPE RSH
GPIO27 I/O General-Purpose Input Output 27 27 71 59 44
GPIO28 I/O General-Purpose Input Output 28 28 2 1 4 2 3
GPIO29 I/O General-Purpose Input Output 29 29 1 100 3 1 2
GPIO30 I/O General-Purpose Input Output 30 30 127 98 1
GPIO31 I/O General-Purpose Input Output 31 31 128 99 2
GPIO32 I/O General-Purpose Input Output 32 32 79 64 49 40 37
GPIO33 I/O General-Purpose Input Output 33 33 65 53 38 32 29
GPIO34 I/O General-Purpose Input Output 34 34 123 94 77
GPIO35 I/O General-Purpose Input Output 35 35 78 63 48 39 36
GPIO37 I/O General-Purpose Input Output 37 37 76 61 46 37 34
GPIO40 I/O General-Purpose Input Output 40 40 101 80 64 53 48
GPIO41 I/O General-Purpose Input Output 41 41 103 82 66 55 50
ADVANCE INFORMATION

GPIO42 I/O General-Purpose Input Output 42 42 94 57

GPIO43 I/O General-Purpose Input Output 43 43 91 54
GPIO44 I/O General-Purpose Input Output 44 44 106 85 69
GPIO45 I/O General-Purpose Input Output 45 45 110 73
GPIO46 I/O General-Purpose Input Output 46 46 4 6
GPIO47 I/O General-Purpose Input Output 47 47 8 6
GPIO48 I/O General-Purpose Input Output 48 48 11 7
GPIO49 I/O General-Purpose Input Output 49 49 12 8
GPIO50 I/O General-Purpose Input Output 50 50 13 9
GPIO51 I/O General-Purpose Input Output 51 51 14 10
GPIO52 I/O General-Purpose Input Output 52 52 15 11
GPIO53 I/O General-Purpose Input Output 53 53 16 12
GPIO54 I/O General-Purpose Input Output 54 54 17 13
GPIO55 I/O General-Purpose Input Output 55 55 51 43
GPIO56 I/O General-Purpose Input Output 56 56 80 65
GPIO57 I/O General-Purpose Input Output 57 57 81 66
GPIO58 I/O General-Purpose Input Output 58 58 82 67
GPIO59 I/O General-Purpose Input Output 59 59 121 92
GPIO60 I/O General-Purpose Input Output 60 60 52 44
GPIO61 I/O General-Purpose Input Output 61 61 120 91
GPIO62 I/O General-Purpose Input Output 62 62 58 46 31
GPIO63 I/O General-Purpose Input Output 63 63 59 47 32
GPIO64 I/O General-Purpose Input Output 64 64 56
GPIO65 I/O General-Purpose Input Output 65 65 57
GPIO66 I/O General-Purpose Input Output 66 66 9
GPIO67 I/O General-Purpose Input Output 67 67 10
GPIO68 I/O General-Purpose Input Output 68 68 72
GPIO69 I/O General-Purpose Input Output 69 69 73
GPIO70 I/O General-Purpose Input Output 70 70 74
GPIO71 I/O General-Purpose Input Output 71 71 83
GPIO72 I/O General-Purpose Input Output 72 72 84
GPIO73 I/O General-Purpose Input Output 73 73 85
GPIO74 I/O General-Purpose Input Output 74 74 86
GPIO75 I/O General-Purpose Input Output 75 75 111
GPIO76 I/O General-Purpose Input Output 76 76 112
GPIO77 I/O General-Purpose Input Output 77 77 113
GPIO78 I/O General-Purpose Input Output 78 78 114
GPIO79 I/O General-Purpose Input Output 79 79 115
GPIO80 I/O General-Purpose Input Output 80 80 116
GPIO81 I/O General-Purpose Input Output 81 81 117
GPIO211 I/O General-Purpose Input Output 211 211 43
GPIO212 I/O General-Purpose Input Output 212 212 44

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Table 5-3. Digital Signals (continued)

PIN 56
SIGNAL NAME DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM
TYPE RSH
GPIO213 I/O General-Purpose Input Output 213 213 45
GPIO214 I/O General-Purpose Input Output 214 214 46
GPIO215 I/O General-Purpose Input Output 215 215 47
GPIO224 I/O General-Purpose Input Output 224 224 21 17 13 9 7
GPIO226 I/O General-Purpose Input Output 226 226 19 15 11 7
GPIO227 I/O General-Purpose Input Output 227 227 48 38 28 24 22
GPIO228 I/O General-Purpose Input Output 228 228 18 14 10 6
GPIO230 I/O General-Purpose Input Output 230 230 50 40 29 25 23
GPIO236 I/O General-Purpose Input Output 236 236 49 39 28 24 22
GPIO242 I/O General-Purpose Input Output 242 242 20 16 12 8 6
GPIO247 I/O General-Purpose Input Output 247 247 42
GPIO253 I/O General-Purpose Input Output 253 253 41

ADVANCE INFORMATION
33, 38, 44, 27, 32, 24, 29,
1, 4, 8, 9, 18, 20, 57, 60, 65, 71, 74, 48, 53, 59, 61,
46, 50, 54, 37, 41, 34, 38,
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 27, 33, 37, 43, 57, 76, 81, 87, 91, 95, 66, 68, 74, 75,
58, 59, 62, 47, 48, 43, 46,
65, 70 96, 99, 119 78, 90
75 51, 62 56
29, 34, 43, 25, 28, 23, 25,
0, 5, 10, 19, 21, 26, 9, 50, 61, 70, 78, 79, 40, 49, 58, 63,
48, 49, 51, 39, 40, 36, 37,
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 32, 35, 42, 56, 66, 80, 88, 94, 100, 115, 64, 65, 69, 79,
57, 63, 74, 42, 52, 39, 47,
79, 230 118, 122 89, 93
76 61, 63 55
3, 9, 15, 29, 51, 81, 1, 14, 48, 97, 117, 10, 38, 76, 90, 3, 28, 60, 1, 24, 2, 22,
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock
227 119, 124 95, 100 75, 78 49, 62 44, 56
2, 14, 28, 34, 50, 2, 13, 50, 56, 98, 1, 9, 40, 77, 4, 29, 61, 2, 25, 3, 23,
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data
64, 80, 230 116, 123, 125 94, 96 77, 79 50 45
9, 11, 13, 15, 19, 1, 8, 10, 12, 19, 51, 6, 8, 15, 43, 3, 11, 32, 1, 7, 29, 2, 26,
23, 29, 33, 35, 41, 59, 62, 64, 65, 73, 47, 50, 52, 53, 35, 37, 38, 31, 32, 28, 29,
LINA_RX I LIN-A Receive 42, 47, 49, 55, 59, 74, 78, 88, 94, 102, 63, 69, 81, 82, 48, 51, 57, 39, 42, 36, 39,
63, 67, 69, 70, 75, 103, 111, 119, 121, 90, 92, 95, 65, 66, 75, 54, 55, 49, 50,
226 124 100 78 62 56
2, 30,
10, 12, 14, 18, 22, 2, 4, 17, 56, 63, 68, 1, 13, 51, 56, 4, 6, 36, 3, 27,
35, 37,
24, 28, 32, 37, 40, 72, 76, 79, 82, 85, 61, 64, 67, 68, 41, 46, 49, 32, 34,
LINA_TX O LIN-A Transmit 40, 41,
44, 46, 54, 58, 64, 87, 101, 104, 106, 80, 83, 85, 93, 50, 64, 67, 37, 38,
53, 56,
68, 73 122, 125 96 69, 76, 79 48, 51
63
8, 9, 12, 14, 20,
0, 5, 11, 12, 21, 30, 6, 8, 10, 16, 8, 25, 6, 23,
50, 59, 61, 63, 64, 1, 12, 29,
47, 49, 51, 57, 61, 40, 47, 49, 51, 28, 30, 25, 27,
MCANA_RX I CAN/CAN FD Receive 72, 74, 81, 100, 112, 32, 34, 36,
63, 66, 68, 70, 76, 52, 66, 79, 89, 31, 52, 28, 47,
115, 116, 118, 120, 37, 63, 74
79, 80, 230, 242 91, 98 61 55
127
4, 10, 11, 13, 18, 21,
1, 4, 7, 13, 17, 20, 7, 9, 14, 17, 2, 6, 10, 6, 9, 27, 7, 24,
52, 57, 58, 60, 62,
31, 46, 48, 50, 56, 44, 46, 48, 50, 13, 31, 33, 29, 34, 26, 31,
MCANA_TX O CAN/CAN FD Transmit 67, 80, 84, 86, 96,
60, 62, 65, 67, 72, 55, 65, 75, 78, 35, 40, 59, 48, 51, 43, 46,
99, 105, 113, 117,
74, 77, 81, 224, 228 84, 99 62, 68 57 52
128
3, 18, 33, 35, 53, 16, 65, 78, 87, 97, 12, 53, 63, 68, 38, 48, 50, 32, 39, 29, 36,
MCANB_RX I CAN/CAN FD Receive
59, 61 120, 121 76, 91, 92 60 41, 49 38, 44
61, 64, 67, 69, 46, 49, 51, 37, 40, 34, 37,
MCANB_TX O CAN/CAN FD Transmit 2, 19, 32, 37, 58 76, 79, 82, 88, 98
77 61 42, 50 39, 45
2, 24, 34, 58, 73, 48, 68, 82, 85, 98, 38, 56, 67, 77, 28, 41, 61, 24, 35, 22, 32,
OUTPUTXBAR1 O Output X-BAR Output 1
78, 227 114, 123 94 77 50 45
3, 25, 37, 54, 59, 17, 20, 69, 76, 97, 13, 16, 57, 61, 12, 42, 46, 8, 37, 6, 34,
OUTPUTXBAR2 O Output X-BAR Output 2
76, 242 112, 121 76, 92 60 49 44
7, 17, 43, 44,
4, 5, 14, 26, 48, 55, 11, 21, 51, 52, 58, 13, 31, 43, 9, 48, 7, 43,
OUTPUTXBAR3 O Output X-BAR Output 3 46, 58, 75, 89,
60, 62, 77, 224 70, 96, 113, 118, 125 59, 74, 79 61 55
96
6, 15, 27, 33, 49, 12, 59, 65, 71, 74, 8, 47, 53, 59, 32, 38, 44,
OUTPUTXBAR4 O Output X-BAR Output 4 32, 64 1, 29
61, 63, 70 120, 124, 126 91, 95, 97 78, 80
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28, 42, 64 2, 56, 94, 105 1, 84 4, 57, 68 2, 57 3, 52
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43, 81 1, 91, 117, 119 90, 100 3, 54, 75 1, 62 2, 56
0, 11, 16, 30, 44, 64, 66, 73, 83, 100, 52, 54, 79, 85, 1, 37, 39, 31, 33, 28, 30,
OUTPUTXBAR7 O Output X-BAR Output 7
69, 71, 80 106, 116, 127 98 63, 69 52 47
OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45, 72 67, 84, 110, 128 55, 99 2, 40, 73 34 31
13, 19, 27, 37, 43, 10, 62, 71, 76, 88, 35, 44, 46, 29, 37, 26, 34,
PMBUSA_ALERT I/OD PMBus-A Open-Drain Bidirectional Alert Signal 50, 59, 61, 69
45, 67 91, 110 51, 54, 73 42 39
PMBus-A Control Signal - Target Input/Controller 12, 18, 26, 35, 42, 63, 70, 72, 78, 87, 51, 58, 63, 68, 36, 43, 48, 30, 39, 27, 36,
PMBUSA_CTL I/O
Output 44, 68 94, 106 85 50, 57, 69 41 38

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Table 5-3. Digital Signals (continued)

PIN 56
SIGNAL NAME DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM
TYPE RSH
25, 33, 23, 30,
3, 9, 15, 16, 24, 35, 8, 50, 66, 68, 78, 6, 40, 54, 56, 29, 39, 41,
35, 39, 32, 36,
PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock 41, 47, 71, 73, 79, 83, 85, 97, 103, 115, 63, 76, 82, 90, 48, 60, 66,
49, 55, 44, 50,
230 119, 124 95 75, 78
62 56
6, 31, 40,
2, 14, 17, 25, 32, 4, 11, 58, 67, 69, 7, 46, 55, 57,
42, 49, 61, 34, 40, 31, 37,
PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data 34, 40, 44, 46, 48, 79, 84, 98, 101, 106, 64, 77, 80, 85,
64, 69, 77, 50, 53 45, 48
62, 72 123, 125 94, 96
79
2, 34, 3, 31,
0, 3, 5, 9, 17, 25, 2, 12, 56, 59, 67, 69, 1, 8, 47, 55, 4, 32, 40,
39, 49, 36, 44,
SCIA_RX I SCI-A Receive Data 28, 35, 49, 63, 64, 78, 84, 97, 100, 116, 57, 63, 76, 79, 42, 48, 60,
52, 61, 47, 55,
72, 80 118, 119 89, 90 63, 74, 75
62 56
1, 33, 2, 30,
1, 2, 7, 8, 16, 24, 1, 11, 58, 66, 68, 76, 7, 46, 54, 56, 3, 31, 39,
35, 37, 32, 34,
SCIA_TX O SCI-A Transmit Data 29, 37, 48, 62, 71, 83, 85, 95, 98, 99, 61, 74, 77, 78, 41, 46, 58,
47, 50, 45, 46,
73 105 84, 100 61, 62, 68
51, 57 52
29, 31, 26, 28,
ADVANCE INFORMATION

11, 13, 15, 19, 23, 10, 62, 64, 73, 81, 50, 52, 66, 69, 35, 37, 51,
SCIB_RX I SCI-B Receive Data 42, 54, 39, 49,
41, 57, 67, 69 88, 102, 103, 124 81, 82, 95 65, 66, 78
55 50
36, 50, 64, 30, 41, 27, 38,
9, 10, 12, 14, 18, 63, 72, 80, 87, 101, 51, 65, 68, 80,
SCIB_TX O SCI-B Transmit Data 67, 75, 76, 53, 56, 48, 51,
22, 40, 56, 68 104, 119, 122, 125 83, 90, 93, 96
79 62, 63 56
21, 33, 42, 67, 75, 10, 19, 61, 65, 94, 11, 34, 38, 7, 28,
SCIC_RX I SCI-C Receive Data 15, 49, 53 25, 29
81, 226 111, 117 57 32
SCIC_TX O SCI-C Transmit Data 20, 43, 68, 77, 224 21, 60, 72, 91, 113 17, 48 13, 33, 54 9, 27 7, 24
7, 30,
3, 9, 12, 18, 56, 68, 19, 63, 72, 80, 87, 15, 51, 65, 68, 11, 36, 50, 27, 38,
SPIA_CLK I/O SPI-A Clock 41, 49,
75, 226 97, 111, 119 76, 90 60, 75 44, 56
62
9, 31,
2, 8, 11, 16, 54, 69, 17, 21, 64, 66, 73, 13, 17, 52, 54, 13, 37, 39, 7, 28,
SPIA_PICO I/O SPI-A Peripheral In, Controller Out (PICO) 33, 47,
71, 77, 224 83, 95, 98, 113 74, 77 58, 61 30, 45
50
6, 29,
10, 18, 51, 62, 67, 10, 35, 40, 26, 31,
1, 4, 10, 13, 17, 35, 14, 43, 50, 55, 34, 39,
SPIA_POCI I/O SPI-A Peripheral Out, Controller In (POCI) 78, 84, 86, 96, 99, 48, 59, 62, 36, 43,
55, 67, 72, 74, 228 63, 75, 78, 93 48, 51,
122 76 46
63
8, 31, 6, 28,
0, 5, 11, 19, 24, 37, 20, 64, 68, 73, 76, 12, 37, 41,
16, 52, 56, 61, 35, 37, 32, 34,
SPIA_PTE I/O SPI-A Peripheral Transmit Enable (PTE) 57, 69, 73, 76, 80, 81, 85, 88, 100, 112, 46, 51, 63,
66, 69, 79, 89 42, 52, 39, 47,
242 116, 118 74
61 55
4, 14, 22, 26, 28, 2, 15, 56, 70, 79, 82, 1, 11, 58, 64, 4, 43, 49, 2, 40, 3, 37,
SPIB_CLK I/O SPI-B Clock
32, 52, 58, 64, 81 96, 104, 117, 125 67, 75, 83, 96 59, 67, 79 48, 56 43, 51
13, 52, 57, 60, 68,
7, 20, 24, 30, 40, 9, 44, 48, 56, 1, 33, 41, 27, 35, 24, 32,
SPIB_PICO I/O SPI-B Peripheral In, Controller Out (PICO) 80, 85, 101, 105,
50, 56, 60, 65, 73 65, 80, 84, 98 64, 68 53, 57 48, 52
127
6, 16, 21, 25, 31, 9, 14, 61, 66, 69, 81, 10, 49, 54, 57,
2, 34, 39, 28, 33, 1, 25,
SPIB_POCI I/O SPI-B Peripheral Out, Controller In (POCI) 41, 51, 57, 61, 66, 83, 103, 120, 126, 66, 82, 91, 97,
42, 66, 80 55, 64 30, 50
71 128 99
15, 23, 27, 29, 33, 1, 16, 65, 71, 74, 12, 53, 59, 81, 3, 38, 44, 1, 32, 2, 29,
SPIB_PTE I/O SPI-B Peripheral Transmit Enable (PTE)
53, 59, 70 102, 121, 124 92, 95, 100 65, 78 54 49
SYNCOUT O External ePWM Synchronization Pulse 6, 52 15, 126 11, 97 80 64 1
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled by
TDI I default. The internal pullup should be enabled or an 35 78 63 48 39 36
external pullup added on the board if this pin is used
as JTAG TDI to avoid a floating input.
JTAG Test Data Output (TDO) - TDO is the default
mux selection for the pin. The internal pullup is
disabled by default. The TDO function will be in a tri-
TDO O state condition when there is no JTAG activity, leaving 37 76 61 46 37 34
this pin floating; the internal pullup should be enabled
or an external pullup added on the board to avoid a
floating GPIO input.
USB0DM O USB-0 PHY differential data 23 102 81 65 54 49
USB0DP O USB-0 PHY differential data 41 103 82 66 55 50
Crystal oscillator input or single-ended clock input.
The device initialization software must configure this
pin before the crystal oscillator is enabled. To use this
X1 I/O 19 88 69 51 42 39
oscillator, a quartz crystal circuit must be connected
to X1 and X2. This pin can also be used to feed a
single-ended 3.3-V level clock.
X2 I/O Crystal oscillator output. 18 87 68 50 41 38

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Table 5-3. Digital Signals (continued)

PIN 56
SIGNAL NAME DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM
TYPE RSH
External Clock Output. This pin outputs a divided-
XCLKOUT O down version of a chosen clock signal from within the 16, 18, 71 66, 83, 87 54, 68 39, 50 33, 41 30, 38
device.

5.3.3 Power and Ground

Table 5-4. Power and Ground
SIGNAL PIN
DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
NAME TYPE
1.2-V Digital Logic Power Pins. TI recommends
placing a decoupling capacitor near each VDD pin
with a minimum total capacitance of approximately
VDD 6, 54, 90, 108 4, 71, 87 8, 53, 71 4, 44, 59 5, 41, 53
10 µF. It is also recommended that all VDD pins
be externally connected to each other when internal
VREG is used.

ADVANCE INFORMATION
3.3-V Analog Power Pins. Place a minimum 2.2-µF
VDDA 41 34 26 22 20
decoupling capacitor on each pin.
3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF
VDDIO 5, 55, 89, 109 3, 70, 88 7, 52, 72 43, 60 40, 54
decoupling capacitor on each pin.
Internal voltage regulator enable with internal
VREGENZ I pulldown. Tie low to VSS to enable internal VREG. 93 73 56 46 42
Tie high to VDDIO to use an external supply.
VSS Digital Ground 7, 53, 92, 107 5, 45, 72, 86 9, 30, 55, 70 5, 26, 45, 58 PAD
VSSA Analog Ground 40 33 25 21 19

5.3.4 Test, JTAG, and Reset

Table 5-5. Test, JTAG, and Reset
SIGNAL PIN
DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
NAME TYPE
TCK I JTAG test clock with internal pullup. 75 60 45 36 33
JTAG test-mode select (TMS) with
internal pullup. This serial control input
is clocked into the TAP controller on the
rising edge of TCK. This device does not
TMS I/O have a TRSTn pin. An external pullup 77 62 47 38 35
resistor (recommended 2.2 kΩ) on the
TMS pin to VDDIO should be placed on
the board to keep JTAG in reset during
normal operation.
Device Reset (in) and Watchdog Reset
(out). During a power-on condition, this
pin is driven low by the device. An
external circuit may also drive this pin
to assert a device reset. This pin is
also driven low by the MCU when a
watchdog reset occurs. During watchdog
reset, the XRSn pin is driven low for the
watchdog reset duration of 512 OSCCLK
cycles. A resistor between 2.2 kΩ and
10 kΩ should be placed between XRSn
XRSn I/OD 3 2 5 3 4
and VDDIO. If a capacitor is placed
between XRSn and VSS for noise
filtering, it should be 100 nF or smaller.
These values will allow the watchdog
to properly drive the XRSn pin to VOL
within 512 OSCCLK cycles when the
watchdog reset is asserted. This pin is
an open-drain output with an internal
pullup. If this pin is driven by an external
device, it should be done using an open-
drain device.

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5.4 Pin Multiplexing

5.4.1 GPIO Muxed Pins
Table 5-6. GPIO Muxed Pins
0, 4,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
8, 12
GPIO EPWM1_ OUTPUT I2CA_SD FSIRXA_ CLB_OUTP EQEP1_IND
SCIA_RX SPIA_PTE MCANA_RX EPWM3_A
0 A XBAR7 A CLK UTXBAR8 EX
GPIO EPWM1_ EQEP1_S CLB_OUTP
SCIA_TX I2CA_SCL SPIA_POCI MCANA_TX EPWM10_B EPWM3_B
1 B TROBE UTXBAR7
GPIO EPWM2_ OUTPUTXB PMBUSA_
SPIA_PICO SCIA_TX FSIRXA_D1 I2CB_SDA EPWM10_A MCANB_TX EPWM4_A
2 A AR1 SDA
GPIO EPWM2_ OUTPUTXB OUTPUTXB PMBUSA_
SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL MCANB_RX EPWM4_B
3 B AR2 AR2 SCL
GPIO EPWM3_ MCANA_ OUTPUTXB EQEP2_S FSIRXA_CL CLB_OUTP
I2CA_SCL SPIB_CLK EPWM11_B SPIA_POCI EPWM1_A
4 A TX AR3 TROBE K UTXBAR6
GPIO EPWM3_ OUTPUT FSITXA_D CLB_OUTP
ADVANCE INFORMATION

I2CA_SDA MCANA_RX SPIA_PTE SCIA_RX EPWM1_B

5 B XBAR3 1 UTXBAR5
GPIO EPWM4_ OUTPUTXB SYNCOU FSITXA_D CLB_OUTP
EQEP1_A SPIB_POCI FSITXA_D1 EPWM2_A
6 A AR4 T 0 UTXBAR8
GPIO EPWM4_ OUTPUT FSITXA_C CLB_OUTP
EPWM2_A EQEP1_B SPIB_PICO SCIA_TX MCANA_TX EPWM2_B
7 B XBAR5 LK UTXBAR2
GPIO EPWM5_ ADCSOC EQEP1_STR CLB_OUTP
SCIA_TX SPIA_PICO I2CA_SCL FSITXA_D1 EPWM11_A
8 A AO OBE UTXBAR5
GPIO EPWM5_ OUTPUT EQEP1_IND PMBUSA_S
SCIB_TX SCIA_RX SPIA_CLK I2CA_SCL FSITXA_D0 LINA_RX I2CB_SCL EQEP3_B
9 B XBAR6 EX CL
GPIO EPWM6_ ADCSOC I2CA_SD FSITXA_CL EQEP3_STR CLB_OUTP
EQEP1_A SCIB_TX SPIA_POCI LINA_TX
10 A BO A K OBE UTXBAR4
GPIO EPWM6_ OUTPUT FSIRXA_ EQEP3_IND
MCANA_RX EQEP1_B SCIB_RX SPIA_PTE LINA_RX EQEP2_A SPIA_PICO
11 B XBAR7 D1 EX
GPIO EPWM7_ MCANA_ EQEP1_STR PMBUSA_C FSIRXA_
SCIB_TX LINA_TX SPIA_CLK
12 A RX OBE TL D0
GPIO EPWM7_ MCANA_ EQEP1_IND PMBUSA_A FSIRXA_
SCIB_RX LINA_RX SPIA_POCI
13 B TX EX LERT CLK
GPIO EPWM8_ OUTPUTX PMBUSA_S CLB_OUTP
SCIB_TX I2CB_SDA SPIB_CLK EQEP2_A LINA_TX EPWM3_A
14 A BAR3 DA UTXBAR7
GPIO EPWM8_ OUTPUTX PMBUSA_S CLB_OUTP
SCIB_RX I2CB_SCL SPIB_PTE EQEP2_B LINA_RX EPWM3_B
15 B BAR4 CL UTXBAR6
GPIO SPIA_PIC OUTPUT EQEP1_S PMBUSA_S EQEP3_STR
EPWM9_A SCIA_TX XCLKOUT EQEP2_B SPIB_POCI
16 O XBAR7 TROBE CL OBE
GPIO SPIA_PO OUTPUT EQEP1_I PMBUSA_S
EPWM9_B SCIA_RX MCANA_TX EPWM6_A
17 CI XBAR8 NDEX DA
GPIO MCANB_ PMBUSA_C EQEP3_IND
SPIA_CLK SCIB_TX EPWM6_A I2CA_SCL EQEP2_A XCLKOUT LINA_TX X2
18 RX TL EX
GPIO MCANB_ I2CA_SD PMBUSA_A CLB_OUTP
SPIA_PTE SCIB_RX EPWM6_B EQEP2_B LINA_RX X1
19 TX A LERT UTXBAR1
GPIO SPIB_PIC MCANA_T ADCE_EXT
EQEP1_A EPWM12_A I2CA_SCL SCIC_TX
20 O X MUXSEL0
GPIO SPIB_PO MCANA_ ADCE_EXT
EQEP1_B EPWM12_B I2CA_SDA SCIC_RX
21 CI RX MUXSEL1
GPIO EQEP1_S CLB_OUTP
SCIB_TX SPIB_CLK LINA_TX LINA_TX EPWM4_A EQEP3_A
22 TROBE UTXBAR1
GPIO EQEP1_I CLB_OUTP USB0
SCIB_RX SPIB_PTE LINA_RX LINA_RX EPWM12_A EPWM4_B
23 NDEX UTXBAR3 DM
GPIO OUTPUTX SPIA_PT SPIB_PIC PMBUSA_S
EQEP2_A EPWM8_A LINA_TX SCIA_TX ERRORSTS EPWM9_A
24 BAR1 E O CL
GPIO OUTPUTX SPIB_PO FSITXA_D PMBUSA_S
EQEP2_B EQEP1_A SCIA_RX EQEP3_A
25 BAR2 CI 1 DA
GPIO OUTPUTX EQEP2_IND OUTPUTXB FSITXA_D PMBUSA_C
SPIB_CLK I2CA_SDA EQEP3_B
26 BAR3 EX AR3 0 TL
GPIO OUTPUTX EQEP2_STR OUTPUTXB FSITXA_C PMBUSA_A EQEP3_STR
SPIB_PTE I2CA_SCL
27 BAR4 OBE AR4 LK LERT OBE
GPIO EPWM7_ OUTPUTXB EQEP2_S
SCIA_RX EQEP1_A LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
28 A AR5 TROBE
GPIO EPWM7_ OUTPUTXB EQEP2_I AUXC
SCIA_TX EQEP1_B LINA_RX SPIB_PTE ERRORSTS I2CB_SCL
29 B AR6 NDEX LKIN
GPIO SPIB_PI OUTPUTXB EQEP1_S FSIRXA_ EQEP3_IND
MCANA_RX EPWM1_A
30 CO AR7 TROBE CLK EX

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Table 5-6. GPIO Muxed Pins (continued)

0, 4,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
8, 12
GPIO SPIB_PO OUTPUTXB EQEP1_I FSIRXA_
MCANA_TX EPWM1_B
31 CI AR8 NDEX D1
GPIO I2CA_SD EQEP1_IND SPIB_CL FSIRXA_ PMBUSA_S
EPWM8_B LINA_TX MCANB_TX ADCSOCBO
32 A EX K D0 DA
GPIO SPIB_PT OUTPUTXB FSIRXA_
I2CA_SCL LINA_RX MCANB_RX EQEP2_B ADCSOCAO SCIC_RX
33 E AR4 CLK
GPIO OUTPUTX PMBUSA_
I2CB_SDA
34 BAR1 SDA
GPIO I2CA_SD PMBUSA_ PMBUSA_C
SCIA_RX SPIA_POCI MCANB_RX LINA_RX EQEP1_A EPWM5_B TDI
35 A SCL TL
GPIO OUTPUTX I2CA_SC MCANB_T PMBUSA_A
SPIA_PTE SCIA_TX LINA_TX EQEP1_B EPWM5_A TDO
37 BAR2 L X LERT
GPIO SPIB_PIC PMBUSA_ CLB_OUTP EQEP3_STR
EPWM2_B FSIRXA_D0 SCIB_TX EQEP1_A LINA_TX
40 O SDA UTXBAR4 OBE
GPIO EPWM7_ PMBUSA_ USB0

ADVANCE INFORMATION
EPWM2_A FSIRXA_D1 SCIB_RX EQEP1_B LINA_RX EPWM12_B SPIB_POCI
41 A SCL DP
GPIO OUTPUT PMBUSA_C I2CA_SD EQEP1_STR CLB_OUTP
LINA_RX SCIC_RX
42 XBAR5 TL A OBE UTXBAR3
GPIO OUTPUT PMBUSA_A PMBUSA_ EQEP1_IND CLB_OUTP
I2CA_SCL SCIC_TX
43 XBAR6 LERT ALERT EX UTXBAR4
GPIO OUTPUT PMBUSA_ FSITXA_CL PMBUSA_ CLB_OUTP
EQEP1_A FSIRXA_D0 LINA_TX
44 XBAR7 SDA K CTL UTXBAR3
GPIO OUTPUT PMBUSA_ CLB_OUTP
FSITXA_D0
45 XBAR8 ALERT UTXBAR4
GPIO PMBUSA_
LINA_TX MCANA_TX FSITXA_D1
46 SDA
GPIO CLB_OUTP PMBUSA_
LINA_RX MCANA_RX
47 UTXBAR2 SCL
GPIO OUTPUTX PMBUSA_
MCANA_TX SCIA_TX
48 BAR3 SDA
GPIO OUTPUTX
MCANA_RX SCIA_RX LINA_RX FSITXA_D0
49 BAR4
GPIO SPIB_PIC I2CB_SD
EQEP1_A MCANA_TX FSITXA_D1
50 O A
GPIO SPIB_PO FSITXA_CL
EQEP1_B MCANA_RX I2CB_SCL
51 CI K
GPIO EQEP1_S CLB_OUTP SYNCOU
SPIB_CLK FSIRXA_D0
52 TROBE UTXBAR5 T
GPIO EQEP1_I CLB_OUTP ADCSOC
SPIB_PTE MCANB_RX FSIRXA_D1
53 NDEX UTXBAR6 AO
GPIO SPIA_PIC OUTPUTX ADCSOC FSIRXA_CL
EQEP2_A LINA_TX
54 O BAR2 BO K
GPIO SPIA_PO OUTPUTX ERRORS
EQEP2_B LINA_RX
55 CI BAR3 TS
GPIO CLB_OUTP MCANA_ EQEP2_STR SPIB_PIC
SPIA_CLK SCIB_TX I2CA_SDA EQEP1_A FSIRXA_D1
56 UTXBAR7 TX OBE O
GPIO CLB_OUTP MCANA_ EQEP2_IND SPIB_PO FSIRXA_CL
SPIA_PTE SCIB_RX I2CA_SCL EQEP1_B
57 UTXBAR8 RX EX CI K
GPIO OUTPUTXB EQEP1_STR
SPIB_CLK LINA_TX MCANB_TX FSIRXA_D0
58 AR1 OBE
GPIO OUTPUTXB EQEP1_IND
SPIB_PTE LINA_RX MCANB_RX
59 AR2 EX
GPIO EPWM12_ MCANA_ OUTPUTXB SPIB_PIC
60 B TX AR3 O
GPIO MCANA_ OUTPUTXB SPIB_PO
MCANB_RX
61 RX AR4 CI
GPIO EPWM10_ OUTPUTXB PMBUSA_
MCANA_TX SCIA_TX
62 A AR3 SDA
GPIO EPWM10_ OUTPUTXB
MCANA_RX SCIA_RX LINA_RX
63 B AR4
GPIO EPWM7_ OUTPUTXB EQEP2_S
SCIA_RX EPWM11_A EQEP1_A LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
64 A AR5 TROBE
GPIO SPIB_PIC MCANA_T
EQEP1_A EPWM11_B I2CA_SCL
65 O X
GPIO SPIB_PO MCANA_
EQEP1_B EPWM12_A I2CA_SDA
66 CI RX

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Table 5-6. GPIO Muxed Pins (continued)

0, 4,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
8, 12
GPIO EPWM7_ MCANA_ EQEP1_IND PMBUSA_A FSIRXA_
EPWM12_B SCIB_RX LINA_RX SPIA_POCI SCIC_RX
67 B TX EX LERT CLK
GPIO EPWM7_ MCANA_ EQEP1_STR PMBUSA_C FSIRXA_
EPWM3_A SCIB_TX LINA_TX SPIA_CLK SCIC_TX
68 A RX OBE TL D0
GPIO EPWM6_ OUTPUT FSIRXA_ EQEP3_IND
EPWM3_B EQEP1_B SCIB_RX SPIA_PTE LINA_RX EQEP2_A SPIA_PICO
69 B XBAR7 D1 EX
GPIO SPIB_PT OUTPUTXB FSIRXA_
I2CA_SCL LINA_RX MCANA_RX EQEP2_B ADCSOCAO EQEP3_A
70 E AR4 CLK
GPIO SPIA_PIC OUTPUT EQEP1_S PMBUSA_S EQEP2_IND EQEP3_STR
EPWM4_B EPWM9_A SCIA_TX XCLKOUT SPIB_POCI
71 O XBAR7 TROBE CL EX OBE
GPIO SPIA_PO OUTPUT EQEP1_I PMBUSA_S
EPWM5_A EPWM9_B SCIA_RX MCANA_TX EPWM6_A EQEP3_B
72 CI XBAR8 NDEX DA
GPIO OUTPUTX SPIA_PT SPIB_PIC PMBUSA_S
EPWM5_B EPWM8_A LINA_TX SCIA_TX ERRORSTS EPWM9_A
73 BAR1 E O CL
GPIO EPWM2_ ADCSOC SPIA_PO
ADVANCE INFORMATION

MCANA_TX EQEP1_B
74 B AO CI
GPIO EPWM1_ EQEP1_STR
LINA_RX EPWM6_A SPIA_CLK SCIC_RX
75 B OBE
GPIO EPWM4_ OUTPUTXB EQEP1_IND
SPIA_PTE MCANA_RX
76 A AR2 EX
GPIO EPWM1_ OUTPUTXB SPIA_PIC
MCANA_TX EQEP1_A SCIC_TX
77 A AR3 O
GPIO EPWM3_ OUTPUTXB EPWM2_ FSITXA_C
EPWM8_A
78 A AR1 B LK
GPIO EPWM3_ EPWM2_ PMBUSA_
EPWM8_B MCANA_RX I2CA_SDA
79 B A SCL
GPIO EPWM1_ OUTPUT I2CB_SD FSITXA_D CLB_OUTP EQEP1_IND
SCIA_RX SPIA_PTE MCANA_RX EPWM3_A
80 A XBAR7 A 0 UTXBAR8 EX
GPIO EPWM1_ OUTPUTXB FSITXA_D EQEP3_IND
SCIC_RX SPIB_CLK I2CB_SCL MCANA_TX
81 B AR6 1 EX
GPIO EPWM10_
EQEP3_A
211 A
GPIO EPWM10_
EQEP3_B
212 B
GPIO EPWM11_ EQEP3_STR
213 A OBE
GPIO EPWM11_ EQEP3_IND
214 B EX
GPIO EPWM7_
EQEP2_A
215 B
GPIO EPWM11_ OUTPUTXB SPIA_PIC EPWM1_ ADCE_EXT
MCANA_TX EQEP1_A SCIC_TX
224 B AR3 O A MUXSEL3
GPIO EPWM10_ EPWM1_ EQEP1_STR ADCE_EXT
LINA_RX EPWM6_A SPIA_CLK SCIC_RX
226 B B OBE MUXSEL1
GPIO EPWM3_ OUTPUTXB EPWM2_
I2CB_SCL
227 A AR1 B
GPIO EPWM10_ ADCSOC SPIA_PO EPWM2_ ADCE_EXT
MCANA_TX EQEP1_B
228 A AO CI B MUXSEL0
GPIO I2CB_SD EPWM3_ EPWM2_ PMBUSA_
MCANA_RX I2CA_SDA
230 A B A SCL
GPIO EPWM7_ EQEP1_IND EPWM12_
236 A EX A
GPIO EPWM11_ OUTPUTXB EPWM4_ EQEP1_IND ADCE_EXT
SPIA_PTE MCANA_RX
242 A AR2 A EX MUXSEL2
GPIO EPWM12_
247 B
GPIO EPWM12_
253 A
AIO20
8
AIO20
9
AIO21
0
AIO22
5

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Table 5-6. GPIO Muxed Pins (continued)

0, 4,
1 2 3 5 6 7 9 10 11 13 14 15 ALT
8, 12
AIO22
9
AIO23
1
AIO23
2
AIO23
3
AIO23
4
AIO23
5
AIO23
7
AIO23

ADVANCE INFORMATION
8
AIO23
9
AIO24
0
AIO24
1
AIO24
4
AIO24
5
AIO24
8
AIO24
9
AIO25
1
AIO25
2

5.4.2 Digital Inputs on ADC Pins (AIOs)

Some GPIOs are multiplexed with analog pins and only have digital input functionality. These are also referred to
as AIOs. Pins with only an AIO option on this port can only function in input mode. See the device data sheet for
list of AIO signals. By default, these pins function as analog pins and the GPIOs are in a high-impedance state.
The GPyAMSEL register is used to configure these pins for digital or analog operation.

Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. Therefore, limit the edge rate of signals connected to AIOs if adjacent
channels are being used for analog functions.

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5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)

Some GPIOs are multiplexed with analog pins and have digital input and output functionality. These are also
referred to as AGPIOs. Unlike AIOs, AGPIOs have full input and output capability.
By default, the AGPIOs are not connected and must be configured. Table 5-7 shows how to configure the
AGPIOs. To enable the analog functionality, set the register AGPIOCTRLx from analog subsystem. To enable
the digital functionality, set the register GPxAMSEL from the General-Purpose Input/Output (GPIO) chapter.
Table 5-7. AGPIO Configuration
AGPIOCTRLx.GPIOy GPxAMSEL.GPIOy Pin Connected To:
(Default = 0) (Default = 1) ADC GPIOy
0 0 - Yes
(1) (1)
0 1 - -
1 0 - Yes
ADVANCE INFORMATION

1 1 Yes -

(1) By default there are no signals connected to AGPIO pins. One of the other rows in the table must be chosen for pin functionality.

Note
If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with
adjacent analog signals. The user must therefore limit the edge rate of signals connected to AGPIOs,
if adjacent channels are being used for analog functions.

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5.4.4 GPIO Input X-BAR

The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see the Input X-BAR figure). The Input X-BAR Destinations table lists the
input X-BAR destinations. For details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the
TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.

GPIO0 Asynchronous
Synchronous Input X-BAR
GPIOx Sync. + Qual.

Other Sources
INPUT16
INPUT15
INPUT14
INPUT13
INPUT12

INPUT10
INPUT11

INPUT9
INPUT8
INPUT7
INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
127:16
eCAP1
eCAP2
INPUT[16:1]

ADVANCE INFORMATION
15:0
EPG1IN1
EPG EPG1IN2
EPG1IN3
EPG1IN4
TZ1,TRIP1
TZ2,TRIP2 ePWM
DCCx Clock Source-0
TZ3,TRIP3 Modules
TRIP6
DCCx Clock Source-1
INPUT[1-14] CLB X-BAR

XINT1 INPUT[1-16] ERAD

XINT2
CPU PIE
XINT3
ePWM
CLA XINT4 INPUT[1-14] X-BAR
XINT5

CMPSS1/3 FILINIT High ADCEXTSOC ADC

CMPSS CMPSS1/3 FILINIT Low
CMPSS2/4 FILINIT High
CMPSS2/4 FILINIT Low ePWM and
EXTSYNCIN1
eCAP Sync
EXTSYNCIN2 Scheme
Other Sources

Output X-BAR

Figure 5-6. Input X-BAR

Table 5-8. Input X-BAR Destinations

EPWM /
EPWM CLB OUTPU EPWM CPU ADC
Input ECAP ERAD ECAP CMPSS DCCx EPG
XBAR XBAR T XBAR TRIP XINT SOC
SYNC
TZ1,
INPUTXBAR1 Yes Yes Yes Yes Yes
TRIP1
TZ2,
INPUTXBAR2 Yes Yes Yes Yes Yes
TRIP2
TZ3,
INPUTXBAR3 Yes Yes Yes Yes Yes
TRIP3
INPUTXBAR4 Yes Yes Yes Yes Yes XINT1
ADCE
EXTSY
INPUTXBAR5 Yes Yes Yes Yes Yes XINT2 XTSO
NCIN1
C
EXTSY
INPUTXBAR6 Yes Yes Yes Yes TRIP6 Yes XINT3
NCIN2

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Table 5-8. Input X-BAR Destinations (continued)

EPWM /
EPWM CLB OUTPU EPWM CPU ADC
Input ECAP ERAD ECAP CMPSS DCCx EPG
XBAR XBAR T XBAR TRIP XINT SOC
SYNC
CMPSS1/3
.
INPUTXBAR7 Yes Yes Yes Yes
EXT_FILTI
N_H
CMPSS1/3
.
INPUTXBAR8 Yes Yes Yes Yes
EXT_FILTI
N_L
CMPSS2/4
.
INPUTXBAR9 Yes Yes Yes Yes
EXT_FILTI
N_H
ADVANCE INFORMATION

CMPSS2/4
.
INPUTXBAR10 Yes Yes Yes Yes
EXT_FILTI
N_L
INPUTXBAR11 Yes Yes Yes Yes CLK1
INPUTXBAR12 Yes Yes Yes Yes CLK1
EPGAI
INPUTXBAR13 Yes Yes Yes Yes XINT4
N1
EPGAI
INPUTXBAR14 Yes Yes Yes Yes XINT5
N2
EPGAI
INPUTXBAR15 Yes Yes CLK1
N3
EPGAI
INPUTXBAR16 Yes Yes CLK0
N4

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5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB
X-BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 5-7. For details on the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F28P55x Real-Time
Microcontrollers Technical Reference Manual.

ADVANCE INFORMATION

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EPG EPG1.EPGOUT
AUXSIG1
CTRIPOUTH AUXSIG2
AUXSIG3
CTRIPOUTL
CLB AUXSIG4
CLB
X-BAR AUXSIG5 Global
CMPSSx AUXSIG6 Mux
CTRIPH AUXSIG7
CTRIPL AUXSIG8

TRIP1
TRIP2
Input X-BAR INPUT1-14 TRIP3
TRIP4
TRIP5
TRIP6
ADVANCE INFORMATION

FSI RXTRIG[1-3] TRIP7

ePWM TRIP8 All
X-BAR TRIP9 ePWM
CLB CLBx_OUT[0-7] TRIP10 Modules
TRIP11
ePWM and eCAP TRIP12
EXTSYNCOUT TRIP14
Sync Chain
TRIP15

ADCSOCA0 ADCSOCA0 eQEPx

Select Circuit
OUTPUTXBAR1
ADCSOCB0 OUTPUTXBAR2
ADCSOCB0
Select Circuit OUTPUTXBAR3
Output OUTPUTXBAR4
X-BAR OUTPUTXBAR5
eCAPx ECAPxOUT OUTPUTXBAR6
OUTPUTXBAR7
EVT1 OUTPUTXBAR8
ADCx EVT2
EVT3
EVT4 GPIO
X-BAR Flags
(shared) Mux
CLAHALT CLAHALT

ERAD EVT[8-11] CLB_OUTPUTXBAR1

CLB_OUTPUTXBAR2
CLB CLB_OUTPUTXBAR3
MCANx FEVT[0-2] CLB_OUTPUTXBAR4
Output CLB_OUTPUTXBAR5
X-BAR CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8

CLB Input X-BAR CLB TILEx

Figure 5-7. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources

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5.5 Pins With Internal Pullup and Pulldown

Some pins on the device have internal pullups or pulldowns. Table 5-9 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 5-9 with pullups and pulldowns are always on and cannot be
disabled.
Table 5-9. Pins With Internal Pullup and Pulldown
RESET
PIN DEVICE BOOT APPLICATION
(XRSn = 0)
GPIOx Pullup disabled Pullup disabled(1) Application defined
GPIO35/TDI Pullup disabled Application defined
GPIO37/TDO Pullup disabled Application defined

ADVANCE INFORMATION
TCK Pullup active
TMS Pullup active
XRSn Pullup active
Other pins (including AIOs) No pullup or pulldown present

(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.

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5.6 Connections for Unused Pins

For applications that do not need to use all functions of the device, Table 5-10 lists acceptable conditioning for
any unused pins. When multiple options are listed in Table 5-10, any option is acceptable. Pins not listed in Table
5-10 must be connected according to Section 5.
Table 5-10. Connections for Unused Pins
SIGNAL NAME ACCEPTABLE PRACTICE
ANALOG
VREFHI Tie to VDDA (applies only if ADC is not used in the application)
VREFLO Tie to VSSA

Analog input pins with • No Connect

DACx_OUT • Tie to VSSA through 4.7-kΩ or larger resistor
ADVANCE INFORMATION

• No Connect
Analog input pins (except • Tie to VSSA
DACx_OUT)
• Tie to VSSA through resistor

• No connection (digital input mode with internal pullup enabled)

Analog input pins (shared with • No connection (digital output mode with internal pullup disabled)
GPIOs)(1)
• Pullup or pulldown resistor (any value resistor, digital input mode, and with internal pullup disabled)

DIGITAL
• No connection (input mode with internal pullup enabled)
GPIOx • No connection (output mode with internal pullup disabled)
• Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)

When TDI mux option is selected (default), the GPIO is in Input mode.
GPIO35/TDI • Internal pullup enabled
• External pullup resistor

When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO • Internal pullup enabled
• External pullup resistor

• No Connect
TCK • Pullup resistor

TMS Pullup resistor

Turn XTAL off and:
• Input mode with internal pullup enabled
GPIO19/X1
• Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled

Turn XTAL off and:

• Input mode with internal pullup enabled
GPIO18/X2
• Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled

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Table 5-10. Connections for Unused Pins (continued)

SIGNAL NAME ACCEPTABLE PRACTICE
POWER AND GROUND
VDD All VDD pins must be connected per Section 5.3. Pins should not be used to bias any external circuits.
VDDA If a dedicated analog supply is not used, tie to VDDIO.
VDDIO All VDDIO pins must be connected per Section 5.3.
VSS All VSS pins must be connected to board ground.
VSSA If an analog ground is not used, tie to VSS.

(1) AGPIO pins share analog and digital functionality. The actions here only apply if these pins are also not being used for analog
functions.

ADVANCE INFORMATION

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6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating conditions (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDD with respect to VSS –0.3 1.5
Supply voltage VDDIO with respect to VSS –0.3 4.6 V
VDDA with respect to VSSA –0.3 4.6
VIN (3.3 V) –0.3 4.6 V
Input voltage(7)
VIN (5.0 V) (5) –0.3 6.0 V
Output voltage VO –0.3 4.6 V
IIK
- VIN < VSS/VSSA
Input clamp current - per pin(4) (6) –20 20 mA
- VIN > VDDIO/VDDA
ADVANCE INFORMATION

Input clamp current - per pin: IIK

–20 mA
GPIO2/3/9/32 - VIN < VSS
IIKTOTAL
Input clamp current - total for all inputs(4) - VIN < VSS/VSSA
(6) –20 20 mA
- VIN > VDDIO/VDDA

Output current Digital output (per pin), IOUT –20 20 mA

Operating junction temperature TJ –40 155 °C
Storage temperature(3) Tstg –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
(4) Continuous clamp current per pin is ±2mA
(5) GPIO2, GPIO3, GPIO9, GPIO32 Only
(6) Applying a VIN greater than VDDIO/VDDA or less than VSS/VSSA will turn on the ESD current clamping diode causing additional
current flow to the respective supply rail. If this occurs, the current must be kept within the MIN/MAX listed to prevent permanent
damage to the device.
(7) Input clamp current must also be observed.

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6.2 ESD Ratings – Commercial

VALUE UNIT
All F28P550Sxx devices in 128-pin PDT package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Charged-device model (CDM), All pins ±500
V(ESD) Electrostatic discharge V
per ANSI/ESDA/JEDEC JS-002(2)
Corner pins on 128-pin PDT: ±750
1, 32, 33, 64, 65, 96, 97, 128
All F28P550Sxx devices in 100-pin PZ package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Charged-device model (CDM), All pins ±500
V(ESD) Electrostatic discharge V
per ANSI/ESDA/JEDEC JS-002(2)
Corner pins on 100-pin PZ: ±750
1, 25, 26, 50, 51, 75, 76, 100

ADVANCE INFORMATION
All F28P550Sxx devices in 80-pin PNA package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Charged-device model (CDM), All pins ±500
V(ESD) Electrostatic discharge V
per ANSI/ESDA/JEDEC JS-002(2)
Corner pins on 80-pin PNA: ±750
1, 20, 21, 40, 41, 60, 61, 80
All F28P550Sxx devices in 64-pin PM package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Charged-device model (CDM), All pins ±500
V(ESD) Electrostatic discharge V
per ANSI/ESDA/JEDEC JS-002(2)
Corner pins on 64-pin PM: ±750
1, 16, 17, 32, 33, 48, 49, 64
All F28P550Sxx devices in 56-pin RSH package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Charged-device model (CDM), All pins ±500
V(ESD) Electrostatic discharge V
per ANSI/ESDA/JEDEC JS-002(2)
Corner pins on 56-pin RSH: ±750
1, 14, 15, 28, 29, 42, 43, 56

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 ESD Ratings – Automotive

VALUE UNIT
All F28P559Sxx-Q1 devices in 128-pin PDT package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 128-pin PDT: ±750
1, 32, 33, 64, 65, 96, 97, 128
All F28P559Sxx-Q1 devices in 100-pin PZ package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 100-pin PZ: ±750
ADVANCE INFORMATION

1, 25, 26, 50, 51, 75, 76, 100

All F28P559Sxx-Q1 devices in 80-pin PNA package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 80-pin PNA: ±750
1, 20, 21, 40, 41, 60, 61, 80
All F28P559Sxx-Q1 devices in 64-pin PM package
Human body model (HBM), per All pins ±2000
AEC Q100-002(1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner pins on 64-pin PM: ±750
1, 16, 17, 32, 33, 48, 49, 64

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
Internal BOR enabled(3) VBOR-VDDIO(MAX) + VBOR-GB (2) 3.3 3.63
Device supply voltage, VDDIO and VDDA V
Internal BOR disabled 2.8 3.3 3.63
Device supply voltage, VDD 1.14 1.2 1.32 V
Device ground, VSS 0 V
Analog ground, VSSA 0 V
Supply ramp rate of VDDIO, VDD,
SRSUPPLY
VDDA with respect to VSS.(4)
Digital input voltage(6) VSS – 0.3 VDDIO + 0.3 V
Digital input voltage(GPIO2, 3, 9, and
VIN VSS – 0.3 5.5 V
32)(5)
Analog input voltage(6) VSSA – 0.3 VDDA + 0.3 V
Junction temperature, TJ (1) –40 150 °C
Free-Air temperature, TA –40 125 °C

(1) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
(2) See the Power Management Module (PMM) section.
(3) Internal BOR is enabled by default.
(4) See the Power Management Module Operating Conditions table.
(5) These pins support applied voltage prior to the device being powered
(6) Applying a VIN greater than VDDIO/VDDA or less than VSS/VSSA will turn on the ESD current clamping diode causing additional
current flow to the respective supply rail. VDDIO/VDDA voltage will internally rise and could impact other electrical characteristics.

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6.5 Power Consumption Summary

Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations.
6.5.1 System Current Consumption - VREG Enable - Internal Supply
Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING MODE
This is an estimation of 30 ℃ 92 mA
VDDIO current consumption current for a typical heavily
IDDIO 85 ℃ 105 mA
during operational usage loaded application. Actual
currents will vary depending 125 ℃ 115 mA

ADVANCE INFORMATION
on system activity, I/O 30 ℃ 1 mA
electrical loading and
switching frequency. This 85 ℃ 3 mA
includes Core supply current
with Internal Vreg Enabled.
- CPU is running from RAM
- Flash is powered up
- X1/X2 crystal is powered up
VDDA current consumption - PLL is enabled,
IDDA
during operational usage SYSCLK=Max Device
frequency 125 ℃ 8 mA
- Analog modules are
powered up
- Outputs are static without
DC Load
- Inputs are static high or low

IDLE MODE
- CPU is in IDLE mode 30 ℃ 30 mA
VDDIO current consumption - Flash is powered down
IDDIO 85 ℃ 36 mA
while device is in Idle mode - PLL is Enabled,
SYSCLK=Max Device 125 ℃ 48 mA
Frequency, CPUCLK is gated 30 ℃ 1 mA
- X1/X2 crystal is powered up
- Analog Modules are 85 ℃ 3 mA
VDDA current consumption while powered down
IDDA
device is in Idle mode - Outputs are static without
DC Load 125 ℃ 8 mA
- Inputs are static high or low
STANDBY MODE (PLL Enabled)
- CPU is in STANDBY mode 30 ℃ 8 mA
VDDIO current consumption - Flash is powered down
IDDIO 85 ℃ 14 mA
while device is in Standby mode- PLL is Enabled, SYSCLK &
CPUCLK are gated 125 ℃ 25 mA
- X1/X2 crystal is powered 30 ℃ 1 mA
down
- Analog Modules are 85 ℃ 3 mA
VDDA current consumption while powered down
IDDA
device is in Standby mode - Outputs are static without
DC Load 125 ℃ 8 mA
- Inputs are static high or low

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6.5.1 System Current Consumption - VREG Enable - Internal Supply (continued)

Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STANDBY MODE (PLL Disabled)
- CPU is in STANDBY mode 30 ℃ 4 mA
VDDIO current consumption - Flash is powered down
IDDIO 85 ℃ 10 mA
while device is in Standby mode- PLL is Disabled, SYSCLK &
CPUCLK are gated 125 ℃ 21 mA
- X1/X2 crystal is powered 30 ℃ 1 mA
down
- Analog Modules are 85 ℃ 3 mA
VDDA current consumption while powered down
IDDA
device is in Standby mode - Outputs are static without
DC Load 125 ℃ 8 mA
- Inputs are static high or low
ADVANCE INFORMATION

HALT MODE
- CPU is in HALT mode 30 ℃ 4 mA
VDDIO current consumption - Flash is powered down
IDDIO 85 ℃ 10 mA
while device is in Halt mode - PLL is Disabled, SYSCLK
and CPUCLK are gated 125 ℃ 20 mA
- X1/X2 crystal is powered 30 ℃ 1 mA
down
- Analog Modules are 85 ℃ 3 mA
VDDA current consumption while powered down
IDDA
device is in Halt mode - Outputs are static without
DC Load 125 ℃ 8 mA
- Inputs are static high or low
FLASH ERASE/PROGRAM
VDDIO current consumption - CPU is running from RAM
IDDIO 91 128 mA
during Erase/Program cycle(1) - Flash going through
continuous Program/Erase
operation
- PLL is enabled, SYSCLK at
120 MHz.
- Peripheral clocks are turned
OFF.
VDDA current consumption - X1/X2 crystal is powered up
IDDA 0.1 8 mA
during Erase/Program cycle - Analog is powered down
- Outputs are static without
DC Load
- Inputs are static high or low

RESET MODE
30 ℃ 10 mA
VDDIO current consumption
IDDIO 85 ℃ 13 mA
while reset is active(2)
125 ℃ 20 mA
Device is under Reset
30 ℃ 0.01 mA
VDDA current consumption while
IDDA 85 ℃ 0.01 mA
reset is active(2)
125 ℃ 0.01 mA

(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, that is, XRSn is low.

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6.5.2 System Current Consumption - VREG Disable - External Supply

Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING MODE
This is an estimation of 30 ℃ 85 mA
VDD current consumption during current for a typical heavily
IDD 85 ℃ 96 mA
operational usage loaded application. Actual
currents will vary depending 125 ℃ 108 mA
on system activity, I/O 30 ℃ 13 mA
VDDIO current consumption electrical loading and
IDDIO switching frequency. This 85 ℃ 17 mA
during operational usage
includes Core supply current 125 ℃ 18 mA
with Internal Vreg Enabled.
- CPU is running from RAM 30 ℃ 1 mA

ADVANCE INFORMATION
- Flash is powered up 85 ℃ 3 mA
- X1/X2 crystal is powered up
- PLL is enabled,
SYSCLK=Max Device
VDDA current consumption frequency
IDDA
during operational usage - Analog modules are
powered up 125 ℃ 8 mA
- Outputs are static without
DC Load
- Inputs are static high or low

IDLE MODE
30 ℃ 28 mA
VDD current consumption while - CPU is in IDLE mode
IDD - Flash is powered down 85 ℃ 35 mA
device is in Idle mode
- PLL is Enabled, 125 ℃ 47 mA
SYSCLK=Max Device
30 ℃ 3 mA
Frequency, CPUCLK is gated
VDDIO current consumption
IDDIO - X1/X2 crystal is powered up 85 ℃ 6 mA
while device is in Idle mode
- Analog Modules are
125 ℃ 7 mA
powered down
- Outputs are static without 30 ℃ 1 mA
VDDA current consumption while DC Load
IDDA 85 ℃ 3 mA
device is in Idle mode - Inputs are static high or low
125 ℃ 8 mA
STANDBY MODE (PLL Enabled)
30 ℃ 6 mA
VDD current consumption while - CPU is in STANDBY mode
IDD - Flash is powered down 85 ℃ 12 mA
device is in Standby mode
- PLL is Enabled, SYSCLK & 125 ℃ 24 mA
CPUCLK are gated
30 ℃ 3 mA
- X1/X2 crystal is powered
VDDIO current consumption
IDDIO down 85 ℃ 6 mA
while device is in Standby mode
- Analog Modules are
125 ℃ 7 mA
powered down
- Outputs are static without 30 ℃ 1 mA
VDDA current consumption while DC Load
IDDA 85 ℃ 3 mA
device is in Standby mode - Inputs are static high or low
125 ℃ 8 mA

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6.5.2 System Current Consumption - VREG Disable - External Supply (continued)

Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STANDBY MODE (PLL Disabled)
30 ℃ 3 mA
VDD current consumption while - CPU is in STANDBY mode
IDD - Flash is powered down 85 ℃ 8 mA
device is in Standby mode
- PLL is Disabled, SYSCLK & 125 ℃ 20 mA
CPUCLK are gated
30 ℃ 2 mA
- X1/X2 crystal is powered
VDDIO current consumption
IDDIO down 85 ℃ 5 mA
while device is in Standby mode
- Analog Modules are
125 ℃ 6 mA
powered down
- Outputs are static without 30 ℃ 1 mA
VDDA current consumption while DC Load
IDDA 85 ℃ 3 mA
ADVANCE INFORMATION

device is in Standby mode - Inputs are static high or low

125 ℃ 8 mA
HALT MODE
30 ℃ 2 mA
VDD current consumption while - CPU is in HALT mode
IDD - Flash is powered down 85 ℃ 8 mA
device is in Halt mode
- PLL is Disabled, SYSCLK 125 ℃ 20 mA
and CPUCLK are gated
30 ℃ 2 mA
- X1/X2 crystal is powered
VDDIO current consumption
IDDIO down 85 ℃ 5 mA
while device is in Halt mode
- Analog Modules are
125 ℃ 6 mA
powered down
- Outputs are static without 30 ℃ 1 mA
VDDA current consumption while DC Load
IDDA 85 ℃ 3 mA
device is in Halt mode - Inputs are static high or low
125 ℃ 8 mA
FLASH ERASE/PROGRAM
VDD current consumption during - CPU is running from RAM
IDD 80 108 mA
Erase/Program cycle(1) - Flash going through
continuous Program/Erase
VDDIO current consumption
IDDIO operation 11 20 mA
during Erase/Program cycle(1)
- PLL is enabled, SYSCLK at
100 MHz.
- Peripheral clocks are turned
OFF.
- X1/X2 crystal is powered up
VDDA current consumption - Analog is powered down
IDDA 0.1 8 mA
during Erase/Program cycle - Outputs are static without
DC Load
- Inputs are static high or low

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6.5.2 System Current Consumption - VREG Disable - External Supply (continued)

Over recommended operating conditions (unless otherwise noted)
TYP : Vnom, Temperatures shown are TJ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESET MODE
30 ℃ 5 mA
VDD current consumption while
IDD 85 ℃ 8 mA
reset is active(2)
125 ℃ 15 mA
30 ℃ 5 mA
VDDIO current consumption
IDDIO Device is under Reset 85 ℃ 5 mA
while reset is active(2)
125 ℃ 5 mA
30 ℃ 0.01 mA
VDDA current consumption while
IDDA 85 ℃ 0.01 mA

ADVANCE INFORMATION
reset is active(2)
125 ℃ 0.01 mA

(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, that is XRSn is low.

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6.5.3 Operating Mode Test Description

The System Current Consumption - VREG Enable - Internal Supply table, System Current Consumption - VREG
Disable - External Supply table, and Section 6.5.4 list the current consumption values for the operational mode
of the device. The operational mode provides an estimation of what an application might encounter. The test
condition for these measurements has the following properties:
• Code is executing from RAM.
• FLASH is read and kept in active state.
• No external components are driven by I/O pins.
• All peripherals have clocks enabled.
• The CPU is actively executing code.
• All analog peripherals are powered up. ADCs and DACs are periodically converting.
6.5.4 Reducing Current Consumption
The F28P55x devices provide some methods to reduce the device current consumption:
ADVANCE INFORMATION

• One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the
application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. The Typical Current
Reduction per Disabled Peripheral table lists the typical current reduction that may be achieved by disabling
the clocks using the PCLKCRx register.
• To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
6.5.4.1 Typical Current Reduction per Disabled Peripheral
For peripherals with multiple instances, the current quoted is for all modules combined.
PERIPHERAL IDDIO CURRENT REDUCTION (mA)
ADC(1) 1.0
CLA 0.56
CLB 1.41
CMPSS(1) 0.31
CPU TIMER 0.06
GPDAC 0.12
MCAN 1.01
DCC 0.08
eCAP 0.12
ERAD 1.56
EPG 0.32
ePWM(per) 0.95
eQEP 0.18
SCI 0.50
I2C 0.51
SPI 0.11
FSI RX 0.34
FSI TX 0.27
PMBUS 0.28

(1) This current represents the current drawn by the digital portion of the each module.

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6.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
Digital and Analog IO
IOH = IOH MIN VDDIO * 0.8
VOH High-level output voltage V
IOH = –100 μA VDDIO – 0.2
IOL = IOL MAX 0.4
VOL Low-level output voltage V
IOL = 100 µA 0.2
IOH High-level output source current for all output pins –4 mA
Low-level output sink
current for all output 4 mA
pins

ADVANCE INFORMATION
IOL IO_DRVSEL:DRVSELG
Low-level output sink 4 mA
PIOx = 0
current for all output
pins - GPIO2/3/9/32 IO_DRVSEL:DRVSELG
12 mA
PIOx = 1
ROH High-level output impedance for all output pins VOH=VDDS-0.4V 50 66 96 Ω
ROL Low-level output impedance for all output pins VOL=0.4V 48 60 84 Ω
High-level input voltage 2.0 V
IO_MODSEL:MODSEL
0.7*VDDIO V
VIH High-level input voltage GPIOx = 0
- GPIO2/3/9/32 IO_MODSEL:MODSEL
1.35 V
GPIOx = 1
Low-level input voltage 0.8 V
IO_MODSEL:MODSEL
0.3*VDDIO V
VIL Low-level input voltage - GPIOx = 0
GPIO2/3/9/32 IO_MODSEL:MODSEL
0.8 V
GPIOx = 1
Input hysteresis (AIO) 125
VHYSTERESIS mV
Input hysteresis (GPIO) 125
VDDIO = 3.3 V
IPULLDOWN Input current Pins with pulldown 120 µA
VIN = VDDIO
Digital inputs with pullup VDDIO = 3.3 V
IPULLUP Input current 160 µA
enabled(1) VIN = 0 V
RPULLDOWN Weak pulldown resistance 22 31 62 kΩ
19 29 54 kΩ
RPULLUP Weak pullup resistance
GPIO2/3/9/32 20 31 65 kΩ
Pullups and outputs
Digital inputs disabled 0.1
0 V ≤ VIN ≤ VDDIO
Digital inputs
ILEAK Pin leakage 20 µA
(GPIO2/3/9/32 only)
Analog drivers
Analog pins disabled 0.1
0 V ≤ VIN ≤ VDDA
Digital inputs 2
CI Input capacitance pF
Analog pins(2)

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6.6 Electrical Characteristics (continued)

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
VREG and BOR
VREG, POR,
BOR(3)

(1) See the Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown.
(2) The analog pins are specified separately; see the Per-Channel Parasitic Capacitance tables that are in the ADC Input Model section.
(3) See the Power Management Module (PMM) section.
ADVANCE INFORMATION

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6.7 Thermal Resistance Characteristics for PDT Package

°C/W(1)
RΘJC Junction-to-case thermal resistance 10.6
RΘJB Junction-to-board thermal resistance 24.9
RΘJA (High k PCB) Junction-to-free air thermal resistance 42.5
PsiJT Junction-to-package top 0.4
PsiJB Junction-to-board 24.4

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

ADVANCE INFORMATION
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

6.8 Thermal Resistance Characteristics for PZ Package

°C/W(1)
RΘJC Junction-to-case thermal resistance 11
RΘJB Junction-to-board thermal resistance 28.8
RΘJA (High k PCB) Junction-to-free air thermal resistance 46.4
PsiJT Junction-to-package top 0.4
PsiJB Junction-to-board 28.2

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

6.9 Thermal Resistance Characteristics for PNA Package

°C/W(1)
RΘJC Junction-to-case thermal resistance 14.5
RΘJB Junction-to-board thermal resistance 29.5
RΘJA (High k PCB) Junction-to-free air thermal resistance 51.7
PsiJT Junction-to-package top 0.5
PsiJB Junction-to-board 29.4

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

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6.10 Thermal Resistance Characteristics for PM Package

°C/W(1)
RΘJC Junction-to-case thermal resistance 11.6
RΘJB Junction-to-board thermal resistance 24.9
RΘJA (High k PCB) Junction-to-free air thermal resistance 45
PsiJT Junction-to-package top 0.4
PsiJB Junction-to-board 24.5

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
ADVANCE INFORMATION

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

6.11 Thermal Resistance Characteristics for RSH Package

°C/W(1)
Junction-to-case thermal resistance(top) 11.6
RΘJC
Junction-to-case thermal resistance(bottom) 1.2
RΘJB Junction-to-board thermal resistance 6.7
RΘJA (High k PCB) Junction-to-free air thermal resistance 23.7
PsiJT Junction-to-package top 0.1
PsiJB Junction-to-board 6.7

6.12 Thermal Design Considerations

Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems
that exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.

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6.13 System
6.13.1 Power Management Module (PMM)
6.13.1.1 Introduction
The Power Management Module (PMM) handles all the power management functions required for device
operation.
6.13.1.2 Overview
The block diagram of the PMM is shown in Figure 6-1. As can be seen, the PMM comprises of various
subcomponents, which are described in the subsequent sections.

To Rest of Chip
MCU

ADVANCE INFORMATION
PMM
I/O CPU Reset
POR RISE Release
DELAY
(80us)

I/O
BOR Internal
All RISE DELAY
Monitors (Ext VREG = 320us)
Release (Int VREG = 40us)
Signal
EN

VMONCTL.bit.BORLVMONDIS
VDD
POR
EN
OUT
IN

Internal 1.2v LDO Internal

VREG
VREGENZ
VDDIO

XRSn
VDD
VSS

VSS

External External

CVDDIO CVDD

Figure 6-1. PMM Block Diagram

6.13.1.2.1 Power Rail Monitors

The PMM has voltage monitors on the supply rails that release the XRSn signal high once the voltages cross the
set threshold during power up. They also function to trip the XRSn signal low if any of the voltages drop below
the programmed levels. The various voltage monitors are described in subsequent sections.

Note
Not all the voltage monitors are supported for device operation in an application after boot up. In the
case where a voltage monitor is not supported, an external supervisor is recommended if the device
needs supply voltage monitoring while the application is running.

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The three voltage monitors (I/O POR, I/O BOR, VDD POR) all have to release their respective outputs before the
device begins operation (that is, XRSn goes high). However, if any of the voltage monitors trips, XRSn is driven
low. The I/Os are held in high impedance when any of the voltage monitors trip.
6.13.1.2.1.1 I/O POR (Power-On Reset) Monitor
The I/O POR monitor supervises the VDDIO rail. During power up, this is the first monitor to release (that is, first
to untrip) on VDDIO.
6.13.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
The I/O BOR monitor also supervises the VDDIO rail. During power up, this is the second monitor to release
(that is, second to untrip) on VDDIO. This monitor has a tighter tolerance compared to the I/O POR.
Any drop in voltage below the recommended operating voltages will trip the I/O BOR and reset the device but
this can be disabled by setting VMONCTL.bit.BORLVMONDIS to 1. The I/O BOR can only be disabled after the
device has fully booted up. If the I/O BOR is disabled, the I/O POR will reset the device for voltage drops.
ADVANCE INFORMATION

Note
The level at which the I/O POR trips is well below the minimum recommended voltage for VDDIO, and
therefore should not be used for device supervision.

Figure 6-2 shows the operating region of the I/O BOR.

3.63 V +10%

Recommended
System Voltage
3.3 V 0% Regulator Range
VDDIO
Operating
Range
3.1 V –6.1%
VBOR-GB
BOR Guard Band
3.0 V –9.1%
VBOR-VDDIO
Internal BOR Threshold
2.81 V –14.8%
2.80 V –15.1%

Figure 6-2. I/O BOR Operating Region

6.13.1.2.1.3 VDD POR (Power-On Reset) Monitor

The VDD POR monitor supervises the VDD rail. During power up, this monitor releases (that is, untrips) once the
voltage crosses the programmed trip level on VDD.

Note
VDD POR is programmed at a level below the minimum recommended voltage for VDD, and therefore
it should not be relied upon for VDD supervision if that is required in the application.

6.13.1.2.2 External Supervisor Usage

VDDIO Monitoring: The I/O BOR is supported for application use, so an external supervisor is not required to
monitor the I/O rail.

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VDD Monitoring:
• VDD supplied from the internal VREG: The VDD supply is derived from the VDDIO supply. The VREG is
designed in such a way that a valid VDDIO supply(monitored by the IO BOR) implies a valid VDD supply.
• VDD supplied from an external supply: The VDD POR is not supported for application use. If VDD monitoring
is required by the application, an external supervisor can be used to monitor the VDD rail.

Note
The use of an external supervisor with the internal VREG is not supported.If VDD monitoring is
required by the application, a package with a VREGENZ pin must be used to power VDD externally.

6.13.1.2.3 Delay Blocks

The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage
monitors and XRSn. This is to ensure that the voltages are stable when XRSn releases. The delay blocks are
only active during power up (that is, when VDDIO and VDD are ramping up).

ADVANCE INFORMATION
The delay blocks contribute to the minimum slew rates specified in Power Management Module Electrical Data
and Timing for the power rails.

Note
The delay numbers specified in the block diagram are typical numbers.

6.13.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)

The internal VREG is supplied by the VDDIO rail and can generate the 1.2 V required to power the VDD pins.
Although the internal VREG eliminates the need to use an external supply for VDD, decoupling capacitors are
still required on the VDD pins for VREG stability and transients. See the VDD Decoupling section for details.
6.13.1.2.5 VREGENZ
The VREGENZ (VREG disable) pin controls the state of the internal VREG. To enable the internal VREG,
connect the VREGENZ pin to a logic low voltage. For applications supplying VDD externally (external VREG),
disable the internal VREG by tying the VREGENZ pin high.

Note
Not all device packages have VREGENZ pinned out. For packages without VREGENZ, external
VREG mode is not supported.

6.13.1.3 External Components

6.13.1.3.1 Decoupling Capacitors

VDDIO and VDD require decoupling capacitors for correct operation. The requirements are outlined in
subsequent sections.
6.13.1.3.1.1 VDDIO Decoupling
Place a minimum amount of decoupling capacitance on VDDIO. See the CVDDIO parameter in Power
Management Module Electrical Data and Timing. The actual amount of decoupling capacitance to use is a
requirement of the power supply driving VDDIO. Either of the configurations outlined below is acceptable:
• Configuration 1: Place a decoupling capacitor on each VDDIO pin per the CVDDIO parameter.
• Configuration 2: Install a single decoupling capacitor that is the equivalent of CVDDIO * VDDIO pins.

Note
Having the decoupling capacitor or capacitors close to the device pins is critical.

6.13.1.3.1.2 VDD Decoupling

Place a minimum amount of decoupling capacitance on VDD. See the CVDD TOTAL parameter in Power
Management Module Electrical Data and Timing.

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In external VREG mode, the actual amount of decoupling capacitance to use is a requirement of the power
supply driving VDD.
Either of the configurations outlined below is acceptable:
• Configuration 1: Divide CVDD TOTAL equally across the VDD pins. In this configuration, the VDD pins may
be separated at the PCB level.
• Configuration 2: Install a single decoupling capacitor with value of CVDD TOTAL. In this configuration, all
VDD pins must be connected to each other on the PCB.

Note
Having the decoupling capacitor or capacitors close to the device pins is critical.

6.13.1.4 Power Sequencing

6.13.1.4.1 Supply Pins Ganging
ADVANCE INFORMATION

Connecting all 3.3-V rails together and supplying from a single source are strongly recommended. This list
includes:
• VDDIO
• VDDA
In addition, connect all power pins to avoid leaving any unconnected.
In external VREG mode, the VDD pins should be tied together and supplied from a single source.
In internal VREG mode, tying the VDD pins together is optional as long as each VDD pin has a capacitor
connected to pin. See the VDD Decoupling section for VDD decoupling configurations.
The analog modules on the device have fairly high PSRR; therefore, in most cases, noise on VDDA will
have to exceed the recommended operating conditions of the supply rails before the analog modules see
performance degradation. Therefore, supplying VDDA separately typically offers minimal benefits. Nevertheless,
for the purposes of noise improvement, placing a pi filter between VDDIO and VDDA is acceptable.

Note
All the supply pins per rail are tied together internally. For example, all VDDIO pins are tied together
internally, all VDD pins are tied together internally, and so forth.

6.13.1.4.2 Signal Pins Power Sequence

Before powering the device, do not apply voltage larger than 0.3 V above VDDIO or 0.3 V below VSS to any
digital pin and 0.3 V above VDDA or 0.3 V below VSSA to any analog pin (including VREFHI). Simply, the signal
pins should only be driven after XRSn goes high, provided all the 3.3-V rails are tied together. This sequencing is
still required even if VDDIO and VDDA are not tied together.

CAUTION
If the above sequence is violated, device malfunction and possibly damage can occur as current will
flow through unintended parasitic paths in the device.

6.13.1.4.3 Supply Pins Power Sequence

6.13.1.4.3.1 External VREG/VDD Mode Sequence

Figure 6-3 depicts the power sequencing requirements for external VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.

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VDDIO VDDIO
(A)
VBOR-VDDIO-UP VDD VDD VBOR-VDDIO-DN(B)
Internal Internal All
All Monitors Release Monitors Release
Signal(C) Signal(D)
XRSn XRSn
SRVDDIO-UP SRVDD-UP SRVDD-DN SRVDDIO-DN

VPOR-VDDIO VPOR-VDD-UP(A) VPOR-VDD-DN(B) VPOR-VDDIO

VDDIO - VDD
Delay

VDDIO-MON-TOT-DELAY VXRSn-PU-DELAY VXRSn-PD-DELAY

A. This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table.
B. This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table.

ADVANCE INFORMATION
C. During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block
Diagram.
D. During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block
Diagram.

Figure 6-3. External VREG Power Up Sequence

• For Power Up:

1. VDDIO (that is, the 3.3-V rail) should come up first with the minimum slew rate specified.
2. VDD (that is, the 1.2-V rail) should come up next with the minimum slew rate specified.
3. The time delta between the VDDIO rail coming up and when the VDD rail can come up is also specified.
4. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PD-DELAY, XRSn will be released and the
device starts the boot-up sequence.
5. The I/O BOR monitor has different release points during power up and power down.
6. During power up, both VDDIO and VDD rails have to be up before XRSn releases.
• For Power Down:
1. There is no requirement between VDDIO and VDD on which should power down first; however, there is a
minimum slew rate specification.
2. The I/O BOR monitor has different release points during power up and power down.
3. Any of the POR or BOR monitors that trips during power down will cause XRSn to go low after
VXRSN-PD-DELAY.

Note
The All Monitors Release Signal is an internal signal.

Note
If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does not
start until the XRSn pin is released by all internal and external sources.

6.13.1.4.3.2 Internal VREG/VDD Mode Sequence

Figure 6-4 depicts the power sequencing requirements for internal VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.

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VDDIO VDDIO
(A)
VBOR-VDDIO-UP VBOR-VDDIO-DN(B)
Internal Internal All
All Monitors Release Monitors Release
Signal(C) Signal(D)
XRSn XRSn
SRVDDIO-UP SRVDDIO-DN

VPOR-VDDIO VPOR-VDDIO

VDDIO-MON-TOT-DELAY VXRSn-PU-DELAY VXRSn-PD-DELAY

A. This trip point is the trip point before XRSn releases. See the Power Management Module Characteristics table.
B. This trip point is the trip point after XRSn releases. See the Power Management Module Characteristics table.
ADVANCE INFORMATION

C. During power up, the All Monitors Release Signal goes high after all POR and BOR monitors are released. See the PMM Block
Diagram.
D. During power down, the All Monitors Release Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block
Diagram.

Figure 6-4. Internal VREG Power Up Sequence

• For Power Up:

1. VDDIO (that is, the 3.3-V rail) should come up with the minimum slew rate specified.
2. The Internal VREG powers up after the I/O monitors (I/O POR and I/O BOR) are released.
3. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PU-DELAY, XRSn will be released and the
device starts the boot-up sequence.
4. The I/O BOR monitor has different release points during power up and power down.
• For Power Down:
1. The only requirement on VDDIO during power down is the slew rate.
2. The I/O BOR monitor has different release points during power up and power down.
3. The I/O BOR tripping will cause XRSn to go low after VXRSN-PD-DELAY and also power down the Internal
VREG.

Note
The All Monitors Release Signal is an internal signal.

Note
If there is an external circuit driving XRSn (for example, a supervisor), the boot-up sequence does not
start until the XRSn pin is released by all internal and external sources.

6.13.1.4.3.3 Supply Sequencing Summary and Effects of Violations

The acceptable power-up sequence for the rails is summarized below. "Power up" here means the rail in
question has reached the minimum recommended operating voltage.

CAUTION
Non-acceptable sequences leads to reliability concerns and possibly damage.

For simplicity, connecting all 3.3-V rails together and following the descriptions in Supply Pins Power Sequence
is recommended.

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Table 6-1. External VREG Sequence Summary
RAILS POWER-UP ORDER
CASE ACCEPTABLE
VDDIO VDDA VDD
A 1 2 3 Yes
B 1 3 2 Yes
C 2 1 3 -
D 2 3 1 -
E 3 2 1 -
F 3 1 2 -
G 1 1 2 Yes
H 2 2 1 -

Table 6-2. Internal VREG Sequence Summary

ADVANCE INFORMATION
RAILS POWER-UP ORDER
CASE ACCEPTABLE
VDDIO VDDA
A 1 2 Yes
B 2 1 -
C 1 1 Yes

Note
The analog modules on the device should only be powered after VDDA has reached the minimum
recommended operating voltage.

6.13.1.4.3.4 Supply Slew Rate

VDDIO has a minimum slew rate requirement. If the minimum slew rate is not met, XRSn might toggle a few
times until VDDIO crosses the I/O BOR region.

Note
The toggling on XRSn has no adverse effect on the device as boot only starts once XRSn is steadily
high. However if XRSn from the device is used to gate the reset signal of other ICs, then the slew rate
requirement should be met to prevent this toggling.

VDD has a minimum slew rate requirement in external VREG mode. If the minimum slew rate is not met, the
VDD POR may release before the VDD operational minimum voltage is met and the device may not start in a
properly reset state.

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6.13.1.5 Power Management Module Electrical Data and Timing

6.13.1.5.1 Power Management Module Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General
VDDIO Capacitance Per
CVDDIO (1) (2) 0.1 uF
Pin(7)
CVDDA (1) (2) VDDA Capacitance Per Pin(7) 2.2 uF
Supply Ramp Rate of 3.3V
SRVDD33 (3) 20 100 mV/us
Rails (VDDIO, VDDA)
VBOR-VDDIO-GB VDDIO Brown Out Reset
(5) 0.1 V
Voltage Guardband
External VREG
ADVANCE INFORMATION

CVDD
Total VDD Capacitance(7) 10 uF
TOTAL(1) (4)
Supply Ramp Rate of 1.2V
SRVDD12 (3) 10 100 mV/us
Rail (VDD)
VDDIO - VDD Ramp Delay Between VDDIO
0 us
Delay(6) and VDD
Internal VREG
CVDD Total Nominal VDD
10 22 uF
TOTAL(1) (4) Capacitance(7)

(1) A bulk capacitor should also be used. The exact value of the decoupling capacitance depends on the system voltage regulation
solution that is supplying these pins.
(2) It is recommended to tie the 3.3V rails (VDDIO, VDDA) together and supply them from a single source.
(3) See the Supply Slew Rate section. Supply ramp rate faster than the maximum can trigger the on-chip ESD protection.
(4) See the Power Management Module (PMM) section on possible configurations for the total decoupling capacitance.
(5) TI recommends VBOR-VDDIO-GB to avoid BOR-VDDIO resets due to normal supply noise or load-transient events on the 3.3-V VDDIO
system regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are
important to prevent activation of the BOR-VDDIO during normal device operation. The value of VBOR-VDDIO-GB is a system-level design
consideration; the voltage listed here is typical for many applications.
(6) Delay between when the 3.3-V rail ramps up and when the 1.2-V rail ramps up. See the VREG Sequence Summary table for the
allowable supply ramp sequences.
(7) Max capacitor tolerance should be 20%.

6.13.1.5.2 Power Management Module Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal Voltage Regulator
VVREG 1.152 1.2 1.248 V
Output
Internal Voltage Regulator
VVREG-PU 350 us
Power Up Time
VVREG-INRUSH Internal Voltage Regulator
(4) 650 mA
Inrush Current
VDDIO Power on Reset Before and After XRSn
VPOR-VDDIO 2.3 V
Voltage Release
VBOR-VDDIO-UP VDDIO Brown Out Reset
(1) Before XRSn Release 2.7 V
Voltage on Ramp Up
VBOR-VDDIO- VDDIO Brown Out Reset
(1) After XRSn Release 2.81 3.0 V
DOWN Voltage on Ramp Down
XRSn Release Delay after
VXRSn-PU-
(2) Supplies are Ramped Up 40 us
DELAY
During Power-Up

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6.13.1.5.2 Power Management Module Characteristics (continued)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
XRSn Trip Delay after
VXRSn-PD-
(3) Supplies are Ramped Down 2 us
DELAY
During Power-Down
VDDIO-MON- Total Delays in Path of
80 us
TOT-DELAY VDDIO Monitors (POR, BOR)
XRSn Release Delay after a
40 us
VDD POR Event
VXRSn-MON- XRSn Release Delay after a Supplies Within Operating
40 us
RELEASE-DELAY VDDIO BOR Event Range
XRSn Release Delay after a
120 us
VDDIO POR Event

ADVANCE INFORMATION
(1) See the I/O BOR Operating Region figure.
(2) Supplies are considered fully ramped up after they cross the minimum recommended operating conditions for the respective rail. All
POR and BOR monitors need to be released before this delay takes effect.
(3) On power down, any of the POR or BOR monitors that trips will immediately trip XRSn. This delay is the time between any of the POR,
BOR monitors tripping and XRSn going low. It is variable and depends on the ramp down rate of the supply.
(4) This is the transient current drawn on the VDDIO rail when the internal VREG turns on. Due to this, there might be some voltage drops
on the VDDIO rail when the VREG turns on which could cause the VREG to ramp up in steps. There is no detriment to the device from
this but the effect can be reduced if desired by using sufficient decoupling capacitors on VDDIO or picking an LDO/DC-DC that can
supply this transient current.

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6.13.2 Reset Timing

XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR) and brown-out reset (BOR) monitors. During power up, the monitor circuits keep the XRSn pin low.
For more details, see the Power Management Module (PMM) section. A watchdog or NMI watchdog reset will
also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should
be placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow
the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 6-5 shows the recommended reset circuit.
VDDIO

2.2 kW to 10 kW
ADVANCE INFORMATION

Optional open-drain
XRSn
Reset source
£100 nF

Figure 6-5. Reset Circuit

6.13.2.1 Reset Sources

The Reset Signals table summarizes the various reset signals and their effect on the device.
Table 6-3. Reset Signals
Reset Source CPU Core Reset Peripherals JTAG / Debug IOs XRS Output
(C28x, FPU, TMU) Reset Logic Reset
POR Yes Yes Yes Hi-Z Yes
BOR Yes Yes Yes Hi-Z Yes
XRS Pin Yes Yes No Hi-Z -
WDRS Yes Yes No Hi-Z Yes
NMIWDRS Yes Yes No Hi-Z Yes
SYSRS (Debugger Reset) Yes Yes No Hi-Z No
SCCRESET Yes Yes No Hi-Z No
SIMRESET. XRS Yes Yes No Hi-Z Yes
SIMRESET. CPU1RS Yes Yes No Hi-Z No

The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual.

CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP.

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6.13.2.2 Reset Electrical Data and Timing

6.13.2.2.1 Reset - XRSn - Timing Requirements
MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1.5 ms
tw(RSL2) Pulse duration, XRSn low on warm reset 3.2 µs

6.13.2.2.2 Reset - XRSn - Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(RSL1) Pulse duration, XRSn driven low by device after supplies are stable 100 µs
tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles
tboot-flash Boot-ROM execution time to first instruction fetch in flash 1.2 ms

ADVANCE INFORMATION
6.13.2.2.3 Reset Timing Diagrams

VDDIO VDDA
(3.3V)

VDD (1.2V)

tw(RSL1)

XRSn(A)
tboot-flash
Boot ROM

CPU
Execution
Phase
User code
th(boot-mode)(B) User code dependent

Boot-Mode GPIO pins as input

Pins
Boot-ROM execution starts Peripheral/GPIO function
Based on boot code

GPIO pins as input (pullups are disabled)

I/O Pins
User code dependent
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see the Pin Attributes table. On-chip monitors will
hold this pin low until the supplies are in a valid range.
B. After reset from any source (see the Reset Sources section), the boot ROM code samples Boot Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on
conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based
on user environment and could be with or without PLL enabled.

Figure 6-6. Power-on Reset

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tw(RSL2)

XRSn

User code
CPU
Execution User code Boot ROM
Phase
Boot ROM execution starts
(initiated by any reset source) th(boot-mode)(A)

Boot-Mode Peripheral/GPIO function GPIO Pins as Input Peripheral/GPIO function

Pins
User-Code Execution Starts
ADVANCE INFORMATION

I/O Pins User-Code Dependent GPIO Pins as Input (Pullups are Disabled)

User-Code Dependent
A. After reset from any source (see the Reset Sources section), the Boot ROM code samples BOOT Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on
conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be
based on user environment and could be with or without PLL enabled.

Figure 6-7. Warm Reset

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6.13.3 Clock Specifications

6.13.3.1 Clock Sources
Table 6-4. Possible Reference Clock Sources
CLOCK SOURCE DESCRIPTION
INTOSC1 Internal oscillator 1.
10-MHz internal oscillator.
INTOSC2(1) Internal oscillator 2.
10-MHz internal oscillator.
X1 (XTAL) External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.

(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).

ADVANCE INFORMATION

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WDCLK
Watchdog Timer

PERCLKDIVSEL.USBCLKDIV

CLBCLKCTL

/1
/2
. SYSCLK
USBBITCLK
.
.
/8

CLB_TILE_CLK
/1 or /2
PLLCLK
/1
/2
.
.
. CLB_REG_CLK
/8

SYSCLKDIVSEL

SYSCLK

SYS PLLSYSCLK
Divider NMIWD
PLLRAWCLK
INTOSC1 SYSPLL

OSCCLK
INTOSC2
ADVANCE INFORMATION

PLLCLKEN

X1 (XTAL)

OSCCLKRCSEL
CPUCLK
FPU
CPU
TMU

Boot ROM CLA ROM GSx RAMs

SYSCLK SYSCLK LSx RAMs
ePIE DCSM
FLASH XINT Mx RAMs
GPIO WD Message RAM
System Control

KDIV

Flash Wrapper Clock FLCLK

Flash Wrapper
Divider

One per SYSCLK peripheral

PCLKCRx ADC
CLA AES
CMPSS
PERx.SYSCLK CPUTIMERs CLB
GPDAC
EPWM ERAD
PGA
ECAP EPG
DCC
EQEP FSI
PMBUS
HRCAL I2C
USB

One per SYSCLK peripheral

LSPCLKDIV

PCLKCRx

LSPCLK PERx.LSPCLK SCI

LSP
Divider SPI

One per SYSCLK peripheral

LINACLKDIV
PCLKCRx

LINACLK PERx.LINACLK
LIN Clock LIN
Divider

One per SYSCLK peripheral

NNPUCLKDIV
PCLKCRx

NNPUCLK PERx.NNPUCLK
NNPU Clock NNPU
Divider

AUXCLKDIVSEL.MCANxCLKDIV

0 /1
Reserved 1 /2
.
MCAN Bit Clock
AUXCLKIN(GPIO29) .
2 .
PLLRAWCLK 3 /20

CLKSRCCTL2.MCANxBCLKSEL

Figure 6-8. Clocking System

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SYSPLL

OSCCLK ÷ INTCLK VCOCLK ÷ PLLRAWCLK

VCO
(REFDIV+1) (ODIV+1)

ADVANCE INFORMATION
÷
IMULT

Figure 6-9. System PLL

In the System PLL figure,

fOSCCLK
fPLLRAWCLK = × IMULT (1)
REFDIV + 1 ODIV + 1

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6.13.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
6.13.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
6.13.3.2.1.1 Input Clock Frequency
MIN MAX UNIT
f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz
f(X1) Frequency, X1, from external oscillator 10 25 MHz

6.13.3.2.1.2 XTAL Oscillator Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
ADVANCE INFORMATION

X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V

X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V

6.13.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
X1 VIL Valid low-level input voltage (Buffer) –0.3 0.3 * VDDIO V
X1 VIH Valid high-level input voltage (Buffer) 0.7 * VDDIO VDDIO + 0.3 V

6.13.3.2.1.4 X1 Timing Requirements

MIN MAX UNIT
tf(X1) Fall time, X1 6 ns
tr(X1) Rise time, X1 6 ns
tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55%
tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55%

6.13.3.2.1.5 AUXCLKIN Timing Requirements

MIN MAX UNIT
tf(AUXI) Fall time, AUXCLKIN 6 ns
tr(AUXI) Rise time, AUXCLKIN 6 ns
tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55%
tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55%

6.13.3.2.1.6 APLL Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
PLL Lock time
SYS PLL Lock Time(1) 5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)) us

(1) The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().

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6.13.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled

over recommended operating conditions (unless otherwise noted)
PARAMETER(1) MIN MAX UNIT
tf(XCO) Fall time, XCLKOUT 6 ns
tr(XCO) Rise time, XCLKOUT 6 ns
tw(XCOL) Pulse duration, XCLKOUT low H – 2(2) H + 2(2) ns
tw(XCOH) Pulse duration, XCLKOUT high H– 2(2) H+ 2(2) ns
f(XCO) Frequency, XCLKOUT 50 MHz

(1) A load of 6 pF is assumed for these parameters.

(2) H = 0.5tc(XCO)

6.13.3.2.1.8 Internal Clock Frequencies

ADVANCE INFORMATION
MIN NOM MAX UNIT
f(SYSCLK) Frequency, device (system) clock 2 150 MHz
tc(SYSCLK) Period, device (system) clock 6.67 500 ns
f(INTCLK) Frequency, system PLL going into VCO (after REFDIV) 2 20 MHz
f(VCOCLK) Frequency, system PLL VCO (before ODIV) 220 600 MHz
f(PLLRAWCLK) Frequency, system PLL output (before SYSCLK divider) 6 300 MHz
f(PLL) Frequency, PLLSYSCLK 2 150 MHz
f(PLL_LIMP) Frequency, PLL Limp Frequency (1) 45/(ODIV+1) MHz
f(LSP) Frequency, LSPCLK 2 150 MHz
tc(LSPCLK) Period, LSPCLK 6.67 500 ns
Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or
f(OSCCLK) See respective clock MHz
X1)
f(EPWM) Frequency, EPWMCLK 150 MHz
f(HRPWM) Frequency, HRPWMCLK 60 150 MHz

(1) PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).

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6.13.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
• A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 6-10,
with the XTALCR.SE bit set to 1.
• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 6-11.
• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 6-12.

Microcontroller Microcontroller

GPIO19 GPIO18* GPIO19 GPIO18

VSS X1 X2 VSS X1 X2
ADVANCE INFORMATION

* Available as a
+3.3 V
GPIO when X1 is
used as a clock

VDD Out

3.3-V Oscillator

Gnd

Figure 6-11. External Crystal

Figure 6-10. Single-ended 3.3-V External Clock
Microcontroller

GPIO19 GPIO18
VSS X1 X2

Figure 6-12. External Resonator

6.13.3.4 XTAL Oscillator

6.13.3.4.1 Introduction
The crystal oscillator in this device is an embedded electrical oscillator that, when paired with a compatible
quartz crystal (or a ceramic resonator), can generate the system clock required by the device.
6.13.3.4.2 Overview
The following sections describe the components of the electrical oscillator and crystal.
6.13.3.4.2.1 Electrical Oscillator
The electrical oscillator in this device is a Pierce oscillator. It is a positive feedback inverter circuit that requires a
tuning circuit in order to oscillate. When this oscillator is paired with a compatible crystal, a tank circuit is formed.
This tank circuit oscillates at the fundamental frequency of the crystal. On this device, the oscillator is designed
to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure
6-13 illustrates the components of the electrical oscillator and the tank circuit.

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MCU To Rest of Chip

XTAL Oscillator
Buffer

Comp

1
XCLKOUT
Circuit
[XTAL On]

Rbias

ADVANCE INFORMATION
XCLKOUT
Pierce Inverter
Internal Internal

GPIO
X1

X2
External External

Rd
Crystal

CL1 CL2

GND GND

Figure 6-13. Electrical Oscillator Block Diagram

6.13.3.4.2.1.1 Modes of Operation

The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode.
6.13.3.4.2.1.1.1 Crystal Mode of Operation
In the crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2.
This mode of operation is engaged when [XTAL On] = 1, which is achieved by setting XTALCR.OSCOFF = 0
and XTALCR.SE = 0. There is an internal bias resistor for the feedback loop so an external one should not be
used. Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias
point of operation and possibly leading to clipped waveforms, out-of-specification duty cycle, and reduction in the
effective negative resistance.
In this mode of operation, the resultant clock on X1 is passed through a comparator (Comp) to the rest of the
chip. The clock on X1 needs to meet the VIH and VIL of the comparator. See the XTAL Oscillator Characteristics
table for the VIH and VIL requirements of the comparator.
6.13.3.4.2.1.1.2 Single-Ended Mode of Operation
In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz
crystal should not be used in this mode.
This mode is enabled when [XTAL On] = 0, which can be achieved by setting XTALCR.OSCOFF = 1 and
XTALCR.SE = 1.

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In this mode of operation, the clock on X1 is passed through a buffer (Buffer) to the rest of the chip. See
the X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input
requirements of the buffer.
6.13.3.4.2.1.2 XTAL Output on XCLKOUT
The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for
observation by configuring the CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers.
See the GPIO Muxed Pins table for a list of GPIOs that XCLKOUT comes out on.
6.13.3.4.2.2 Quartz Crystal
Electrically, a quartz crystal can be represented by an LCR (Inductor-Capacitor-Resistor) circuit. However, unlike
an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped.
Components of the crystal are shown in Figure 6-14 and explained below.
Quartz Crystal
ADVANCE INFORMATION

Internal External

Cm

Rm C0 CL

Lm

Figure 6-14. Crystal Electrical Representation

Cm (Motional capacitance): Denotes the elasticity of the crystal.

Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but
can be approximated as such depending on the values of the other crystal components.
Lm (Motional inductance): Denotes the vibrating mass of the crystal.
C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package
capacitance.
CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external to
the crystal. The frequency ppm specified in the crystal data sheet is usually tied to the CL parameter.
Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins, while
some crystal manufacturers specify CL as the capacitance on just one of the crystal pins. Check with the crystal
manufacturer for how the CL is specified in order to use the correct values in calculations.
From Figure 6-13, CL1 and CL2 are in series; so, to find the equivalent total capacitance seen by the crystal, the
capacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1 = CL2.
It is recommended that a stray PCB capacitance be added to this value. 3 pF to 5 pF are reasonable estimates,
but the actual value will depend on the PCB in question.
Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has
to satisfy both the electrical oscillator and the crystal.

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The effect of CL on the crystal is frequency-pulling. If the effective load capacitance is lower than the target, the
crystal frequency will increase and vice versa. However, the effect of frequency-pulling is usually very minimal
and typically results in less than 10-ppm variation from the nominal frequency.
6.13.3.4.2.3 GPIO Modes of Operation
On this device, X1 and X2 can be used as GPIO19 and GPIO18, respectively, depending on the operating mode
of the XTAL. Refer to the External Oscillator (XTAL) section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual .
6.13.3.4.3 Functional Operation

6.13.3.4.3.1 ESR – Effective Series Resistance

Effective Series Resistance is the resistive load the crystal presents to the electrical oscillator at resonance. The
higher the ESR, the lower the Q, and less likely the crystal will start up or maintain oscillation. The relationship

ADVANCE INFORMATION
between ESR and the crystal components is indicated below.

2
ESR = Rm * 1 + C0
CL (2)

Note that ESR is not the same as motional resistance of the crystal, but can be approximated as such if the
effective load capacitance is much greater than the shunt capacitance.
6.13.3.4.3.2 Rneg – Negative Resistance
Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount of
energy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. Rneg
depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of the
circuit.
The generally accepted practice is to have Rneg > 3x ESR to 5x ESR to ensure the crystal starts up under
all conditions. Note that it takes slightly more energy to start up the crystal than it does to sustain oscillation;
therefore, if it can be ensured that the negative resistance requirement is met at start-up, then oscillation
sustenance will not be an issue.
Figure 6-15 and Figure 6-16 show the variation between negative resistance and the crystal components for this
device. As can be seen from the graphs, the crystal shunt capacitance (C0) and effective load capacitance (CL)
greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs; so, refer to
Table 6-5 for minimum and maximum values for design considerations.
6.13.3.4.3.3 Start-up Time
Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned
in the Rneg – Negative Resistance section, for reliable start-up across all conditions, it is recommended that the
Rneg > 3x ESR to 5x ESR of the crystal.
Crystal ESR and the dampening resistor (Rd) greatly affect the start-up time. The higher the two values, the
longer the crystal takes to start up. Longer start-up times are usually a sign that the crystal and components are
not a correct match.
Refer to Crystal Oscillator Specifications for the typical start-up times. Note that the numbers specified here are
typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question and
the external components.
6.13.3.4.3.3.1 X1/X2 Precondition
On this device, the GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the
crystal if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a known
state before the XTAL is turned on. See the TMS320F28P55x Real-Time Microcontrollers Technical Reference
Manual for details.

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6.13.3.4.3.4 DL – Drive Level

Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The
maximum drive level specified in the crystal manufacturer’s data sheet is usually the maximum the crystal can
dissipate without damage or significant reduction in operating life. On the other hand, the drive level specified
by the electrical oscillator is the maximum power it can provide. The actual power provided by the electrical
oscillator is not necessarily the maximum power and depends on the crystal and board components.
For cases where the actual drive level from the electrical oscillator exceeds the maximum drive level
specification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce the
power dissipated by the crystal. Note that Rd reduces the circuit gain; and therefore, the actual value to use
should be evaluated to make sure all other conditions for start-up and sustained oscillation are met.
6.13.3.4.4 How to Choose a Crystal
Using Crystal Oscillator Specifications as a reference:
ADVANCE INFORMATION

1. Pick a crystal frequency (for example, 20 MHz).

2. Check that the ESR of the crystal <=50 Ω per specifications for 20 MHz.
3. Check that the load capacitance requirement of the crystal manufacturer is within 6 pF and 12 pF per
specifications for 20 MHz.
• As mentioned, CL1 and CL2 are in series; so, provided CL1 = CL2, effective load capacitance CL =
[CL1]/2.
• Adding board parasitics to this results in CL = [CL1]/2 + Cstray
4. Check that the maximum drive level of the crystal >= 1 mW. If this requirement is not met, a dampening
resistor Rd can be used. Refer to DL – Drive Level on other points to consider when using Rd.
6.13.3.4.5 Testing
It is recommended that the user have the crystal manufacturer completely characterize the crystal with their
board to ensure the crystal always starts up and maintains oscillation.
Below is a brief overview of some measurements that can be performed:
Due to how sensitive the crystal circuit is to capacitance, it is recommended that scope probes not be connected
to X1 and X2. If scope probes must be used to monitor X1/X2, an active probe with less than 1-pF input
capacitance should be used.
Frequency
1. Bring out the XTAL on XCLKOUT.
2. Measure this frequency as the crystal frequency.
Negative Resistance
1. Bring out the XTAL on XCLKOUT.
2. Place a potentiometer in series with the crystal between the load capacitors.
3. Increase the resistance of the potentiometer until the clock on XCLKOUT stops.
4. This resistance plus the crystal’s actual ESR is the negative resistance of the electrical oscillator.
Start-Up Time
1. Turn off the XTAL.
2. Bring out the XTAL on XCLKOUT.
3. Turn on the XTAL and measure how long it takes the clock on XCLKOUT to stay within 45% and 55% duty
cycle.
6.13.3.4.6 Common Problems and Debug Tips
Crystal Fails to Start Up
• Go through the How to Choose a Crystal section and make sure there are no violations.

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Crystal Takes a Long Time to Start Up

• If a dampening resistor Rd is installed, it is too high.
• If no dampening resistor is installed, either the crystal ESR is too high or the overall circuit gain is too low due
to high load capacitance.
6.13.3.4.7 Crystal Oscillator Specifications
6.13.3.4.7.1 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ESR MAX = 110 Ω
f = 10 MHz CL1 = CL2 = 24 pF 4 ms
Start-up C0 = 7 pF
time(1) ESR MAX = 50 Ω
f = 20 MHz CL1 = CL2 = 24 pF 2 ms
C0 = 7 pF

ADVANCE INFORMATION
Crystal drive level (DL) 1 mW

(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.

6.13.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements

For the Crystal Equivalent Series Resistance (ESR) Requirements table:
1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
2. ESR = Negative Resistance/3
Table 6-5. Crystal Equivalent Series Resistance (ESR) Requirements
MAXIMUM ESR (Ω) MAXIMUM ESR (Ω)
CRYSTAL FREQUENCY (MHz)
(CL1 = CL2 = 12 pF) (CL1 = CL2 = 24 pF)
10 55 110
12 50 95
14 50 90
16 45 75
18 45 65
20 45 50

Negative Resistance vs. 10MHz Crystal

3000
C0 (pF)
1
2500 3
5
7
Rneg (Ohms)

2000 9

1500

1000

500

0
2 4 6 8 10 12 14 16
Effective CL (pF)

Figure 6-15. Negative Resistance Variation at 10 MHz

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Negative Resistance vs. 20MHz Crystal

1600
C0 (pF)
1400 1
3
1200 5
7

Rneg (Ohms)
1000 9

800

600

400

200

0
2 4 6 8 10 12 14 16
Effective CL (pF)

Figure 6-16. Negative Resistance Variation at 20 MHz

ADVANCE INFORMATION

6.13.3.4.7.3 Crystal Oscillator Parameters

MIN MAX UNIT
CL1, CL2 Load capacitance 12 24 pF
C0 Crystal shunt capacitance 7 pF

6.13.3.4.7.4 Crystal Oscillator Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ESR MAX = 110 Ω
f = 10 MHz CL1 = CL2 = 24 pF 4 ms
Start-up C0 = 7 pF
time(1) ESR MAX = 50 Ω
f = 20 MHz CL1 = CL2 = 24 pF 2 ms
C0 = 7 pF
Crystal drive level (DL) 1 mW

(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.

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6.13.3.5 Internal Oscillators

To reduce production board costs and application development time, all devices contain two independent internal
oscillators, referred to as INTOSC1 and INTOSC2. By default, INTOSC2 is set as the source for the system
reference clock (OSCCLK) and INTOSC1 is set as the backup clock source.
Applications requiring tighter SCI baud rate matching can use the SCI baud tuning example
(baud_tune_via_uart) available in C2000Ware.
6.13.3.5.1 INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
PACKAGE TEST
PARAMETER PART MIN TYP MAX UNIT
SUFFIX CONDITIONS
-40°C to 125°C 9.82 (–1.8%) 10 10.1 (1.0%)
Frequency, INTOSC1 and
fINTOSC All All -30°C to 90°C 9.86 (–1.4%) 10 10.1 (1.0%) MHz
INTOSC2(1)

ADVANCE INFORMATION
-10°C to 85°C 9.9 (–1.0%) 10 10.1 (1.0%)
fINTOSC- Frequency stability at room
All All 30°C, Nominal VDD ±0.1 %
STABILITY temperature
tINTOSC-ST Start-up and settling time All All 20 µs

(1) INTOSC frequency may shift due to the thermal and mechanical stress of solder reflow. A post-reflow bake can restore the unit to its
original data sheet performance.

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6.13.4 Flash Parameters

Table 6-6 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is
the value set in register FRDCNTL[RWAIT].
Table 6-6. Minimum Required Flash Wait States with Different Clock Sources and Frequencies
Wait States
CPUCLK (MHz)
(FRDCNTL[RWAIT](1))
120 < CPUCLK ≤ 150 3
80 < CPUCLK ≤ 120 2
0 < CPUCLK ≤ 80 1

(1) Minimum required FRDCNTL[RWAIT] is 1, RWAIT=0 is not supported.

The F28P55x devices have a 128-bit prefetch buffer that provides high flash code execution efficiency across
wait states. Figure 6-17 and Figure 6-18 illustrate typical efficiency across wait-state settings compared to
ADVANCE INFORMATION

previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer
will depend on how many branches are present in application software. Two examples of linear code and
if-then-else code are provided.

100% 100%

95%
90%
90%
80%
Efficiency (%)

Efficiency (%)

85%
70% 80%

60% 75%

Flash with 64-Bit Prefetch 70% Flash with 64-Bit Prefetch

50% Flash with 128-Bit Prefetch
Flash with 128-Bit Prefetch
65%
40%
60%

30% 55%
0 1 2 3 4 5 0 1 2 3 4 5
Wait State D005 Wait State D006

Figure 6-17. Application Code With Heavy 32-Bit Figure 6-18. Application Code With 16-Bit If-Else
Floating-Point Math Instructions Instructions

Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle.

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6.13.4.1 Flash Parameters

PARAMETER MIN TYP MAX UNIT
128 data bits + 16 ECC bits 62.5 625 µs
Program Time(1)
2KB (Sector) 8 80 µs
2KB (Sector) 15 55 ms
64KB 17 61 ms
Erase Time(2) (3) at < 25 cycles
128KB 18 66 ms
256KB 21 78 ms
2KB (Sector) 25 130 ms
64KB 28 143 ms
Erase Time(2) (3) at 1000 cycles
128KB 30 157 ms
256KB 35 183 ms

ADVANCE INFORMATION
2KB (Sector) 30 221 ms
64KB 33 243 ms
Erase Time(2) (3) at 2000 cycles
128KB 36 265 ms
256KB 42 310 ms
2KB (Sector) 120 1003 ms
64KB 132 1102 ms
Erase Time(2) (3) at 20K cycles
128KB 145 1205 ms
256KB 169 1410 ms
Nwec Write/Erase Cycles per Bank (4) 100000 cycles
tretention Data retention duration at TJ = 85oC 20 years

(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(4) The combined total of bank and sector write/erase cycles is limited to this number

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6.13.5 RAM Specifications

All volatile memory (RAM and ROM) on the F28P55x device is 0 Wait-state for both reads and writes, meaning
the memory operates at the same speed as SYSCLK. Table 6-7, Table 6-8, and Table 6-9 summarize the
characteristics of the different RAM instances on the device.
Table 6-7. RAM Parameters – F28P55xSJ
FETCH READ NUMBER OF NUMBER OF
STORE TIME BURST
RAM TYPE SIZE TIME(1) TIME(1) BUS WIDTH BUSES WAIT
(CYCLES) ACCESS
(CYCLES) (CYCLES) AVAILABLE STATES
LS RAM 64KB 2 2 1 16/32 bits 2 0 No
M0 2KB 2 2 1 16/32 bits 1 0 No
M1 2KB 2 2 1 16/32 bits 1 0 No
GS RAM 64KB 2 2 1 16/32 bits 3 0 No
CLA-to-CPU
ADVANCE INFORMATION

Message 256B 2 2 1 16/32 bits 2 0 No

RAM
CPU-to-CLA
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CLA-to-DMA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM
DMA-to-CLA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM

(1) Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.

Table 6-8. RAM Parameters – F28P55xSG

FETCH READ NUMBER OF NUMBER OF
STORE TIME BURST
RAM TYPE SIZE TIME(1) TIME(1) BUS WIDTH BUSES WAIT
(CYCLES) ACCESS
(CYCLES) (CYCLES) AVAILABLE STATES
LS RAM 64KB 2 2 1 16/32 bits 2 0 No
M0 2KB 2 2 1 16/32 bits 1 0 No
M1 2KB 2 2 1 16/32 bits 1 0 No
GS RAM 32KB 2 2 1 16/32 bits 2 0 No
CLA-to-CPU
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CPU-to-CLA
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CLA-to-DMA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM
DMA-to-CLA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM

(1) Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.

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Table 6-9. RAM Parameters – F28P55xSD

FETCH READ NUMBER OF NUMBER OF
STORE TIME BURST
RAM TYPE SIZE TIME(1) TIME(1) BUS WIDTH BUSES WAIT
(CYCLES) ACCESS
(CYCLES) (CYCLES) AVAILABLE STATES
LS RAM 32KB 2 2 1 16/32 bits 2 0 No
M0 2KB 2 2 1 16/32 bits 1 0 No
M1 2KB 2 2 1 16/32 bits 1 0 No
GS RAM 32KB 2 2 1 16/32 bits 2 0 No
CLA-to-CPU
Message 256B 2 2 1 16/32 bits 2 0 No
RAM
CPU-to-CLA
Message 256B 2 2 1 16/32 bits 2 0 No
RAM

ADVANCE INFORMATION
CLA-to-DMA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM
DMA-to-CLA
Message 256B 2 2 1 16/32 bits 3 0 No
RAM

(1) Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.

6.13.6 ROM Specifications

All volatile memory (RAM and ROM) on the F28P55x device is 0 Wait-state for both reads and writes, meaning
the memory operates at the same speed as SYSCLK. Table 6-10 summarizes the aspects of the ROM instances
on the device.
Table 6-10. ROM Parameters – F28P55xSJ, F28P55xSG, and F28P55xSD
FETCH READ NUMBER OF NUMBER OF
STORE TIME BURST
ROM TYPE SIZE TIME(1) TIME(1) BUS WIDTH BUSES WAIT
(CYCLES) ACCESS
(CYCLES) (CYCLES) AVAILABLE STATES
Boot ROM +
96KB 2 2 1 16/32 bits 1 0 No
Secure ROM
CLA Data
8KB 2 2 1 16/32 bits 2 0 No
ROM

(1) Without arbitration between read/write/fetch. Access completes in 2 cycles; otherwise, arbitration priority (Write/Read/Fetch) is
followed.

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6.13.7 Emulation/JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port has
four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for Reduced-Pin and
Enhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a compact JTAG interface
requiring only two pins (TMS and TCK), which allows other device functionality to be muxed to the traditional
GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
The PD (Power Detect) pin of the JTAG debug probe header should be connected to the board's 3.3-V supply.
Header GND pins should be connected to board ground. TDIS (Cable Disconnect Sense) should also be
ADVANCE INFORMATION

connected to board ground. The JTAG clock should be looped from the header TCK output pin back to the
RTCK input pin of the header (to sense clock continuity by the JTAG debug probe). This MCU does not support
the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should
always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to
4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
Header pin RESET is an open-drain output from the JTAG debug probe header that enables board components
to be reset through JTAG debug probe commands (available only through the 20-pin header). Figure 6-19 shows
how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 6-20 shows how to connect to
the 20-pin JTAG header. The 20-pin JTAG header pins EMU2, EMU3, and EMU4 are not used and should be
grounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
in CCS for C2000 devices.
For more information about JTAG emulation, see the XDS Target Connection Guide.

Note
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is disabled by
default. If this pin is used as JTAG TDI, the internal pullup should be enabled or an external pullup
added on the board to avoid a floating input. In the cJTAG option, this pin can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is disabled
by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this
pin floating. The internal pullup should be enabled or an external pullup added on the board to avoid a
floating GPIO input. In the cJTAG option, this pin can be used as GPIO.

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Distance between the header and the target

should be less than 6 inches (15.24 cm).
3.3 V

2.2 kΩ
1 2
TMS TMS TRST
3.3 V

10 kΩ
(A)
3 4
TDI TDI TDIS GND
MCU 3.3 V 100 Ω
5 6
3.3 V PD KEY
10 kΩ
(A)
7 8
TDO TDO GND
9 10

ADVANCE INFORMATION
RTCK GND
11 12
TCK TCK GND
4.7 kΩ 4.7 kΩ
3.3 V 13 EMU0 EMU1 14 3.3 V

A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.

Figure 6-19. Connecting to the 14-Pin JTAG Header

Distance between the header and the target

should be less than 6 inches (15.24 cm).

3.3 V

2.2 kΩ
1 2
TMS TMS TRST
3.3 V

10 kΩ
(A)
3 TDI TDIS 4 GND
MCU TDI
3.3 V 100 Ω
3.3V 5 PD KEY 6
10 kΩ
(A)
7 TDO GND 8
TDO
9 RTCK GND 10

TCK 11 TCK GND 12

4.7 kΩ 4.7 kΩ
3.3 V 13 EMU0 EMU1 14 3.3 V
15 RESET GND 16
Open
Drain 17 EMU2 EMU3 18

A low pulse from the JTAG debug probe 19 EMU4 GND 20

can be tied with other reset sources
to reset the board. GND GND
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.

Figure 6-20. Connecting to the 20-Pin JTAG Header

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6.13.7.1 JTAG Electrical Data and Timing

6.13.7.1.1 JTAG Timing Requirements
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 66.66 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.66 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 26.66 ns
tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 7
3 ns
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 7
th(TCKH-TDI) Input hold time, TDI valid from TCK high 7
4 ns
th(TCKH-TMS) Input hold time, TMS valid from TCK high 7

6.13.7.1.2 JTAG Switching Characteristics

ADVANCE INFORMATION

over recommended operating conditions (unless otherwise noted)

NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDO) Delay time, TCK low to TDO valid 6 20 ns

6.13.7.1.3 JTAG Timing Diagram

1
1a 1b

TCK

TDO

3 4

TDI/TMS

Figure 6-21. JTAG Timing

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6.13.7.2 cJTAG Electrical Data and Timing

6.13.7.2.1 cJTAG Timing Requirements
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 100 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 40 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 40 ns
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 7 ns
3
tsu(TMS-TCKL) Input setup time, TMS valid to TCK low 7 ns
th(TCKH-TMS) Input hold time, TMS valid from TCK high 2 ns
4
th(TCKL-TMS) Input hold time, TMS valid from TCK low 2 ns

6.13.7.2.2 cJTAG Switching Characteristics

ADVANCE INFORMATION
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TMS) Delay time, TCK low to TMS valid 6 20 ns
5 tdis(TCKH-TMS) Delay time, TCK high to TMS disable 20 ns

6.13.7.2.3 cJTAG Timing Diagram

1
1a 1b
2
3 4 3 4 5
TCK

TMS TMS Input TMS Input TMS Output

Figure 6-22. cJTAG Timing

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6.13.8 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to
a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input
X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts. For more details, see the X-BAR chapter in the TMS320F28P55x Real-Time
Microcontrollers Technical Reference Manual.
6.13.8.1 GPIO – Output Timing
6.13.8.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
ADVANCE INFORMATION

PARAMETER MIN MAX UNIT

tr(GPO) Rise time, GPIO switching low to high All GPIOs 6(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 6(1) ns
All GPIOs not listed
50
below
tfGPO Toggling frequency, GPIO pins MHz
GPIO 2, 3, 9, and 32 40
GPIO 23 and 41 25

(1) Rise time and fall time vary with load. These values assume a 6-pF load.

6.13.8.1.2 General-Purpose Output Timing Diagram

GPIO

tr(GPO)
tf(GPO)

Figure 6-23. General-Purpose Output Timing

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6.13.8.2 GPIO – Input Timing

6.13.8.2.1 General-Purpose Input Timing Requirements
MIN MAX UNIT
QUALPRD = 0 1tc(SYSCLK) cycles
tw(SP) Sampling period
QUALPRD ≠ 0 2tc(SYSCLK) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
Synchronous mode 2tc(SYSCLK) cycles
tw(GPI) (2) Pulse duration, GPIO low/high
With input qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

6.13.8.2.2 Sampling Mode

ADVANCE INFORMATION
(A)
GPIO Signal GPxQSELn = 1,0 (6 samples)

1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1

tw(SP) Sampling Period determined

(B)
by GPxCTRL[QUALPRD]
tw(IQSW)
(C)
Sampling Window (SYSCLK cycle * 2 * QUALPRD) * 5

SYSCLK

QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.

Figure 6-24. Sampling Mode

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6.13.8.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
ADVANCE INFORMATION

signal. This is determined by the value written to GPxQSELn register.

Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0

SYSCLK

GPIOxn

tw(GPI)

Figure 6-25. General-Purpose Input Timing

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6.13.9 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through
the enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to sixteen peripheral
interrupts into each CPU interrupt line. It also expands the vector table to allow each interrupt to have its own
ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 6-26 shows the interrupt architecture for this device.
TINT0
TIMER0

ADVANCE INFORMATION
LPM Logic LPMINT
WAKEINT
WDINT NMI module NMI
WD

INPUTXBAR4 XINT1 Control CPU

INPUTXBAR5 XINT2 Control
GPIO0 ePIE INT1
Input
to INPUTXBAR6 XINT3 Control to
X-BAR
GPIOx INT12
INPUTXBAR13 XINT4 Control
INPUTXBAR14 XINT5 Control

TIMER1 INT13

TIMER2 INT14
Peripherals
See ePIE Table

Figure 6-26. Device Interrupt Architecture

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6.13.9.1 External Interrupt (XINT) Electrical Data and Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.13.9.1.1 External Interrupt Timing Requirements
MIN MAX UNIT
Synchronous 2tc(SYSCLK) cycles
tw(INT) Pulse duration, INT input low/high
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles

6.13.9.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(1) tw(IQSW) + 14tc(SYSCLK) tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
ADVANCE INFORMATION

(1) This assumes that the ISR is in a single-cycle memory.

6.13.9.1.3 External Interrupt Timing

tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5

td(INT)

Address bus
Interrupt Vector
(internal)

Figure 6-27. External Interrupt Timing

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6.13.10 Low-Power Modes

This device has HALT, IDLE and STANDBY as clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the
Low-Power Modes section of the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
6.13.10.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 6-11 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 6-11. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
IDLE STANDBY HALT
CLOCK DOMAIN
SYSCLK Active Gated Gated

ADVANCE INFORMATION
CPUCLK Gated Gated Gated
Clock to modules connected Active Gated Gated
to PERx.SYSCLK
WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
PLL Powered Powered Software must power down PLL before entering HALT.
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash(1) Powered Powered Powered
XTAL(2) Powered Powered Powered

(1) The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the
application.
(2) The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.

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6.13.10.2 Low-Power Mode Wake-up Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.13.10.2.1 IDLE Mode Timing Requirements
MIN MAX UNIT
Without input qualifier 2tc(SYSCLK)
tw(WAKE) Pulse duration, external wake-up signal cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW)

6.13.10.2.2 IDLE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Without input qualifier 40tc(SYSCLK) cycles
From Flash (active state)
With input qualifier 40tc(SYSCLK) + tw(WAKE) cycles
ADVANCE INFORMATION

Delay time, external wake signal to

td(WAKE-IDLE)
program execution resume(1) Without input qualifier 25tc(SYSCLK) cycles
From RAM
With input qualifier 25tc(SYSCLK) + tw(WAKE) cycles

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.

6.13.10.2.3 IDLE Entry and Exit Timing Diagram

td(WAKE-IDLE)
Address/Data
(internal)

XCLKOUT

tw(WAKE)
(A)
WAKE

A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.

Figure 6-28. IDLE Entry and Exit Timing Diagram

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6.13.10.2.4 STANDBY Mode Timing Requirements

MIN MAX UNIT
QUALSTDBY = 0 | 2tc(OSCCLK) 3tc(OSCCLK)
Pulse duration, external
tw(WAKE-INT) QUALSTDBY > 0 | cycles
wake-up signal (2 + QUALSTDBY) * tc(OSCCLK)
(2 + QUALSTDBY)tc(OSCCLK) (1)

(1) QUALSTDBY is a 6-bit field in the LPMCR register.

6.13.10.2.5 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Delay time, IDLE instruction executed to

ADVANCE INFORMATION
td(IDLE-XCOS) 16tc(INTOSC1) cycles
XCLKOUT stop
Wakeup from flash
td(WAKE-STBY) Delay time, external wake signal to program (Flash module in 175tc(SYSCLK) + tw(WAKE-INT) cycles
execution resume(1) active state)
td(WAKE-STBY) Wakeup from RAM 3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.

6.13.10.2.6 STANDBY Entry and Exit Timing Diagram

(A) (C) (F)
(B) (D)(E) (G)

Device STANDBY STANDBY Normal Execution

Status
Flushing Pipeline

Wake-up
Signal

tw(WAKE-INT)

td(WAKE-STBY)

OSCCLK

XCLKOUT

td(IDLE-XCOS)

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 6-29. STANDBY Entry and Exit Timing Diagram

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6.13.10.2.7 HALT Mode Timing Requirements

MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal(1) toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal(1) toscst + 8tc(OSCCLK) cycles

(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See the Crystal Oscillator (XTAL) section for more information. For applications using INTOSC1
or INTOSC2 for OSCCLK, see the Internal Oscillators section for toscst. Oscillator start-up time does not apply to applications using a
single-ended crystal on the X1 pin, as it is powered externally to the device.

6.13.10.2.8 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
ADVANCE INFORMATION

PARAMETER MIN MAX UNIT

Delay time, IDLE instruction executed to XCLKOUT
td(IDLE-XCOS) 16tc(INTOSC1) cycles
stop
Delay time, external wake signal end to CPU1 program
execution resume
td(WAKE-HALT) cycles
Wakeup from Flash - Flash module in active state 75tc(OSCCLK)
Wakeup from RAM 75tc(OSCCLK)

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6.13.10.2.9 HALT Entry and Exit Timing Diagram

(A) (C) (F)
(B) (D)(E) (G)

Device
HALT HALT
Status

Flushing Pipeline Normal

Execution

GPIOn

td(WAKE-HALT)
tw(WAKE-GPIO)

OSCCLK

Oscillator Start-up Time

XCLKOUT

td(IDLE-XCOS)

A. IDLE instruction is executed to put the device into HALT mode.

ADVANCE INFORMATION
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock
source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible
to keep the internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up
sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean
clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure,
care should be taken to maintain a low noise environment before entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

Figure 6-30. HALT Entry and Exit Timing Diagram

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6.14 Analog Peripherals

The analog subsystem module is described in this section.
The analog modules on this device include the Analog-to-Digital Converter (ADC), temperature sensor,
Comparator Subsystem (CMPSS), Programmable Gain Amplifier (PGA), and buffered Digital-to-Analog
Converter (DAC).
The analog subsystem has the following features:
• Flexible voltage references
– The ADCs are referenced to VREFHIx and VSSA pins
• VREFHIx pin voltage can be driven in externally or can be generated by an internal bandgap voltage
reference
• The internal voltage reference range can be selected to be 0 V to 3.3 V or 0 V to 2.5 V
– The buffered DACs are referenced to VREFHIx and VSSA
ADVANCE INFORMATION

– The comparator DACs are referenced to VDDA and VSSA

• Flexible pin usage
– Buffered DAC outputs, comparator subsystem inputs, and digital inputs (AIOs)/outputs (AGPIOs) are
multiplexed with ADC inputs
– Internal connection to VREFLO on all ADCs for offset self-calibration
6.14.1 Block Diagram
The following analog subsystem block diagrams show the connections between the different integrated analog
modules to the device pins. These pins fall into two categories: analog module inputs/outputs and reference
pins.
The reference pins, VREFHI and VREFLO, can be used to supply an external voltage reference to the
associated ADCs. VREFHI can also be used to supply the voltage reference to buffered DAC. The choice
of reference is configurable per module for each CMPSS or buffered DAC; the selection is made using the
module's configuration registers.
Some analog pins support digital functionality through muxed AIOs and AGPIOs. AIOs only support digital input
functionality, while AGPIOs support full digital input and output functionality.
The following notes apply to all packages:
• Not all analog pins are available on all devices. See the device data manual to determine which pins are
available.
• See the device data manual to determine the allowable voltage range for VREFHI and VREFLO.
• An external capacitor is required on the VREFHI pins. See the device data manual for the specific value
required.

Figure 6-31 shows the Analog Subsystem Block Diagram for the 128-/80-pin TQFP, the 64-pin LQFP, and the
56-pin VQFN.
Figure 6-32 shows the Analog Subsystem Block Diagram for the 100-pin LQFP.
Figure 6-33 shows the general overview of the analog group connections.
The analog pins and internal connections are given in Analog Pins and Internal Connections. Analog Signal
Descriptions lists descriptions of analog signals.

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VREFHI CMP1_HP Comparator Subsystem 1 CMPSS Module

VREFLO Digital CTRIP1H
CMP1_HN Filter
ADC Module
VDDA CTRIPOUT1H
Reference Circuit
Misc. Analog DAC12
Buffered DAC Module
ANAREFSEL
Temp Sensor DAC12 Digital CTRIP1L
CMP1_LN CMPSS Input MUX
(C12) Vref Filter CTRIPOUT1L
CMP1_LP Temp Sensor
REFLO
CMP2_HP Comparator Subsystem 2 Analog Interconnect
Digital CTRIP2H
A15 HPMXSEL3/HNMXSEL0 /LPMXSEL3/LNMXSEL0 CMP2_HN VDDA Filter CTRIPOUT2H Reference Circuit
A1/B7/D11/DACB_OUT HPMXSEL4/ /LPMXSEL4/
(64/80/128-pin) A6/D14/E14 HPMXSEL2/ /LPMXSEL2/ REFHI DAC12
ADC Inputs

Input MUX
A2/B6/C9/PGA1_INP HPMXSEL0/ /LPMXSEL0/ DAC12
A0 to A30 Digital CTRIP2L
A11/B10/C0/PGA2_OUT HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1 ADC-A CMP2_LN
Filter
(128-pin) B5/D15/E15 HPMXSEL5/ /LPMXSEL5/ CTRIPOUT2L
AGPIO
12-bits

Analog Interconnect
AGPIO
AGPIO CMP2_LP
AIO
AIO
CMPSS1 Input MUX AIO Comparator Subsystem 3
REFLO CMP3_HP
Digital CTRIP3H
A10/B1/C10 HPMXSEL2/HNMXSEL0/LPMXSEL2/LNMXSEL0
HPMXSEL1/ /LPMXSEL1/ CMP3_HN VDDA Filter CTRIPOUT3H
A9
A12 HPMXSEL0/HNMXSEL1/LPMXSEL0/LNMXSEL1
DAC12
A5 HPMXSEL4/ /LPMXSEL4/
REFHI
DAC12 Digital CTRIP3L
ADC Inputs

Input MUX
AGPIO
AGPIO
CMP3_LN
AGPIO
B0 to B30 Filter CTRIPOUT3L
AIO
AIO
ADC-B
CMPSS2 Input MUX AIO CMP3_LP
12-bits
(64/80/128-pin) B2/C6/E12 HPMXSEL0/ /LPMXSEL0/ CMP4_HP Comparator Subsystem 4
B3/PGA2_INP HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 REFLO Digital CTRIP4H
A14/B14/C4/PGA1_OUT HPMXSEL4/ /LPMXSEL4/ CMP4_HN VDDA Filter CTRIPOUT4H
B12/C2/PGA2_INM HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A3 HPMXSEL5/ /LPMXSEL5/ DAC12
AGPIO
AGPIO
A0/B15/C15/DACA_OUT HPMXSEL2/ /LPMXSEL2/ AGPIO

ADVANCE INFORMATION
REFHI DAC12 Digital CTRIP4L
CMPSS3 Input MUX
AIO
AIO
AIO
CMP4_LN
ADC Inputs Filter CTRIPOUT4L

Input MUX
C0 to C30 ADC-C
B4/C8 HPMXSEL0/ /LPMXSEL0/ CMP4_LP
C14 HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 12-bits
C1/E11/PGA3_INP HPMXSEL2/ /LPMXSEL2/
A8/B0/C11 HPMXSEL4/ /LPMXSEL4/
REFLO
(128-pin) B11/D16/E16 HPMXSEL5/ /LPMXSEL5/
A7/C3/D12/B30/E30 HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
AGPIO
AGPIO
AGPIO
CMPSS4 Input MUX AIO
AIO
AIO
REFHI
ADC Inputs
Input MUX
D0 to D30 ADC-D
12-bits

REFLO

REFHI
ADC Inputs
Input MUX

E0 to E30 ADC-E
12-bits

REFLO
CMPSS Inputs

VREFHI

DACA_OUT 12-bit
Buffered
DAC-A

Figure 6-31. Analog Subsystem Block Diagram (128-/80-/64-/56-Pin Packages)

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VREFHI CMP1_HP Comparator Subsystem 1 CMPSS Module

VREFLO Digital CTRIP1H
CMP1_HN VDDA Filter CTRIPOUT1H
ADC Module
Reference Circuit
DAC12 Buffered DAC Module
ANAREFSEL
Misc. Analog DAC12 Digital CTRIP1L
CMP1_LN CMPSS Input MUX
Temp Sensor Filter CTRIPOUT1L
Vref
(C12) CMP1_LP Temp Sensor
REFLO
CMP2_HP Comparator Subsystem 2 Analog Interconnect
Digital CTRIP2H
CMP2_HN VDDA Filter CTRIPOUT2H Reference Circuit
A1/B7/D11/DACB_OUT HPMXSEL4/ /LPMXSEL4/
A6/D14/E14 HPMXSEL2/ /LPMXSEL2/ REFHI DAC12
ADC Inputs

Input MUX
A2/B6/C9/PGA1_INP HPMXSEL0/ /LPMXSEL0/ DAC12
A0 to A30 Digital CTRIP2L
A11/B10/C0/PGA2_OUT HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1 ADC-A CMP2_LN
Filter
B5/D15/E15 HPMXSEL5/ /LPMXSEL5/ CTRIPOUT2L
AGPIO
12-bits

Analog Interconnect
AGPIO
AGPIO CMP2_LP
AIO
AIO
CMPSS1 Input MUX AIO Comparator Subsystem 3
REFLO CMP3_HP
Digital CTRIP3H
A10/B1/C10 HPMXSEL2/HNMXSEL0/LPMXSEL2/LNMXSEL0
HPMXSEL1/ /LPMXSEL1/
CMP3_HN VDDA Filter CTRIPOUT3H
A9
B0/C11 HPMXSEL3/ /LPMXSEL3/
DAC12
A12 HPMXSEL0/HNMXSEL1/LPMXSEL0/LNMXSEL1
REFHI
A5 HPMXSEL5/ /LPMXSEL5/ DAC12 Digital CTRIP3L
ADC Inputs CMP3_LN

Input MUX
AGPIO
AGPIO
AGPIO
B0 to B30 Filter CTRIPOUT3L
AIO
AIO
ADC-B
CMPSS2 Input MUX AIO CMP3_LP
12-bits
B2/C6/E12 HPMXSEL0/ /LPMXSEL0/ CMP4_HP Comparator Subsystem 4
B3/PGA2_INP HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 REFLO Digital CTRIP4H
A14/B14/C4/PGA1_OUT HPMXSEL4/ /LPMXSEL4/ CMP4_HN VDDA Filter CTRIPOUT4H
B12/C2/PGA2_INM HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A3 HPMXSEL5/ /LPMXSEL5/ DAC12
AGPIO
AGPIO
A0/B15/C15/DACA_OUT HPMXSEL2/ /LPMXSEL2/ AGPIO
DAC12
ADVANCE INFORMATION

AIO REFHI CMP4_LN Digital CTRIP4L

CMPSS3 Input MUX AIO
AIO ADC Inputs Filter CTRIPOUT4L

Input MUX
C0 to C30 ADC-C
B4/C8 HPMXSEL0/ /LPMXSEL0/ CMP4_LP
C14 HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0 12-bits
C1/E11/PGA3_INP HPMXSEL2/ /LPMXSEL2/
A8/B0/C11 HPMXSEL4/ /LPMXSEL4/
REFLO
B11/D16/E16 HPMXSEL5/ /LPMXSEL5/
A7/B30/C3/D12/E30 HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
AGPIO
AGPIO
AGPIO
CMPSS4 Input MUX AIO
AIO
AIO
REFHI
ADC Inputs
Input MUX

D0 to D30 ADC-D
12-bits

REFLO

REFHI
ADC Inputs
Input MUX

E0 to E30 ADC-E
12-bits

REFLO
CMPSS Inputs

VREFHI

DACA_OUT 12-bit
Buffered
DAC-A

Figure 6-32. Analog Subsystem Block Diagram (100-Pin Package)

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CMPSSx Input MUX PGA Module

CMPSS Input MUX
CMPxHPMX
CMPx_HP0
0 AIO
CMPx_HP1
1
CMPx_HP2 AGPIO
2
CMPx_HP3
3 CMPx_HP
CMPx_HP4
4
CMPx_HP5 5
CMPx_HP6 6

CMPxHNMX
CMPx_HN0 0
CMPx_HN1 CMPx_HN
1

To CMPSSx
CMPxLNMX
CMPx_LN0 0
CMPx_LN1 CMPx_LN
1

CMPxLPMX

ADVANCE INFORMATION
CMPx_LP0
0
CMPx_LP1
1
CMPx_LP2
2
CMPx_LP3 CMPx_LP
3
CMPx_LP4 4
CMPx_LP5 5
CMPx_LP6 6

ADCA ADCA

AIO

AGPIO

ADCB ADCB

AIO

AGPIO
ADCC ADCC

AIO
TO Device Pins

AGPIO
To ADCs

ADCD ADCD

AIO

AGPIO

ADCE ADCE

AIO
PGAx_OUT

AGPIO
VDDA

PGAx_OUT_INT
PGAx_INP +
PGAx_INM
- PGAx_OUT

VSSA

Figure 6-33. Analog Group Connections

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Input connections to the CMPSS modules are selectable through a programmable input mux. Figure 6-33
demonstrates the connection between the input MUX of CMPSS modules, PGA modules, and ADC modules.
Table 6-12 shows the mapping of ADC input signals and PGA input and output signals to CMPSS mux inputs.
• To configure the CMPx_HP input mux for CMPSSx, write to the CMPxHPMXSEL field in the CMPHPMXSEL
analog subsystem register.
• To configure the CMPx_HN input mux for CMPSSx, write to the CMPxHNMXSEL field in the CMPHNMXSEL
analog subsystem register.
• To configure the CMPx_LP input mux for CMPSSx, write to the CMPxLPMXSEL field in the CMPLPMXSEL
analog subsystem register.
• To configure the CMPx_LN input mux for CMPSSx, write to the CMPxLNMXSEL field in the CMPLNMXSEL
analog subsystem register.
Table 6-12. CMPSS Input Mux Options
CMPSSx Input MUX CMP1 CMP2 CMP3 CMP4
ADVANCE INFORMATION

HP0 A2, B6, C9, PGA1_INP A4, B8 B2,C6, E12 B4, C8

HP1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, C3, D12, B30, E30,
HP2 A6, D14, E14(3) A9 A0, B15, C15, DACA_OUT C1, E11, PGA3_INP
A10, B1, C10
HP3 A15(2) B3, PGA2_INP C14
B0, C11(1)
A8
HP4 A1, B7, D11, DACB_OUT A14, B14, C4, PGA1_OUT
B0, C11(2)
HP5 B5, D15, E15(4) A5(1) A3 B11, D16, E16(4)
HP6 PGA1_OUT_INT PGA3_OUT_INT PGA2_OUT_INT
HP7 TEMP SENSOR
HN0 A15(2) A10, B1, C10 B3, PGA2_INP C14
HN1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, B30, C3, D12, E30
LP0 A2, B6, C9, PGA1_INP A4, B8 B2, C6, E12 B4, C8
LP1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, B30, C3, D12, E30
LP2 A6, D14, E14(3) A9 A0, B15, C15, DACA_OUT C1, E11, PGA3_INP
A10, B1, C10
LP3 A15(2) B3, PGA2_INP C14
B0, C11(1)
A8
LP4 A1, B7, D11, DACB_OUT A14, B14, C4, PGA1_OUT
B0, C11(2)
LP5 B5, D15, E15(4) A5(1) A3 B11, D16, E16(4)
LP6 PGA1_OUT_INT PGA3_OUT_INT PGA2_OUT_INT
LN0 A15 A10, B1, C10 B3, PGA2_INP C14
LN1 A11, B10, C0, PGA2_OUT A12 B12, C2, PGA2_INM A7, C3, D12, B30,E30

(1) These MUX options are available only on 100 QFP package.
(2) This MUX option is available only on 56 QFN, 64 QFP, 80 QFP, and 128 QFP packages.
(3) This MUX option is available only on 64 QFP, 80 QFP, 100 QFP, and 128 QFP packages.
(4) This MUX option is available only on 100 QFP and 128 QFP packages.

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6.14.2 Analog Pins and Internal Connections

Table 6-13. Analog Pins and Internal Connections
Pins/Package ADC Comparator Subsystem (MUX)
AIO Input/
Pin Name 128 100 80 64 56 DAC PGA High High Low Low
A B C D E AGPIO
QFP QFP QFP QFP QFN Positive Negative Positive Negative
31 24
VREFHI 20 16 14 - - - D20 E20
32 25
33 26
VREFLO 21 17 15 A13 B13 C13 D13 E13
34 27
Analog Group 1 CMP1
CMP1 CMP1 AGPIO228
A6/D14/E14 18 14 10 6 - A6 - - D14 E14 - - (3)
(HPMXSEL=2) (LPMXSEL=2)
CMP1 CMP1 AGPIO224
A2/B6/C9/PGA1_INP 21 17 13 9 7 A2 B6 C9 - - PGA1_INP - - (3)
(HPMXSEL=0) (LPMXSEL=0)

ADVANCE INFORMATION
CMP1 CMP1 CMP1 CMP1 AGPIO233
A15 - A15 - - (3)
22 14 10 8 - - (HPMXSEL=3) (HNMXSEL=0) (LPMXSEL=3) (LNMXSEL=0)
B9/C7/PGA1_INM 18 - B9 C7 PGA1_INM
CMP1 CMP1 CMP1 CMP1
A11/B10/C0/PGA2_OUT 27 20 16 12 10 A11 B10 C0 - - PGA2_OUT AIO237
(HPMXSEL=1) (HNMXSEL=1) (LPMXSEL=1) (LNMXSEL=1)
CMP1 CMP1
A1/B7/D11/DACB_OUT 29 22 18 14 12 A1 B7 - D11 - DACB_OUT - - AIO232
(HPMXSEL=4) (LPMXSEL=4)
CMP1 CMP1
B5/D15/E15 - - - - B5 D15 E15 - AIO252
38 32 - (HPMXSEL=5) - (LPMXSEL=5) -
PGA3_OUT 24 20 18 - - - PGA3_OUT
Analog Group 2 CMP2
CMP2 CMP2
A4/B8 42 36 27 23 21 A4 B8 - - - - - AIO225
(HPMXSEL=0) (LPMXSEL=0)
CMP2 CMP2
A12 35 28 22 18 16 A12 - - - - - - AIO238
(HPMXSEL=1) (LPMXSEL=1)
CMP2 CMP2 AGPIO227
A9 48 38 28 24 22 A9 - - - - - - (3)
(HPMXSEL=2) (LPMXSEL=2)
CMP2 CMP2 CMP2 CMP2 AGPIO230
A10/B1/C10 50 40 29 25 23 A10 B1 C10 - - (3)
(HPMXSEL=3) (HNMXSEL=0) (LPMXSEL=3) (LNMXSEL=0)
CMP2 CMP2 AGPIO231
B0/C11 - 41 - - - - B0 C11 - - (3)
(HPMXSEL=3) (LPMXSEL=3)
28 - 17 13 11 CMP2 CMP2
A5 A5 - - - - - - AIO249
- 35 - - - (HPMXSEL=5) (LPMXSEL=5)

Analog Group 3 CMP3

CMP3 CMP3 AGPIO226
B2/C6/E12 19 15 11 7 - - B2 C6 - E12 - - (3)
(HPMXSEL=0) (LPMXSEL=0)
CMP3 CMP3 CMP3 CMP3
B12/C2/PGA2_INM 28 21 17 13 11 - B12 C2 - - PGA2_INM AIO244
(HPMXSEL=1) (HNMXSEL=1) (LPMXSEL=1) (LNMXSEL=1)

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Table 6-13. Analog Pins and Internal Connections (continued)

Pins/Package ADC Comparator Subsystem (MUX)
AIO Input/
Pin Name 128 100 80 64 56 DAC PGA High High Low Low
A B C D E AGPIO
QFP QFP QFP QFP QFN Positive Negative Positive Negative
CMP3 CMP3
A0/B15/C15/DACA_OUT 30 23 19 15 13 A0 B15 C15 - - DACA_OUT - - AIO231
(HPMXSEL=2) (LPMXSEL=2)
CMP3 CMP3 CMP3 CMP3 AGPIO242
B3/PGA2_INP 16 B3 - (3)
20 12 8 6 - - - PGA2_INP (HPMXSEL=3) (HNMXSEL=0) (LPMXSEL=3) (LNMXSEL=0)
C5 28 - C5
CMP3 CMP3
A14/B14/C4/PGA1_OUT 26 19 15 11 9 A14 B14 C4 - - PGA1_OUT - - AIO239
(HPMXSEL=4) (LPMXSEL=4)
20 - 12 8 6 CMP3 CMP3
A3 A3 - - - - - -
- 18 - - - (HPMXSEL=5) (LPMXSEL=5) AIO229
Analog Group 4 CMP4
CMP4 CMP4 AGPIO236
B4/C8 49 39 28 24 22 - B4 C8 - - - -
ADVANCE INFORMATION

(HPMXSEL=0) (LPMXSEL=0) (3)

CMP4 CMP4
C1/E11/PGA3_INP 35 29 22 18 16 - - C1 - E11 PGA3_INP - - -
(HPMXSEL=2) (LPMXSEL=2)
CMP4 CMP4 CMP4 CMP4 AGPIO247
C14 42 42 27 23 21 - - C14 - - (3)
(HPMXSEL=3) (HNMXSEL=0) (LPMXSEL=3) (LNMXSEL=0)
B0/C11 39 - 24 20 18 - B0 C11 CMP4 CMP4 AIO241
- - - -
A8 - 37 - - - A8 - - (HPMXSEL=4) (LPMXSEL=4) AIO240
CMP4 CMP4
B11/D16/E16 36 30 - - - - B11 - D16 E16 - - AIO251
(HPMXSEL=5) (LPMXSEL=5)
PGA3_INM 36(1) 30(1) - - - - - PGA3_INM
23 19 17 CMP4 CMP4 CMP4 CMP4
A7/B30/C3/D12/E30 37 31 A7 B30 C3 D12 E30 AIO245
(HPMXSEL=1) (HNMXSEL=1) (LPMXSEL=1) (LNMXSEL=1)
Other Analog
CMP2
TempSensor(2) - - C12 - - - - - -
(HPMXSEL=7)
PGA1_OUT_I CMP1 CMP1
PGA1_OUT_INT(2) A21 B21 - - - - - -
NT (HPMXSEL=6) (LPMXSEL=6)
PGA2_OUT_I CMP3 CMP3
PGA2_OUT_INT(2) - B22 C21 - - - - -
NT (HPMXSEL=6) (LPMXSEL=6)
PGA3_OUT_I CMP2 CMP2
PGA3_OUT_INT(2) A22 - C22 - - - - -
NT (HPMXSEL=6) (LPMXSEL=6)

(1) Signal is bonded together with another signal as a single pin on this package.
(2) Internal connection only; does not come to a device pin.
(3) Only on 100 QFP package, AGPIO 247 is available.

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Note
The GPIOs on the analog pins support full digital input and output functionality and are referred to as AGPIOs. By default, the AGPIOs are
unconnected; that is, the analog and digital functions are both disabled. For configuration details, see the Digital Inputs and Outputs on ADC
Pins (AGPIOs) section.

ADVANCE INFORMATION
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6.14.3 Analog Signal Descriptions

Table 6-14. Analog Signal Descriptions
Signal Name Description
AIOx Digital input on ADC pin
AGPIOx Digital input/output pin with ADC functionality
ADCINAx, Ax ADC A Input
ADCINBx, Bx ADC B Input
ADCINCx, Cx ADC C Input
ADCINDx, Dx ADC D Input
ADCINEx, Ex ADC E Input
CMPx_HP Comparator subsystem high comparator positive input
CMPx_HN Comparator subsystem high comparator negative input
ADVANCE INFORMATION

CMPx_LP Comparator subsystem low comparator positive input

CMPx_LN Comparator subsystem low comparator negative input
DACA_OUT Buffered DAC Output
DACB_OUT CMPSS1 DAC Output
PGAx_INP PGA module non-inverting pin

PGAx_INM PGA module inverting pin

PGAx_OUT PGA module output
PGAx_OUT_INT PGA module internal output connected to CMPSS and ADC modules
TEMP SENSOR, TS Internal temperature sensor

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6.14.4 Analog-to-Digital Converter (ADC)

The ADC module described here is a successive approximation (SAR) style ADC with resolution of 12 bits.
This section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX,
the sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and other
analog support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic
for programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses,
post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of
the Analog-to-Digital Converter (ADC) chapter in the TMS320F28P55x Real-Time Microcontrollers Technical
Reference Manual).
Each ADC has the following features:

ADVANCE INFORMATION
• Resolution of 12 bits
• Ratiometric external reference set by VREFHI/VREFLO
• Selectable internal reference of 2.5 V or 3.3 V
• Single-ended signal mode
• Input multiplexer with up to 32 channels
• 16 configurable SOCs
• 16 individually addressable result registers
• External analog input mux selection per SOC, up to 4 bits
• Sample cap reset feature for memory crosstalk mitigation
• Multiple trigger sources
– Software immediate start
– All ePWMs: ADCSOC A or B
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
– ECAP events in capture mode (CEVT1, CEVT2, CEVT3, and CEVT4) and APWM mode (period match,
compare match, or both).
– Global software trigger for multiple ADCs
• Four flexible PIE interrupts
• Burst-mode triggering option
• Hardware oversampling mode up to 128x, with configurable trigger spread delay
• Hardware undersampling mode
• Trigger phase delay function
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Configurable digital filter for high/low/zero-crossing compare
– Trigger-to-sample delay capture
– Absolute value calculation
– 24-bit accumulation register for oversampling, with configurable binary shift
– Minimum/maximum calculation for outlier rejection

Note
Not every channel can be pinned out from all ADCs. See the Pin Configuration and Functions section
to determine which channels are available.

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The block diagram for the ADC core and ADC wrapper are shown in Figure 6-34.

ADCEXTMUX[3:0]
ADCCLK SYSCLK
Clock Prescaler Analog to Digital Control Logic
SIGNALMODE
SIGNALMODE
RESOLUTION Post Processing Block
RESOLUTION

SOCx (0-15) Analog to Digital Core

TRIGSEL
Triggers
CHSEL [15:0]
Reference Voltage Generator
[15:0] REPEATx (1-2)
ADCIN0 0 ACQPS Analog System Control
SOC Arbitration& TRIGSEL
ADCIN1 1 [15:0]
Control CHSEL MODE
ADCIN2 2 ADCSOC Input Circuit
NSEL
ADCIN3 3 [15:0]
EXTCHSEL PHASE
ADCIN4 4 SPREAD Converter
ADCIN5 5
ADCIN6 6 REPEATx (1-2)

...
...
ADCIN7 7 VIN+
ADCIN8 8 DOUT SOCxSTART[15:0] TRIGGER[15:0] SOCx (0-15)
ADCIN9 9 VIN-
ADCIN10 10 RESULT
ADCIN11 11 EOCx[15:0]
EOCx[15:0]
... ... S/H
ADVANCE INFORMATION

Circuit Converter
ADCIN29 29
FREECOUNT
ADCIN30 30
ADCIN31 31 ADCRESULT 0–15 Regs

Conversion Start Delay Sync

Calculation Logic

PPBxRESULT
Input Circuit Sample Correction
(OFFCAL, OFFREF, INV, ABS,
last-sample delta)
Analog to Digital Core
Oversampling and
Accumulation
(COUNT, SUM, MAX, MIN)
VREFHI ADCEVTINT
Limit Compare and Event
1 Logic, Digital Filters ADCEVT
Bandgap
Reference
0 ADCOSINT1
Circuit Post Processing Block (1-4)

Interrupt Block (1-4) ADCINT1-4

VREFLO Analog to Digital Control Logic ADCINT1-4_DMA

REFPMUXSEL

ANAREFx1P65SEL

Reference Voltage Generator Analog System Control

Figure 6-34. ADC Module Block Diagram

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6.14.4.1 ADC Configurability

Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 6-15 summarizes the basic ADC options and their level of configurability.
Table 6-15. ADC Options and Configuration Levels
OPTIONS CONFIGURABILITY
Clock Per module(1)
Resolution Not configurable (12-bit resolution only)
Signal mode Not configurable (single-ended signal mode only)
Reference voltage source Either external or internal for all modules
Trigger source Per SOC(1)
Converted channel Per SOC
Acquisition window duration Per SOC(1)

ADVANCE INFORMATION
EOC location Per module
Burst mode Per module(1)

(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.

6.14.4.1.1 Signal Mode

The ADC supports single-ended signaling. The input voltage to the converter is sampled through a single pin
(ADCINx), referenced to VREFLO.

Pin Voltage
VREFHI
VREFHI

ADCINx ADCINx

VREFHI/2 ADC

VREFLO
VREFLO
(VSSA)

Digital Output
2n - 1

ADC Vin

Figure 6-35. Single-ended Signaling Mode

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6.14.4.2 ADC Electrical Data and Timing

Note
The ADC inputs should be kept below VDDA + 0.3 V. If an ADC input goes above this level, ADC
disturbances to other channels may occur by two mechanisms:
• ADC input overvoltage will overdrive the CMPSS mux, disturbing all other channels which share a
common CMPSS mux. This disturbance will be continuous regardless of if the overvoltage input is
sampled by the ADC
• When the ADC samples the overvoltage ADC input, VREFHI will be pulled up to a higher level.
This will disturb subsequent ADC conversions on any channel until the VREF stabilizes

Note
ADVANCE INFORMATION

The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion.

6.14.4.2.1 ADC Operating Conditions

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADCCLK (derived from PERx.SYSCLK) 5 75 MHz
150-MHz SYSCLK
Sample rate 3.9 MSPS

Sample window duration (set by ACQPS and

With 50 Ω or less Rs 67 ns
PERx.SYSCLK)(1)
VREFHI External Reference 1.55 1.65 or 2.50 VDDA V
Internal Reference = 3.3V Range 1.65 V
VREFHI(2)
Internal Reference = 2.5V Range 2.50 V
VREFLO VSSA VSSA V
VREFHI - VREFLO 2.4 VDDA V
Conversion range Internal Reference = 3.3 V Range 0 3.3 V
Conversion range Internal Reference = 2.5 V Range 0 2.5 V
Conversion range External Reference VREFLO VREFHI V
Conversion range Analog Supply as Reference VSSA VDDA V

(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage
into the pin in this mode.

6.14.4.2.2 ADC Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General
ADCCLK Conversion Cycles 150-MHz SYSCLK 14 ADCCLKs
External Reference mode 500 µs
Internal Reference mode 5000 µs
Power Up Time
Internal Reference mode, when switching between
5000 µs
2.5-V range and 3.3-V range.
VREFHI input current(1) 40 µA
Internal Reference Capacitor
2.2 µF
Value(2)

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6.14.4.2.2 ADC Characteristics (continued)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
External Reference Capacitor
2.2 µF
Value(2)
DC Characteristics
Internal reference –45 45
Gain Error LSB
External reference –5 ±3 5
Offset Error –5 ±1 5 LSB
Channel-to-Channel Gain Error(4) 2 LSB
Channel-to-Channel Offset
2 LSB
Error(4)
ADC-to-ADC Gain Error(5) Identical VREFHI and VREFLO for all ADCs 4 LSB

ADVANCE INFORMATION
ADC-to-ADC Offset Error(5) Identical VREFHI and VREFLO for all ADCs 2 LSB
DNL Error >–1 ±0.5 1 LSB
INL Error –2 ±1.5 2 LSB
ADC-to-ADC Isolation VREFHI = 2.5 V, synchronous ADCs –1 1 LSBs
AC Characteristics
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 69.2
SNR(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from dB
TBD
INTOSC
THD(3) VREFHI = 2.5 V, fin = 100 kHz –83 dB
SFDR(3) VREFHI = 2.5 V, fin = 100 kHz 79.2 dB
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 68.5
SINAD(3) VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from dB
60.0
INTOSC
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
11.2
X1, Single ADC
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from
ENOB(3) TBD bits
X1, synchronous ADCs
VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from Not
X1, asynchronous ADCs Supported
VDD = 1.2-V DC + 100mV
60
DC up to Sine at 1 kHz
VDD = 1.2-V DC + 100 mV
57
DC up to Sine at 300 kHz
PSRR dB
VDDA = 3.3-V DC + 200 mV
60
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
57
Sine at 900 kHz

(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(4) Variation across all channels belonging to the same ADC module.
(5) Worst case variation compared to other ADC modules.

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6.14.4.2.3 ADC INL and DNL

0x006

0x005

0x004
Digital Output Code

0x003

0x002
ADVANCE INFORMATION

0x001

DNL Error
0x000

Analog Input Voltage

= Ideal Transfer Function

= Transfer Function (Low)

= INL Error

VREFHI – VREFLO
R=
2^n

Figure 6-36. ADC INL and DNL

6.14.4.2.4 ADC Input Model

Table 6-16. Input Model Parameters
DESCRIPTION REFERENCE MODE VALUE
Cp Parasitic input capacitance All See Table 6-17 to Table 6-21
External Reference, 2.5-V Internal
1000 Ω
Ron Sampling switch resistance Reference
3.3-V Internal Reference 1700 Ω
External Reference, 2.5-V Internal
4 pF
Ch Sampling capacitor Reference
3.3-V Internal Reference 2.5 pF
Rs Nominal source impedance All 50 Ω

ADC
ADCINx
Rs
Switch Ron
AC Cp Ch

VREFLO

Figure 6-37. Input Model

This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analog-

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to-Digital Converter (ADC) chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference
Manual. For recommendations on improving ADC input circuits, see the ADC Input Circuit Evaluation for C2000
MCUs Application Report.
Table 6-17. Per-Channel Parasitic Capacitance for 128-Pin QFP
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
A0, B15, C15, DACA_OUT 1.7 3.2

A1, B7, D11, DACB_OUT, REFHI 1.5 3.0

A2, B6, C9, PGA1_INP 1.7 3.2

A3 5.4 6.9

A4, B8, REFLO 1.2 2.7

ADVANCE INFORMATION
A5 2.2 3.7

A6, D14, E14 0.2 1.7

A7, C3, D12, B30, E30 0.9 2.4

A8, B0, C11 0.5 2.0

A9 0.2 1.7

A10, B1, C10 0.2 1.7

A11, B10, C0,PGA2_OUT 1.1 2.6

A12 1.1 2.6

A14, B14, C4, PGA1_OUT 1.0 2.5

A15 0.5 2.0

A16, B16, C16 0.2 0.2

A17,B17,C17 0.2 0.2

A18,B18,C18 0.2 0.2

A19,B19,C19 0.2 0.2

A20,B20,C20 0.2 0.2

B2, C6, E12 0.2 1.7

B3, PGA2_INP 0.2 1.7

B4, C8 0.2 1.7

B5, D15, E15 0.5 2.0

B9, C7, PGA1_INM 1.8 1.8

B11, D16, E16 5.0 6.5

B12, C2, PGA2_INM 1.0 2.5

C1,E11,PGA3_INP 0.7 2.2

C5 5.4 5.4

C14 4.9 6.4

D0,E0,A24 0.2 0.2

D1,E1,B24 0.2 0.2

D2,E2,C24 0.2 0.2

D3,E3,A25 0.2 0.2

D4,E4,B25 0.2 0.2

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Table 6-17. Per-Channel Parasitic Capacitance for 128-Pin QFP (continued)

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
D5,E5,C25 5.0 5.0

D6,E6,A26 5.0 5.0

D7,E7,B26 5.0 5.0

D8, E8, C26 0.2 0.2

D9,E9, A27 0.2 0.2

D10,E10,B27 0.2 0.2

D18,E18,C27 0.2 0.2

D19,E19,A28 0.2 0.2

ADVANCE INFORMATION

Table 6-18. Per-Channel Parasitic Capacitance for 100-Pin QFP

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
A0, B15, C15, DACA_OUT 1.7 3.2

A1, B7, D11, DACB_OUT, REFHI 1.5 3.0

A2, B6, C9, PGA1_INP 1.7 3.2

A3 5.4 6.9

A4, B8, REFLO 1.2 2.7

A5 2.2 3.7

A6, D14, E14 0.2 1.7

A7, C3, D12, B30, E30 0.9 2.4

A8, B0, C11 0.5 2.0

A9 0.2 1.7

A10, B1, C10 0.2 1.7

A11, B10, C0, PGA2_OUT 1.1 2.6

A12 1.1 2.6

A14, B14, C4, PGA1_OUT 1.0 2.5

A16/B16/C16 0.2 0.2

A17,B17,C17 0.2 0.2

A18,B18,C18 0.2 0.2

A19,B19,C19 0.2 0.2

A20,B20,C20 0.2 0.2

B2, C6, E12 0.2 1.7

B3, PGA2_INP 0.2 1.7

B4, C8 0.2 1.7

B5, D15, E15 0.5 2.0

B9, C7, PGA1_INM 1.8 1.8

B11, D16, E16 5.0 6.5

B12, C2, PGA2_INM 1.0 2.5

C1,E11,PGA3_INP 0.7 2.2

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Table 6-18. Per-Channel Parasitic Capacitance for 100-Pin QFP (continued)

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
C5 5.4 5.4

C14 4.9 6.4

D0,E0,A24 0.2 0.2

D1,E1,B24 0.2 0.2

D2,E2,C24 0.2 0.2

D3,E3,A25 0.2 0.2

D4,E4,B25 0.2 0.2

Table 6-19. Per-Channel Parasitic Capacitance for 80-Pin QFP

ADVANCE INFORMATION
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
A0, B15, C15, DACA_OUT 1.7 3.2

A1, B7, D11, DACB_OUT, REFHI 1.5 3.0

A2, B6, C9, PGA1_INP 1.7 3.2

A3 5.4 6.9

A4, B8, REFLO 1.2 2.7

A5 2.2 3.7

A6, D14, E14 0.2 1.7

A7, C3, D12, B30,E30 0.9 2.4

A8, B0, C11 0.5 2.0

A9 0.2 1.7

A10, B1, C10 0.2 1.7

A11, B10, C0,PGA2_OUT 1.1 2.6

A12 1.1 2.6

A14, B14, C4, PGA1_OUT 1.0 2.5

A15 0.5 2.0

A16/B16/C16 0.2 0.2

A17,B17,C17 0.2 0.2

A18,B18,C18 0.2 0.2

A19,B19,C19 0.2 0.2

A20,B20,C20 0.2 0.2

B2, C6, E12 0.2 1.7

B3, PGA2_INP 0.2 1.7

B4, C8 0.2 1.7

B9, C7, PGA1_INM 1.8 1.8

B12, C2, PGA2_INM 1.0 2.5

C1,E11,PGA3_INP 0.7 2.2

C5 5.4 5.4

C14 4.9 6.4

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Table 6-19. Per-Channel Parasitic Capacitance for 80-Pin QFP (continued)

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
D0,E0,A24 0.2 0.2

D1,E1,B24 0.2 0.2

D2,E2,C24 0.2 0.2

D3,E3,A25 0.2 0.2

D4,E4,B25 0.2 0.2

Table 6-20. Per-Channel Parasitic Capacitance for 64-Pin QFP

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
ADVANCE INFORMATION

A0, B15, C15, DACA_OUT 1.7 3.2

A1, B7, D11, DACB_OUT, REFHI 1.5 3.0

A2, B6, C9, PGA1_INP 1.7 3.2

A3 5.4 6.9

A4, B8, REFLO 1.2 2.7

A5 2.2 3.7

A6, D14, E14 0.2 1.7

A7, C3, D12, B30, E30 0.9 2.4

A8, B0, C11 0.5 2.0

A9 0.2 1.7

A10, B1, C10 0.2 1.7

A11, B10, C0,PGA2_OUT 1.1 2.6

A12 1.1 2.6

A14, B14, C4, PGA1_OUT 1.0 2.5

A15 0.5 2.0

A16, B16, C16 0.2 0.2

A17,B17,C17 0.2 0.2

A18,B18,C18 0.2 0.2

A19,B19,C19 0.2 0.2

A20,B20,C20 0.2 0.2

B2, C6, E12 0.2 1.7

B3, PGA2_INP 0.2 1.7

B4, C8 0.2 1.7

B9, C7, PGA1_INM 1.8 1.8

B12, C2, PGA2_INM 1.0 2.5

C1,E11,PGA3_INP 0.7 2.2

C5 5.4 5.4

C14 4.9 6.4

D0,E0,A24 0.2 0.2

D1,E1,B24 0.2 0.2

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Table 6-20. Per-Channel Parasitic Capacitance for 64-Pin QFP (continued)

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
D2,E2,C24 0.2 0.2

D3,E3,A25 0.2 0.2

D4,E4,B25 0.2 0.2

Table 6-21. Per-Channel Parasitic Capacitance for 56-Pin QFN

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
A0, B15, C15, DACA_OUT 1.7 3.2

A1, B7, D11, DACB_OUT, REFHI 1.5 3.0

ADVANCE INFORMATION
A2, B6, C9, PGA1_INP 1.7 3.2

A3 5.4 6.9

A4, B8, REFLO 1.2 2.7

A5 2.2 3.7

A7, C3, D12, B30,E30 0.9 2.4

A8, B0, C11 0.5 2.0

A9 0.2 1.7

A10, B1, C10 0.2 1.7

A11, B10, C0,PGA2_OUT 1.1 2.6

A12 1.1 2.6

A14, B14, C4, PGA1_OUT 1.0 2.5

A15 0.5 2.0

A16,B16,C16 0.2 0.2

A17,B17,C17 0.2 0.2

A18,B18,C18 0.2 0.2

A19,B19,C19 0.2 0.2

A20,B20,C20 0.2 0.2

B3, PGA2_INP 0.2 1.7

B4, C8 0.2 1.7

B9, C7, PGA1_INM 1.8 1.8

B12, C2, PGA2_INM 1.0 2.5

C1,E11,PGA3_INP 0.7 2.2

C5 5.4 5.4

C14 4.9 6.4

D0,E0,A24 0.2 0.2

D1,E1,B24 0.2 0.2

D2,E2,C24 0.2 0.2

D3,E3,A25 0.2 0.2

D4,E4,B25 0.2 0.2

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6.14.4.2.5 ADC Timing Diagrams

The following diagrams show the ADC conversion timings for two SOCs given the following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round-robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 6-22 lists the descriptions of the ADC timing parameters. Table 6-23 and Table 6-24 list the ADC timings.
Sample n

Input on SOC0.CHSEL

Input on SOC1.CHSEL
Sample n+1
ADVANCE INFORMATION

ADC S+H SOC0 SOC1

SYSCLK

ADCCLK

ADCTRIG

ADCSOCFLG.SOC0

ADCSOCFLG.SOC1

ADCRESULT0 (old data) Sample n

ADCRESULT1 (old data) Sample n+1

ADCINTFLG.ADCINTx

tSH tLAT

tEOC

tINT

Figure 6-38. ADC Timings for 12-bit Mode in Early Interrupt Mode

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Sample n
Input on SOC0.CHSEL

Input on SOC1.CHSEL
Sample n+1

ADC S+H SOC0 SOC1

SYSCLK

ADCCLK

ADCTRIG

ADVANCE INFORMATION
ADCSOCFLG.SOC0

ADCSOCFLG.SOC1

ADCRESULT0 (old data) Sample n

ADCRESULT1 (old data) Sample n+1

ADCINTFLG.ADCINTx

tSH tLAT

tEOC

tINT

Figure 6-39. ADC Timings for 12-bit Mode in Late Interrupt Mode

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Table 6-22. ADC Timing Parameter Descriptions
PARAMETER DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The
duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH is not
tSH
necessarily the same for different SOCs.
Note: The value on the S+H capacitor is captured approximately 5 ns before the end of the S+H window regardless of
device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results are returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
tEOC
subsequent sample can start before the conversion results are latched.
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT coincides with the end of conversion (EOC) signal.
ADVANCE INFORMATION

If the INTPULSEPOS bit is 0, tINT coincides with the end of the S+H window. If tINT triggers a read of the ADC result
tINT register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken to make sure
the read occurs after the results latch (otherwise, the previous results are read).
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there is a delay of
OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or trigger the DMA
exactly when the sample is ready.
The time from the end of the S+H window until a DMA read of the ADC conversion result is triggered, when
ADCCTL1.TDMAEN = 1.
tDMA If TDMAEN is set to 0, then the DMA trigger occurs at TINT. In certain conditions, the ADCINT flag can be set before the
ADCRESULT value is latched. To make sure that the DMA read occurs after the ADCRESULT value has been latched,
write 1 to ADCCTL1.TDMAEN to enable DMA timings.

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Table 6-23. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 0

ADCCLK Prescale SYSCLK Cycles
ADCCTL2. tINT tINT
Prescale Ratio tEOC tLAT tDMA
PRESCALE (Early)(1) (Late)
0 1 15 20 1 15 20
2 2 30 35 1 30 35
3 2.5 38 46 1 38 46
4 3 45 50 1 45 50
5 3.5 53 58 1 53 58
6 4 60 65 1 60 65
7 4.5 68 73 1 68 73
8 5 75 80 1 75 80
9 5.5 83 88 1 83 88

ADVANCE INFORMATION
10 6 90 95 1 90 95
11 6.5 98 103 1 98 103
12 7 105 110 1 105 110
13 7.5 113 118 1 113 118
14 8 120 125 1 120 125
15 8.5 128 133 1 128 133

(1) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.

Table 6-24. ADC Timings in 12-bit Mode with SAMPCAPRESETSEL = 1

ADCCLK Prescale SYSCLK Cycles
ADCCTL2. tINT tINT
Prescale Ratio tEOC tLAT tDMA
PRESCALE (Early)(1) (Late)
0 1 14 19 1 14 19
2 2 28 33 1 28 33
3 2.5 35 40 1 35 40
4 3 42 47 1 42 47
5 3.5 49 54 1 49 54
6 4 56 61 1 56 61
7 4.5 63 68 1 63 68
8 5 70 75 1 70 75
9 5.5 77 82 1 77 82
10 6 84 89 1 84 89
11 6.5 91 96 1 91 96
12 7 98 103 1 98 103
13 7.5 105 110 1 105 110
14 8 112 117 1 112 117
15 8.5 119 124 1 119 124

(1) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.

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6.14.5 Temperature Sensor

6.14.5.1 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor
is sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in the Temperature
Sensor Characteristics table.
6.14.5.1.1 Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Tacc Temperature Accuracy External reference ±15 °C
Start-up time
tstartup (TSNSCTL[ENABLE] to 500 µs
sampling temperature sensor)
ADVANCE INFORMATION

tacq ADC acquisition time 450 ns

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6.14.6 Comparator Subsystem (CMPSS)

The Comparator Subsystem (CMPSS) consists of analog comparators and supporting circuits that are useful for
power applications such as peak current mode control, switched-mode power supply, power factor correction,
voltage trip monitoring, and so forth.
The comparator subsystem is built around a number of modules. Each subsystem contains two comparators,
two reference 12-bit DACs, and two digital filters. The subsystem also includes two ramp generators. The
ramp generators ramp up and down. Comparators are denoted "H" or "L" within each module where “H” and
“L” represent high and low, respectively. Each comparator generates a digital output which indicates whether
the voltage on the positive input is greater than the voltage on the negative input. The positive input of
the comparator is driven from an external pin (see the Analog Subsystem chapter of the TMS320F28P55x
Real-Time Microcontrollers Technical Reference Manual for mux options available to the CMPSS). The negative
input can be driven by an external pin or by the programmable reference 12-bit DAC. Each comparator output
passes through a programmable digital filter that can remove spurious trip signals. An unfiltered output is also

ADVANCE INFORMATION
available if filtering is not required. Two ramp generator circuits are optionally available to control the reference
12-bit DAC values for the high and low comparators in the subsystem. The DAC along with a wrapper can be
used to generate a ramp which is used for slope compensation in Peak Current Mode Control (PCMC) and other
applications.
Each CMPSS includes:
• Two analog comparators
• Two independently programmable reference 12-bit DACs
• Dual decrementing/incrementing ramp generators
• Two digital filters with max filter clock prescale of 224
• Ability to synchronize submodules with EPWMSYNCPER
• Ability to extend clear signal with EPWMBLANK
• Ability to synchronize output with SYSCLK
• Ability to latch output
• Ability to invert output
• Option to use hysteresis on the input
• Option for negative input of comparator to be driven by an external signal or by the reference DAC
• Option for positive input of comparator to be driven by an external signal or by the PGA
• Option to use the low comparator DAC output, CMPx_DACL, on an external pin (select instances only,
mutually exclusive with use of compare functionality)
• External connection to CMPSS filters
• Supports connection with ePWM for diode emulation
• Ramp generator prescaler
• Wake-up from standby and halt LPM (Low Power Modes) triggered by CMPSS trip outputs
6.14.6.1 CMPx_DACL
Some CMPSS module instances have support for DAC output buffered to a pin. This CMPx_DACL output from
the CMPSS module uses the low-side DAC of the CMPSS module specified. When using DAC output from a
CMPSS instance, all other CMPSS module features for that instance are unavailable.
For CMPx_DACL instances available for a particular device, please see the DAC column of the Analog Pins and
Internal Connections table.
See the Buffered Output from CMPx_DACL Electrical Characteristics section for DAC output capabilities.

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6.14.6.2 CMPSS Connectivity Diagram

CMPSS Module

GPIO Mux
CMP1_HP Comparator Subsystem 1 CTRIP1H ePWM X-BAR
Digital CTRIP1H
CMP1_HN VDDA Filter CTRIPOUT1H CTRIP1L ePWMs
DAC12 CMP1_DACL CTRIP2H
CTRIP1L
Output X-BAR
DAC12 Digital
CMP1_LN CTRIP2L
Filter CTRIPOUT1L
CMP1_LP CTRIP3H ePWM X-BAR ePWMs
CMP2_HP Comparator Subsystem 2
CTRIP2H CTRIP3L
Digital
CMP2_HN VDDA Filter CTRIPOUT2H CTRIP4H

DAC12 CTRIP4L
CTRIP2L
DAC12 Digital
CMP2_LN
Filter CTRIPOUT2L
CMP2_LP
Comparator Subsystem 3
ADVANCE INFORMATION

CMP3_HP
Digital CTRIP3H
CMP3_HN VDDA Filter CTRIPOUT3H
DAC12
CTRIPOUT1H
DAC12 Digital CTRIP3L
CMP3_LN
Filter CTRIPOUT3L CTRIPOUT1L

CMP3_LP CTRIPOUT2H
CMP4_HP Comparator Subsystem 4
CTRIPOUT2L
Digital CTRIP4H
CMP4_HN VDDA Filter CTRIPOUT4H CTRIPOUT3H Output X-BAR GPIO Mux
DAC12
CTRIPOUT3L
DAC12 Digital CTRIP4L
CMP4_LN
Filter CTRIPOUT4L CTRIPOUT4H
CMP4_LP
CTRIPOUT4L

Figure 6-40. CMPSS Connectivity

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6.14.6.3 Block Diagram

The block diagram for the CMPSS is shown in Figure 6-41.
• CTRIPx(x= "H" or "L") signals are connected to the ePWM X-BAR for ePWM trip response. See the
Enhanced Pulse Width Modulator (ePWM) chapter of the for more details on the ePWM X-BAR mux
configuration.
• CTRIPxOUTx(x= "H" or "L") signals are connected to the Output X-BAR for external signaling. See
the General-Purpose Input/Output (GPIO) chapter of the for more details on the Output X-BAR mux
configuration.
To LPM Wakeup
COMPCTL[CTRIPHSEL]
COMPSTS[COMPHSTS] Comparator

ASYNCH
SYSCLK > COMPDACHCTL[SWLOADSEL] COMPCTL[COMPHINV] 3 CTRIPH Digital Filter
CMPx_HP SYSCLK SYNCH
EPWMSYNCPER_H + 2 To EPWM X-BAR
COMPSTS[COMPHSTS]

>
COMPSTS[COMPLSTS] D Q 0 1 CTRIPOUTH Output MUX

2 1|0 DACHVALS 0 12-bit COMPH 0 0 Digital 0

To OUTPUT X-BAR
COMPDACHCTL2[XTRIGCFG] D Q 1 DACHVALA Ramp generator
DACH 0 D RQ Filter S

>
_ R
1 1

>
TRIGSYNCH COMPCTL[CTRIPOUTHSEL] CMPSS DAC
EN CMPx_HN 1 . R Q
EXT_FILTIN_H . OR CMPSS Buffered DAC
Ramp Generator(H) 1 n

ADVANCE INFORMATION
COMPCTL[COMPHSOURCE] 0 0
COMPDACHCTL[RAMPSOURCE]+ COMPSTS[COMPHLATCH]
16*COMPDACHCTL2[RAMPSOURCEUSEL] CTRIPHFILCTL[FILTINSEL] 1
COMPDACHCTL[DACSOURCE] OR
COMPSTSCLR[HSYNCCLREN]
EPWM1SYNCPER 0 COMPCTL[ASYNCHEN]
EPWM2SYNCPER 1 EPWMSYNCPER_H 0 0 COMPSTSCLR[HLATCHCLR]
EPWM3SYNCPER 2
OR

EPWMBLANK_H 1
... … AND
EPWMnSYNCPER n-1 COMPDACHCTL[BLANKEN]
COMPSTSCLR[LSYNCCLREN]
COMPSTSCLR[LLATCHCLR]
EPWMSYNCPER_L
COMPDACLCTL[RAMPSOURCE]+ 0 0 COMPCTL[ASYNCLEN]
OR

16*COMPDACLCTL2[RAMPSOURCEUSEL] COMPDACLCTL[BLANKEN]
AND OR
COMPDACHCTL[BLANKSOURCE]+ 1 0 0
EPWMBLANK_L
16*COMPDACHCTL2[BLANKSOURCEUSEL] COMPSTS[COMPLLATCH]
COMPDACHCTL[SWLOADSEL] 1
EPWM1BLANK CMPx_LP CTRIPLFILCTL[FILTINSEL]
0 SYSCLK > + OR
EPWM2BLANK 1 R Q
EPWM3BLANK D Q 0 0

>
2 12-bit COMPL 0 Digital COMPCTL[CTRIPLSEL]
R

>
... … DACLVALS 0
DACL 0 D RQ Filter S
D Q 1 _ 1 1
EPWMnBLANK n-1 3 CTRIPL
CMPx_LN 1 . COMPSTS[COMPLSTS]
DACLVALA 2 To EPWM X-BAR

>
EN EXT_FILTIN_L . SYNCL
COMPDACLCTL[BLANKSOURCE]+ n SYSCLK 1 CTRIPOUTL
ASYNCL To OUTPUT X-BAR
16*COMPDACLCTL2[BLANKSOURCEUSEL] 1 COMPCTL[COMPLSOURCE] 0
Ramp Generator(L) 0 COMPCTL[COMPLINV] To LPM Wakeup
COMPCTL[CTRIPOUTLSEL]
COMPDACLCTL[DACSOURCE] CMPxDACL
TRIGSYNCL
>>1 1 Bu
er To Pin

COMPDACHCTL2[XTRIGCFG] 1 2|0 CMPxDACOUTEN Enable

COMPSTS[COMPHSTS] (from Analog Subsystem)
COMPSTS[COMPLSTS]
EPWMSYNCPER_L

A. CMPxDACL only exists for the CMPSS 1 module on this device.

B. Enabling the DACL to a pin disables all other functionality: DACH, both COMP, the Ramp Generator, and the digital filters.

Figure 6-41. CMPSS Module Block Diagram

Each reference 12-bit DAC can be configured to drive a reference voltage into the negative input of the
respective comparator. Some CMPSS instances also allow the low DAC output to be routed to a pin to act as
an external DAC. In this case, all other CMPSS module functionality is not useable, including the high DAC, both
comparators, ramp generation, and the digital filters. The reference 12-bit DAC is illustrated in Figure 6-42.
VDDA DACREF

12-bit DACOUTH
DACHVALA DACH To COMPH

12-bit DACOUTL
DACLVALA DACL To COMPL
VSSA
Figure 6-42. Reference DAC Block Diagram

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6.14.6.4 CMPSS Electrical Data and Timing

6.14.6.4.1 CMPSS Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPU Power-up time 500 µs
Comparator input (CMPINxx) range 0 VDDA V
Low common mode, inverting
Input referred offset error –20 20 mV
input set to 50mV
1x 4 12 20
2x 17 24 33
Hysteresis(1) LSB
3x 25 36 50
4x 30 48 67
Step response 21 60
Response time (delay from CMPINx input change to ns
ADVANCE INFORMATION

Ramp response (1.65V/µs) 26

output on ePWM X-BAR or Output X-BAR)
Ramp response (8.25mV/µs) 30 ns
PSRR Power Supply Rejection Ratio Up to 250 kHz 46 dB
CMRR Common Mode Rejection Ratio 40 dB

(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.

CMPSS Comparator Input Referred Offset and Hysteresis

Input Referred Offset

CTRIPx
Logic Level CTRIPx = 1

CTRIPx = 0

COMPINxP
Voltage
0 CMPINxN or
DACxVAL

Figure 6-43. CMPSS Comparator Input Referred Offset

Hysteresis

CTRIPx
Logic Level CTRIPx = 1

CTRIPx = 0

COMPINxP
Voltage
0 CMPINxN or
DACxVAL

Figure 6-44. CMPSS Comparator Hysteresis

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6.14.6.4.2 CMPSS DAC Static Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CMPSS DAC output range Internal reference 0 VDDA V
Static offset error(1) –25 25 mV
Static gain error(1) –2 2 % of FSR
Static DNL Endpoint corrected >–1 4 LSB
Static INL Endpoint corrected –16 16 LSB
Settling time Settling to 1LSB after full-scale output change 1 µs
Resolution 12 bits
Error induced by comparator trip or CMPSS
CMPSS DAC output disturbance(2) DAC code change within the same CMPSS –100 100 LSB
module
CMPSS DAC disturbance time(2) 200 ns

ADVANCE INFORMATION
(1) Includes comparator input referred errors.
(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.

6.14.6.4.3 CMPSS Illustrative Graphs

Offset Error

Figure 6-45. CMPSS DAC Static Offset

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Ideal Gain

Actual Gain
ADVANCE INFORMATION

Actual Linear Range

Figure 6-46. CMPSS DAC Static Gain

Linearity Error

Figure 6-47. CMPSS DAC Static Linearity

6.14.6.4.4 Buffered Output from CMPx_DACL Operating Conditions

over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL Resistive Load(2) 5 kΩ
CL Capacitive Load 100 pF

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6.14.6.4.4 Buffered Output from CMPx_DACL Operating Conditions (continued)

over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 5 kΩ 0.3 VDDA – 0.3 V
VOUT Valid Output Voltage Range(3)
RL = 1 kΩ 0.6 VDDA – 0.6 V
Reference Voltage(4) VREFHI 2.4 2.5 or 3.0 VDDA V

(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
(3) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(4) For best PSRR performance, VREFHI should be less than VDDA.

6.14.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics

ADVANCE INFORMATION
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General
Resolution(4) 12 bits
Load Regulation –1 1 mV/V
Glitch Energy 1.5 V-ns
Settling to 2 LSBs after 0.3V-
Voltage Output Settling Time Full-Scale 2 µs
to-3V transition
Settling to 2 LSBs after 0.3V-
Voltage Output Settling Time 1/4th Full-Scale 1.6 µs
to-0.75V transition
Slew rate from 0.3V-to-3V
Voltage Output Slew Rate 2.8 4.5 V/µs
transition
Load Transient Settling Time 5-kΩ Load 328 ns
TPU Power Up Time Bandgap Not Enabled 500 µs
DC Characteristics
Offset Offset Error –100 100 mV
Gain Gain Error(2) –1.5 1.5 % of FSR
DNL Differential Non Linearity(4) Endpoint corrected –2 2 LSB (12-bit)
INL Integral Non Linearity Endpoint corrected –7 7 LSB (12-bit)
AC Characteristics
Integrated noise from 100 Hz
600 µVrms
Output Noise to 100 kHz
Noise density at 10 kHz 800 nVrms/√Hz
SNR Signal to Noise Ratio 1 kHz, 200 KSPS 64 dB
THD Total Harmonic Distortion 1 kHz, 200 KSPS –64.2 dB
Spurious Free Dynamic
SFDR 1 kHz, 200 KSPS 66 dB
Range
Signal to Noise and Distortion
SINAD 1 kHz, 200 KSPS 61.7 dB
Ratio

Power Supply Rejection DC 70 dB

PSRR
Ratio(3) 100 kHz 30 dB

(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) Gain error is calculated for linear output range.
(3) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
(4) 11-bit effective (monotonic response).

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6.14.7 Buffered Digital-to-Analog Converter (DAC)

The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that can drive an
external load. For driving even higher loads than typical, a trade-off can be made between load size and
output voltage swing. For the load conditions of the buffered DAC, see the Buffered DAC Electrical Data and
Timing section. The buffered DAC is a general-purpose DAC that can be used to generate a DC voltage or AC
waveforms such as sine waves, square waves, triangle waves and so forth. Software writes to the DAC value
register can take effect immediately or can be synchronized with EPWMSYNCO events.
Each buffered DAC has the following features:
• 12-bit resolution
• Selectable reference voltage source
• x1 and x2 gain modes when using internal VREFHI
• Ability to synchronize with EPWMSYNCPER
ADVANCE INFORMATION

DAC Module
DACCTL[DACREFSEL]
ANAREFx1P65SEL
Reference Voltage Source
0 Output Bu
er
2.5 V DACREF
0 1 12-Bit DAC
Internal Reference
1
Circuit 1.65 V 0
Internal Reference Circuit
1
VREFHI
ANAREFPCTL[REFPMUXSELx]

VDDA

SYSCLK > DACCTL[LOADMODE]

DACVALS D Q 0
12-bit DACOUT
DACVALA
DAC
D Q 1

EPWM1SYNCPER
0
EN
EPWM2SYNCPER
1
EPWM3SYNCPER VSSA VSSA
2
...
... DACCTL[MODE]
EPWMnSYNCPER (Select x1 or x2 gain)
n-1

DACCTL[SYNCSEL]

A. VDAC is not available for this device; so, VREFHI and VSSA are the reference voltages.

Figure 6-48. DAC Module Block Diagram

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6.14.7.1 Buffered DAC Electrical Data and Timing

6.14.7.1.1 Buffered DAC Operating Conditions
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL Resistive Load(2) 5 kΩ
CL Capacitive Load 100 pF
RL = 5 kΩ 0.3 VDDA – 0.3 V
VOUT Valid Output Voltage Range(3)
RL = 1 kΩ 0.6 VDDA – 0.6 V
Reference Voltage(4) VREFHI 2.4 2.5 or 3.0 VDDA V

(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
(3) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear

ADVANCE INFORMATION
due to the buffer.
(4) For best PSRR performance, VREFHI should be less than VDDA.

6.14.7.1.2 Buffered DAC Electrical Characteristics

over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General
Resolution 12 bits
Load Regulation –1 1 mV/V
Glitch Energy 1.5 V-ns
Settling to 2 LSBs after 0.3V-
Voltage Output Settling Time Full-Scale 2 µs
to-3V transition
Settling to 2 LSBs after 0.3V-
Voltage Output Settling Time 1/4th Full-Scale 1.6 µs
to-0.75V transition
Slew rate from 0.3V-to-3V
Voltage Output Slew Rate 2.8 4.5 V/µs
transition
5-kΩ Load 328 ns
Load Transient Settling Time
1-kΩ Load 557 ns
Reference Input Resistance(2) VREFHI 160 200 240 kΩ
External Reference mode 500 µs
TPU Power Up Time
Internal Reference mode 5000 µs
DC Characteristics
Offset Offset Error Midpoint –10 10 mV
Gain Gain Error(3) –2.5 2.5 % of FSR
DNL Differential Non Linearity(4) Endpoint corrected –1 ±0.4 1 LSB
INL Integral Non Linearity Endpoint corrected –5 ±2 5 LSB
AC Characteristics
Integrated noise from 100 Hz
600 µVrms
Output Noise to 100 kHz
Noise density at 10 kHz 800 nVrms/√Hz
SNR Signal to Noise Ratio 1 kHz, 200 KSPS 64 dB
THD Total Harmonic Distortion 1 kHz, 200 KSPS –64.2 dB
Spurious Free Dynamic
SFDR 1 kHz, 200 KSPS 66 dB
Range
Signal to Noise and Distortion
SINAD 1 kHz, 200 KSPS 61.7 dB
Ratio

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6.14.7.1.2 Buffered DAC Electrical Characteristics (continued)

over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power Supply Rejection DC 70 dB

PSRR
Ratio(5) 100 kHz 30 dB

(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) Per active Buffered DAC module.
(3) Gain error is calculated for linear output range.
(4) The DAC output is monotonic.
(5) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
ADVANCE INFORMATION

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6.14.8 Programmable Gain Amplifier (PGA)

The Programmable Gain Amplifier (PGA) is used to amplify an input voltage for the purpose of increasing the
effective resolution of the downstream ADC and CMPSS modules.
The integrated PGA helps to reduce cost and design effort for many control applications that traditionally require
external, stand-alone amplifiers. On-chip integration ensures that the PGA is compatible with the downstream
ADC and CMPSS modules. Software-selectable gain and filter settings make the PGA adaptable to various
performance needs.
The PGA has the following features:
• Rail to rail input and output voltage within VDDA and VSSA range
• Programmable gain modes including unity gain and other values from 2X - 64X
• Standalone gain mode using off-chip passive components
• Post-gain filtering using on-chip resistors

ADVANCE INFORMATION
• Differential input support
• Hardware assisted chopping for offset reduction
• Support for Kelvin ground connections using PGA_INM pins
The active component in the PGA is an embedded operational amplifier (op amp) that is configured as a
non-inverting or inverting amplifier with internal feedback resistors. These internal feedback resistor values are
paired to produce software selectable voltage gains.
Three PGA signals are available at the device pins:
• PGA_INP is the positive input to the PGA op-amp.
• PGA_INM is the negative input to the PGA op-amp. See the device data manual for more information.
• PGA_OUT supports op-amp output filtering with RC components. The filtered signal is available for sampling
and monitoring by on-chip ADC and CMPSS modules.
PGA_OUT_INT is an internal signal at the op amp output. It is available for sampling and monitoring by the
internal ADC and CMPSS modules. Figure 6-49 shows the PGA block diagram.

To ADC and CMPSS

VDDA PGA_OUTENABLE & FILT_RES_SEL=0

FILT_RES_SEL
PGA_INP +
_ PGA_OUT
RFILT

PGA_OUTENABLE PGA_OUTENABLE & OUT_EN_INTGAIN &

FILT_RES_SEL FILT_RES_SEL=0

VSSA PGA_OUT_INT To ADC and CMPSS

Ria Rib
PGA_INM

Figure 6-49. PGA Block Diagram

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6.14.8.1 PGA Electrical Data and Timing

6.14.8.1.1 PGA Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PGA Output Range(1) VSSA+0.025 VDDA-0.025 V
Cap Load on PGA Out 40 pF

(1) This is the linear output range of the PGA. The PGA can output voltages outside this range, but the voltages will not be linear.

6.14.8.1.2 PGA Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General
ADVANCE INFORMATION

Min ADC S+H

Settling within ±1 ADC LSB
(No Filter; All Gain Settings; 400 ns
Accuracy
Single ADC Driven)
Min ADC S+H
Settling within ±1 ADC LSB
(No Filter; All Gain Settings; 450 ns
Accuracy
Two ADC Driven)
Min ADC S+H
Settling within ±1 ADC LSB
(With Filter;All Gain 450(5) ns
Accuracy
Settings)
1
2, 4, 8, 16, 32, 64
Gain Settings
-1, -3, -7, -15, -31,
-63
Input Bias Current 2 nA
Short Circuit Current 41 mA
Full Scale Step Response Settling within ±1 ADC LSB
450 ns
(No Filter) Accuracy
Settling Time Gain Switching 10 µs
Slew Rate Naked OPA Mode 10.9 V/µs
Gain = 1 10 V/µs
Gain = 2/-1 21 V/µs
Gain = 4/-3 39 V/µs
Slew Rate Gain = 8/-7 56 V/µs
Gain = 16/-15 46 V/µs
Gain = 32/-31 29 V/µs
Gain = 64/-63 25 V/µs
Gain = 1 256 kΩ
Gain = 2/-1 16 kΩ
Gain = 4/-3 8 kΩ
Ria Gain = 8/-7 8 kΩ
Gain = 16/-15 8 kΩ
Gain = 32/-31 8 kΩ
Gain = 64/-63 4 kΩ

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6.14.8.1.2 PGA Characteristics (continued)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Gain = 1 0 kΩ
Gain = 2/-1 16 kΩ
Gain = 4/-3 24 kΩ
Rib Gain = 8/-7 56 kΩ
Gain = 16/-15 128 kΩ
Gain = 32/-31 248 kΩ
Gain = 64/-63 252 kΩ
RFILT = 800 Ω 800 Ω
RFILT = 400 Ω 400 Ω

ADVANCE INFORMATION
Filter Resistor Targets RFILT = 200 Ω 200 Ω
RFILT = 100 Ω 100 Ω
RFILT = 50 Ω 50 Ω
Gain Bandwidth Product Gain=1 7 MHz
Gain Bandwidth Product Gain=1 7 MHz
Closed Loop -3bd BW Gain=1 15 MHz
Gain=2/-1 13.7 MHz
Gain=4/-3 10.5 MHz
Gain=8/-7 9.5 MHz
Gain=16/-15 5.8 MHz
Gain=32/-31 3.8 MHz
Gain=64/-63 3.25 MHz
DC Characteristics
Gain Error(1) Gain = 1 +/-0.18 %
Gain Error(1) Gain = 2, -1 +/-0.37 %
Gain Error(1) Gain = 4, -3 +/-0.6 %
Gain Error(1) Gain = 8, -7 +/-0.73 %
Gain Error(1) Gain = 16, -15 +/-0.81 %
Gain Error(1) Gain = 32, -31 +/-1.0 %
Gain Error(1) Gain = 64, -63 +/-1.82 %
Offset Error(2) Input Referred +/-1.0 mV
Offset Temp Coefficient Input Referred ±3.0 µV/C
Offset Error - Chopped +/-0.8 mV
Offset Temp Coefficient -
0.3 µV/C
Chopped
DC Code Spread 2.5 12b LSB
AC Characteristics
Bandwidth(3) All Gain Modes 7 MHz
DC –78 dB
THD(4)
Up to 100 kHz –70 dB
DC –60 dB
CMRR
Up to 100 kHz –50 dB
DC –75 dB
PSRR(4)
Up to 100 kHz –50 dB
Noise PSD(4) 1 kHz 200 nV/sqrt(Hz)

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6.14.8.1.2 PGA Characteristics (continued)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Integrated Noise
3 Hz to 30 MHz 100 µV
(Input Referred)(4)

(1) Includes ADC gain error.

(2) Includes ADC offset error.
(3) 3dB bandwidth.
(4) Performance of PGA alone.
(5) Step response time (max) = 450ns + 7.6*Rfilt* Cfilt
ADVANCE INFORMATION

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6.15 Control Peripherals

6.15.1 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced
trip-zone functionality, and global register reload capabilities.
The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules and allows localized synchronization within the modules.
Figure 6-50 shows the ePWM module. Figure 6-51 shows the ePWM trip input connectivity.

ADVANCE INFORMATION

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Time-Base (TB)

TBPRD Shadow (24) EXTSYNCIN ePWM EXTSYNCOUT

TBPRDHR (8) SYNC
TBPRD Active (24)
Scheme

CTR=PRD
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SWFSYNC]
Counter
DCAEVT1/sync(A)
Up/Down
(16 bit) DCBEVT1/sync(A)
CTR=ZERO
TBCTR
Active (16) CTR_Dir CTR=PRD EPWMx_INT
CTR=ZERO
TBPHSHR (8)
CTR=PRD or ZERO EPWMxSOCA
16 8
CTR=CMPA Event On-chip
Phase EPWMxSOCB
TBPHS Active (24) Trigger ADC
ADVANCE INFORMATION

Control CTR=CMPB
And
CTR=CMPC
Interrupt
CTR=CMPD (ET) ADCSOCOUTSELECT
Counter Compare (CC)
CTR_Dir
Action
CTR=CMPA Qualifier DCAEVT1.soc(A) Select and pulse stretch
(AQ) DCBEVT1.soc(A) for external ADC
CMPAHR (8)
16 HiRes PWM (HRPWM)
CMPAHR (8)
CMPA Active (24) ADCSOCAO
ADCSOCBO
CMPA Shadow (24) EPWMA ePWMxA

CTR=CMPB Dead PWM Trip

Band Chopper Zone
(DB) (DB) (TZ)
CMPBHR (8)
16
CMPB Active (16) EPWMB ePWMxB
CMPB Shadow (16)
CMPBHR (8)
EPWMx_TZ_INT
TBCNT (16) CTR=CMPC CTR=ZERO
TZ1 to TZ3
DCAEVT1.inter
EMUSTOP
CMPC[15-0] 16 DCBEVT1.inter
CLOCKFAIL
DCAEVT2.inter
CMPC Active (16) EQEPxERR
DCBEVT2.inter
CMPC Shadow (16) DCAEVT1.force(A)
DCBEVT1.force(A)
TBCNT (16) CTR=CMPD DCAEVT2.force(A)
DCBEVT2.force(A)
CMPD[15-0] 16

CMPD Active (16)

CMPD Shadow (16)

A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.

Figure 6-50. ePWM Submodules and Critical Internal Signal Interconnects

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ADVANCE INFORMATION
Figure 6-51. ePWM Trip Input Connectivity

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6.15.1.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules and allows localized synchronization within the modules. Figure 6-52 shows the synchronization
scheme.
TBCTL

TBCTL2[OSHTSYNC]

TBCTL3[OSSFRCEN]
GLDCTL2[OSHTLD]
SWFSYNC

:ULWH ³1´ WR

:ULWH ³1´ WR
CTR=ZERO

CTR=CMPB
CTR=CMPC

TBCTL2[OSHTSYNCMODE]
CTR=CMPD
CLR
DCAEVT1.sync One Shot
DCBEVT1.sync Latch
ADVANCE INFORMATION

0
Set Q
EPWMSYNCOUTEN
1

SWEN

ZEROEN
0 0
CMPBEN
1 EPWMxSYNCOUT
CMPCEN OR 1
0
CMPDEN

DCARVT1EN
TBCTL2[SELFCLRTRREM]
DCBEVT1EN

Disable Clear
Register
EPWM1SYNCOUT 0
|
|
|
EPWMxSYNCOUT
EPWMxSYNCIN HRPCTL[PWMSYNCSELX]
ECAP1SYNCOUT CTR=CMPC UP
|
|
|
CTR=CMPC DOWN
ECAPySYNCOUT CTR=CMPD UP EPWMxSYNCPER
Other Sources CTR=CMPD DOWN CMPSS
DAC
HRPCTL[PWMSYNCSEL]

EPWMSYNCINSEL CTR=PRD
CTR=ZERO
Note: SYNCO and SYNCOUT are used interchangeably

Figure 6-52. Synchronization Chain Architecture

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6.15.1.2 ePWM Electrical Data and Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.15.1.2.1 ePWM Timing Requirements
MIN MAX UNIT
Asynchronous 2tc(EPWMCLK)
tw(SYNCIN) Sync input pulse width Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW)

6.15.1.2.2 ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER(1) MIN MAX UNIT

ADVANCE INFORMATION
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SYSCLK) cycles
Delay time, trip input active to PWM forced high
td(TZ-PWM) Delay time, trip input active to PWM forced low 25 ns
Delay time, trip input active to PWM Hi-Z

(1) 20-pF load on pin.

6.15.1.2.3 Trip-Zone Input Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.15.1.2.3.1 Trip-Zone Input Timing Requirements
MIN MAX UNIT
Asynchronous 1tc(EPWMCLK) cycles
tw(TZ) Pulse duration, TZx input low Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles

6.15.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram

EPWMCLK

tw(TZ)
(A)
TZ

td(TZ-PWM)

(B)
PWM

A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery
software.

Figure 6-53. PWM Hi-Z Characteristics

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6.15.2 High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
ADVANCE INFORMATION

6.15.2.1 HRPWM Electrical Data and Timing

6.15.2.1.1 High-Resolution PWM Characteristics
PARAMETER MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size(1) 150 310 ps

(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.

6.15.3 External ADC Start-of-Conversion Electrical Data and Timing

6.15.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(SYSCLK) cycles

6.15.3.2 ADCSOCAO or ADCSOCBO Timing Diagram

tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO

Figure 6-54. ADCSOCAO or ADCSOCBO Timing

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6.15.4 Enhanced Capture (eCAP)

The features of the eCAP module include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed by way of Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module features described in this chapter include:
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single-shot capture of up to four event time-stamps
• Continuous mode capture of time stamps in a four-deep circular buffer

ADVANCE INFORMATION
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
The capture functionality of the Type 1 eCAP is enhanced from the Type 0 eCAP with the following added
features:
• Event filter reset bit
– Writing a 1 to ECCTL2[CTRFILTRESET] clears the event filter, the modulo counter, and any pending
interrupts flags. Resetting the bit is useful for initialization and debug.
• Modulo counter status bits
– The modulo counter (ECCTL2 [MODCNTRSTS]) indicates which capture register is loaded next. In the
Type 0 eCAP, to know the current state of the modulo counter was not possible
• DMA trigger source
– eCAPxDMA was added as a DMA trigger. CEVT[1-4] can be configured as the source for eCAPxDMA.
• Input multiplexer
– ECCTL0 [INPUTSEL] selects one of 128 input signals, which are detailed in the Configuring Device Pins
for the eCAP section of the Enhanced Capture (eCAP) chapter in the .
• EALLOW protection
– EALLOW protection was added to critical registers. To maintain software compatibility with Type-0,
configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
The capture functionality of the Type 2 eCAP is enhanced from the Type 1 eCAP with the following added
features:
• Added ECAPxSYNCINSEL register
– ECAPxSYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can have
a separate SYNCIN signal.

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6.15.4.1 eCAP Block Diagram

ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
CTRPHS
(phase register−32 bit) APWM Mode

SYNC
ECAPxSYNCIN
OVF CTR_OVF CTR [0−31]
ECAPxSYNCOUT TSCTR
PWM
(counter−32 bit) Output
Delta−Mode PRD [0−31] Compare
RST X-Bar
Logic
CMP [0−31]
32

CTR=PRD
CTR [0−31]
CTR=CMP
32
PRD [0−31]
HRCTRL[HRE] ECCTL1 [ CAPLDEN, CTRRSTx]

32
32 CAP1 LD1
Polarity
ADVANCE INFORMATION

(APRD Active) LD
Select

APRD
32
shadow CMP [0−31]
HRCTRL[HRE] 32

32 HRCTRL[HRE]
32
CAP2 LD2 Polarity
(ACMP Active) LD Select Other
Event [127:16]
Sources
Prescale
Event
32 ACMP
qualifier 16
shadow ECCTL1[PRESCALE] Input
HRCTRL[HRE] [15:0]
X-Bar
32
Polarity
32 CAP3 LD3
LD Select
(APRD Shadow)

HRCTRL[HRE]
32
32 CAP4 LD4 Polarity
(ACMP Shadow) LD
Select

4 Edge Polarity Select

ECCTL1[CAPxPOL]
4

ECCTL2[CTRFILTRESET]
Interrupt Continuous /
Trigger Oneshot MODCNTRSTS
and CTR_OVF Capture Control
Flag
CTR=PRD
ECAPx Control
(to ePIE) CTR=CMP
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC

SYSCLK Capture Pulse

HRCLK HR Submodule
ECAPx_HRCAL HR Input
(to ePIE)

Figure 6-55. eCAP Block Diagram

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6.15.4.2 eCAP Synchronization

The eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from
EPWM, eCAP, or X-Bar. The SYNC signal is defined by the selection in the ECAPxSYNCINSEL[SEL] bit for
ECAPx as shown in Figure 6-56.

ECAPx

Disable 0x0
0x1 ECAPxSYNCIN
ECAPxSYNCIN EPWMxSYNCOUT
ECCTL2[SWSYNC] EXTSYNCOUT
Signals ECAPxSYNCOUT
CTR=PRD
(EPWM, ECAP, Disable
INPUTXBAR, «) Disable

ADVANCE INFORMATION
0xn SYNCSELECT[SYNCOUT]

ECCTL2[SYNCOSEL]

ECAPSYNCINSEL[SEL]

Figure 6-56. eCAP Synchronization Scheme

6.15.4.3 eCAP Electrical Data and Timing

6.15.4.3.1 eCAP Timing Requirements
MIN NOM MAX UNIT
Asynchronous 2tc(SYSCLK)
tw(CAP) Capture input pulse width Synchronous 2tc(SYSCLK) ns
With input qualifier 1tc(SYSCLK) + tw_(IQSW)

6.15.4.3.2 eCAP Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns

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6.15.5 Enhanced Quadrature Encoder Pulse (eQEP)

The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-performance
motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 6-57):
• Programmable input qualification for each pin (part of the GPIO MUX)
• Quadrature decoder unit (QDU)
• Position counter and control unit for position measurement (PCCU)
• Quadrature edge-capture unit for low-speed measurement (QCAP)
• Unit time base for speed/frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
• Quadrature Mode Adapter (QMA)
ADVANCE INFORMATION

System
control registers
To CPU
EQEPxENCLK
SYSCLK

Data bus
QCPRD
Enhanced QEP (eQEP) peripheral
QCAPCTL QCTMR
16 16

16
Quadrature
capture unit
QCTMRLAT (QCAP)
QCPRDLAT

Registers QUTMR QWDTMR

used by QUPRD QWDPRD
multiple units
32 16
QEPCTL QDECCTL
QEPSTS UTOUT 16
UTIME QWDOG
QFLG EQEPxAIN EQEPx_A
WDTOUT QMA EQEPxBIN EQEPx_B
EQEPxINT QCLK
PIE
QDIR EQEPxIIN
32 Quadrature
Position counter/ QI decoder EQEPxIOUT GPIO EQEPx_INDEX
control unit QS (QDU) MUX
EQEPxIOE
QPOSLAT (PCCU) PHE
QPOSSLAT PCSOUT EQEPxSIN
QPOSILAT EQEPxSOUT EQEPx_STROBE
EQEPxSOE
32 32 16

QPOSCNT QPOSCMP QEINT

QPOSINIT QFRC
QPOSMAX QCLR
QPOSCTL

Figure 6-57. eQEP Block Diagram

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6.15.5.1 eQEP Electrical Data and Timing

For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.15.5.1.1 eQEP Timing Requirements
MIN MAX UNIT
Synchronous(1) 2tc(SYSCLK)
tw(QEPP) QEP input period cycles
Synchronous with input qualifier 2[1tc(SYSCLK) + tw(IQSW)]
Synchronous(1) 2tc(SYSCLK)
tw(INDEXH) QEP Index Input High time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)
Synchronous(1) 2tc(SYSCLK)
tw(INDEXL) QEP Index Input Low time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)
Synchronous(1) 2tc(SYSCLK)
tw(STROBH) QEP Strobe High time cycles

ADVANCE INFORMATION
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)
Synchronous(1) 2tc(SYSCLK)
tw(STROBL) QEP Strobe Input Low time cycles
Synchronous with input qualifier 2tc(SYSCLK) + tw(IQSW)

(1) The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.

6.15.5.1.2 eQEP Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 5tc(SYSCLK) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 7tc(SYSCLK) cycles

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6.16 Communications Peripherals

6.16.1 Modular Controller Area Network (MCAN)
The Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed
real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to
detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides
data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD
feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may
coexist on the same network without any conflict provided that partial network transceivers, which can detect
and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is
compliant to ISO 11898-1:2015.

Note
ADVANCE INFORMATION

The availability of the CAN FD feature is dependent on the device's part number. Refer to the device
data sheet for more information.

Device
MCANSS

NMI Uncorrectable ECC

Correctable ECC
Configurable Interrupts (2 lines)
PIE
Counter Overflow and Clock Stop/
Wakeup

CPU BUS mcanss_tx

SYSCLK Peripheral Clock

mcanss_rx
Clock disable/
MCAN Bit Clock Bit Timing Clock
enable
Wakeup

Clock Stop and Wakeup

RESET Reset

Figure 6-58. MCAN Module Overview

The MCAN module implements the following features:

• Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015
• Full CAN FD support (up to 64 data bytes)
• AUTOSAR and SAE J1939 support
• Flexible Message RAM allocation (maximum configuration below is for a device with 4352 32-bit word
message RAM)
– Up to 32 dedicated transmit buffers
– Configurable transmit FIFO, up to 32 elements
– Configurable transmit queue, up to 32 elements
– Configurable transmit Event FIFO, up to 32 elements
– Up to 64 dedicated receive buffers
– Two configurable receive FIFOs, up to 64 elements each
– Up to 128 filter elements
• Loop-back mode for self-test
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• Maskable interrupt (two configurable interrupt lines, correctable ECC, counter overflow and clock stop/
wakeup)
• Non-maskable interrupt (uncorrectable ECC)
• Two clock domains (CAN clock/host clock)
• ECC check for Message RAM
• Clock stop and wake-up support
• Timestamp counter
Non-supported features:
• Host bus firewall
• Clock calibration
• Debug over CAN

ADVANCE INFORMATION

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6.16.2 Inter-Integrated Circuit (I2C)

The I2C module has the following features:
• Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple controller-transmitters and target-receivers
– Support for multiple target-transmitters and controller-receivers
– Combined controller transmit/receive and receive/transmit mode
– Data transfer rate from 10Kbps up to 400Kbps (Fast-mode)
• Supports voltage thresholds compatible to:
– SMBus 3.0 and below
ADVANCE INFORMATION

– PMBus 1.3 and below

• One 16-byte receive FIFO and one 16-byte transmit FIFO
• Supports two ePIE interrupts
– I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:
• Transmit Ready
• Receive Ready
• Register-Access Ready
• No-Acknowledgment
• Arbitration-Lost
• Stop Condition Detected
• Addressed-as-Target
– I2Cx_FIFO interrupts:
• Transmit FIFO interrupt
• Receive FIFO interrupt
• Module enable and disable capability
• Free data format mode
Figure 6-59 shows how the I2C peripheral module interfaces within the device.

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I2C module

I2CXSR I2CDXR

TX FIFO
FIFO Interrupt
SDA
to CPU/PIE
RX FIFO

Peripheral bus

I2CRSR I2CDRR

ADVANCE INFORMATION
Control/status
Clock registers CPU
SCL synchronizer

Prescaler

Noise filters Interrupt to

I2C INT CPU/PIE
Arbitrator

Figure 6-59. I2C Peripheral Module Interfaces

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6.16.2.1 I2C Electrical Data and Timing

Note
To meet all of the I2C protocol timing specifications, the I2C module clock must be configured in the
range from 7 MHz to 12 MHz.
A pullup resistor must be chosen to meet the I2C standard timings. In most circumstances, 2.2 kΩ of
total bus resistance to VDDIO is sufficient. For evaluating pullup resistor values for a particular design,
see the I2C Bus Pullup Resistor Calculation Application Report.

6.16.2.1.1 I2C Timing Requirements

NO. MIN MAX UNIT
Standard mode
ADVANCE INFORMATION

T0 fmod I2C module frequency 7 12 MHz

Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 4.0 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 4.0 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 250 ns
T5 tr(SDA) Rise time, SDA 1000 ns
T6 tr(SCL) Rise time, SCL 1000 ns
T7 tf(SDA) Fall time, SDA 300 ns
T8 tf(SCL) Fall time, SCL 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 4.0 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF
Fast mode
T0 fmod I2C module frequency 7 12 MHz
Hold time, START condition, SCL fall delay after
T1 th(SDA-SCL)START 0.6 µs
SDA fall
Setup time, Repeated START, SCL rise before SDA
T2 tsu(SCL-SDA)START 0.6 µs
fall delay
T3 th(SCL-DAT) Hold time, data after SCL fall 0 µs
T4 tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
T5 tr(SDA) Rise time, SDA 20 300 ns
T6 tr(SCL) Rise time, SCL 20 300 ns
T7 tf(SDA) Fall time, SDA 11.4 300 ns
T8 tf(SCL) Fall time, SCL 11.4 300 ns
Setup time, STOP condition, SCL rise before SDA
T9 tsu(SCL-SDA)STOP 0.6 µs
rise delay
Pulse duration of spikes that will be suppressed by
T10 tw(SP) 0 50 ns
filter
T11 Cb capacitance load on each bus line 400 pF

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6.16.2.1.2 I2C Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode
S1 fSCL SCL clock frequency 0 100 kHz
S2 TSCL SCL clock period 10 µs
S3 tw(SCLL) Pulse duration, SCL clock low 4.7 µs
S4 tw(SCLH) Pulse duration, SCL clock high 4.0 µs
Bus free time between STOP and START
S5 tBUF 4.7 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 3.45 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 3.45 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA

ADVANCE INFORMATION
Fast mode
S1 fSCL SCL clock frequency 0 400 kHz
S2 TSCL SCL clock period 2.5 µs
S3 tw(SCLL) Pulse duration, SCL clock low 1.3 µs
S4 tw(SCLH) Pulse duration, SCL clock high 0.6 µs
Bus free time between STOP and START
S5 tBUF 1.3 µs
conditions
S6 tv(SCL-DAT) Valid time, data after SCL fall 0.9 µs
S7 tv(SCL-ACK) Valid time, Acknowledge after SCL fall 0.9 µs
S8 II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA

6.16.2.1.3 I2C Timing Diagram

STOP START

SDA
ACK Contd...

S6 T10 S7
T5 T7 S3

SCL S4 Contd...

9th
T6 T8 clock
S2
Repeated
START STOP
S5

SDA
ACK
T2
T9
T1

SCL

9th
clock

Figure 6-60. I2C Timing Diagram

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6.16.3 Power Management Bus (PMBus) Interface

The PMBus module has the following features:
• Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
• Supports voltage thresholds compatible to:
– PMBus 1.3and below
– SMBus 3.0and below
• Support for controller and target
• Support for I2C mode
• Support for threespeeds:
– Standard Mode: Up to 100 kHz
– Fast Mode: 400 kHz
– Fast Plus Mode: 1MHz
• Packet error checking
ADVANCE INFORMATION

• CONTROL and ALERT signals

• Clock high and low time-outs
• Four-byte transmit and receive buffers
• One maskable interrupt, which can be generated by several conditions:
– Receive data ready
– Transmit buffer empty
– Target address received
– End of message
– ALERT input asserted
– Clock low time-out
– Clock high time-out
– Bus free

Note
Please see the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual to
determine which pins support Fast Plus Mode as well as full SMBUS3.0 and PMBUS1.3 specifications

PCLKCR20

SYSCLK

Div PMBCTRL
ALERT DMA

Bit clock
CTL Other registers

GPIO Mux CPU

PMBTXBUF
SCL

Shift register PMBRXBUF

SDA PMBUSA_INT PIE

PMBus Module

Figure 6-61. PMBus Block Diagram

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6.16.3.1 PMBus Electrical Data and Timing

6.16.3.1.1 PMBus Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIL Valid low-level input voltage 0.8 V
VIH Valid high-level input voltage 2.1 VDDIO V
VOL Low-level output voltage At Ipullup = 4 mA 0.4 V
IOL Low-level output current VOL ≤ 0.4 V 4 mA
Pulse width of spikes that must be
tSP 0 50 ns
suppressed by the input filter
Ii Input leakage current on each pin 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA
Ci Capacitance on each pin 10 pF

ADVANCE INFORMATION
6.16.3.1.2 PMBus Fast Plus Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fmod PMBus Module Clock Frequency(2) 20 25 MHz
3.3V Nominal Bus Voltage 10 1000(3) kHz
fSCL SCL clock frequency
5.0V Nominal Bus Voltage 10 1000(4) kHz
Bus free time between STOP and
tBUF 0.5 µs
START conditions
START condition hold time -- SDA fall
tHD;STA 0.26 µs
to SCL fall delay
Repeated START setup time -- SCL
tSU;STA 0.26 µs
rise to SDA fall delay
STOP condition setup time -- SCL rise
tSU;STO 0.26 µs
to SDA rise delay
Data hold time after SCL fall 300 ns
tHD;DAT Data hold time after SCL fall
0 ns
PMBCTRL_ZH_EN = 1 (1)
tSU;DAT Data setup time before SCL rise 50 ns
tTimeout Clock low time-out 25 35 ms
tLOW Low period of the SCL clock 0.5 µs
tHIGH High period of the SCL clock 0.26 50 µs
Cumulative clock low extend time
tLOW;SEXT From START to STOP 25 ms
(target device)
Cumulative clock low extend time
tLOW;MEXT Within each byte 10 ms
(controller device)
tr Rise time of SDA and SCL 5% to 95% 20 120 ns
tf Fall time of SDA and SCL 95% to 5% 20 120 ns

(1) This bit must be set to enable 0ns hold time/SMBUS3.0 Compliance
(2) If the max clock is used all below timings will be met with the default register configurations for the PMBUS
(3) Due to max IO drive strength of 12mA, 1MHz SCL clock is only valid for bus capacitances up to 520pF
(4) Due to max IO drive strength of 12mA, 1MHz SCL clock is only valid for bus capacitances up to 330pF

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6.16.3.1.3 PMBus Fast Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(SYSCLK)
Fmod PMBus Module Clock Frequency (2) 10 MHz
/ 32

fSCL SCL clock frequency 10 400 kHz

Bus free time between STOP and
tBUF 1.3 µs
START conditions
START condition hold time -- SDA fall
tHD;STA 0.6 µs
to SCL fall delay
Repeated START setup time -- SCL
tSU;STA 0.6 µs
rise to SDA fall delay
STOP condition setup time -- SCL rise
tSU;STO 0.6 µs
to SDA rise delay
ADVANCE INFORMATION

Data hold time after SCL fall 300 ns

tHD;DAT Data hold time after SCL fall
0 ns
PMBCTRL_INC_1[ZH+EN] = 1(1)
tSU;DAT Data setup time before SCL rise 100 ns
tTimeout Clock low time-out 25 35 ms
tLOW Low period of the SCL clock 1.3 µs
tHIGH High period of the SCL clock 0.6 50 µs
Cumulative clock low extend time
tLOW;SEXT From START to STOP 25 ms
(target device)
Cumulative clock low extend time
tLOW;MEXT Within each byte 10 ms
(controller device)
tr Rise time of SDA and SCL 5% to 95% 20 300 ns
tf Fall time of SDA and SCL 95% to 5% 20 300 ns

(1) This bit must be set to enable 0ns hold time/SMBUS3.0 Compliance
(2) If the max clock is used all below timings will be met with the default register configurations for the PMBUS

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6.16.3.1.4 PMBus Standard Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(SYSCLK)
Fmod PMBus Module Clock Frequency(2) 10 MHz
/ 32

fSCL SCL clock frequency 10 100 kHz

Bus free time between STOP and
tBUF 4.7 µs
START conditions
START condition hold time -- SDA fall
tHD;STA 4 µs
to SCL fall delay
Repeated START setup time -- SCL
tSU;STA 4.7 µs
rise to SDA fall delay
STOP condition setup time -- SCL rise
tSU;STO 4 µs
to SDA rise delay

ADVANCE INFORMATION
Data hold time after SCL fall 300 ns
tHD;DAT Data hold time after SCL fall
0 ns
PMBCTRL_INC_1[ZH+EN] = 1 (1)
tSU;DAT Data setup time before SCL rise 250 ns
tTimeout Clock low time-out 25 35 ms
tLOW Low period of the SCL clock 4.7 µs
tHIGH High period of the SCL clock 4 50 µs
Cumulative clock low extend time
tLOW;SEXT From START to STOP 25 ms
(target device)
Cumulative clock low extend time
tLOW;MEXT Within each byte 10 ms
(controller device)
tr Rise time of SDA and SCL 1000 ns
tf Fall time of SDA and SCL 300 ns

(1) This bit must be set to enable 0ns hold time/SMBUS3.0 Compliance
(2) If the max clock is used all below timings will be met with the default register configurations for the PMBUS

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6.16.4 Serial Communications Interface (SCI)

The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
ADVANCE INFORMATION

– SCIRXD: SCI receive-input pin

– Baud rate programmable to 64K different rates
• Data-word format
– 1 start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO

Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.

Figure 6-62 shows the SCI block diagram.

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TXSHF
SCITXD
Register

TXENA
SCICTL1.1
Frame
Format and Mode

Parity
Even/Odd TXEMPTY
0 1
SCICCR.6 8 SCICTL2.6

Enable
TX FIFO_0
TXINT
SCICCR.5 To CPU
TX FIFO_1 TX FIFO Interrupts TX Interrupt
88
Logic

ADVANCE INFORMATION
TX FIFO_N
TXINTENA

TXRDY SCICTL2.0
8
TXWAKE 0 1 SCICTL2.7
SCICTL1.3

SCI TX Interrupt Select Logic

WUT 8

Transmit Data
Buffer Register
SCITXBUF.7-0 Auto Baud Detect Logic

Baud Rate
MSB/LSB
LSPCLK Registers
RXSHF
SCIRXD
Register
SCIHBAUD.15-8 RXWAKE

SCILBAUD.7-0 SCICTL1.0 SCIRXST.1

RXENA

0 1
8

SCIFFENA
SCIFFTX.14 RX FIFO_0 RXINT
8 RX FIFO_1 To CPU
RX FIFO Interrupts RX Interrupt
Logic

RX FIFO_N
RXFFOVF
8 SCIFFRX.15
0 1
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6

RXENA BRKDT
RXERRINTENA
SCICTL1.0
SCIRXST.5 SCICTL1.6

SCI RX Interrupt Select Logic

8

SCIRXST.5-2
Receive Data BRKDT FE OE PE
Buffer Register
RXERROR
SCIRXBUF.7-0
SCIRXST.7

Figure 6-62. SCI Block Diagram

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6.16.5 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-
transfer rate. The SPI is normally used for communications between the MCU controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications are
supported by the controller or peripheral operation of the SPI. The port supports a 16-level, receive and transmit
FIFO for reducing CPU servicing overhead.
The SPI module features include:
• SPIPOCI: SPI peripheral-output/controller-input pin
• SPIPICO: SPI peripheral-input/controller-output pin
• SPIPTE: SPI peripheral transmit-enable pin
• SPICLK: SPI serial-clock pin
ADVANCE INFORMATION

• Two operational modes: Controller and Peripheral

• Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithm
• 16-level transmit/receive FIFO
• DMA support
• High-speed mode
• Delayed transmit control
• 3-wire SPI mode
• SPIPTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 6-63 shows the SPI CPU interfaces.

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PCLKCR8
Low-Speed
LSPCLK SYSCLK CPU
Prescaler

Bit Clock

SYSRS

Peripheral Bus
SPIPICO

SPIPOCI

ADVANCE INFORMATION
GPIO MUX SPI
SPIINT
SPICLK PIE
SPITXINT
SPIPTE

SPIRXDMA
DMA
SPITXDMA

Figure 6-63. SPI CPU Interface

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6.16.5.1 SPI Controller Mode Timings

The following section contains the SPI Controller Mode Timings.

Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPIPICO, and SPIPOCI.

6.16.5.1.1 SPI Controller Mode Timing Requirements

NO. PARAMETER (2) (BRR + 1)(1) MIN MAX UNIT
High-Speed Mode
8 tsu(POCI)M Setup time, SPIPOCI valid before SPICLK Even, Odd 0.7 ns
Setup time, SPIPOCI valid before
ADVANCE INFORMATION

8 tsu(POCI)M SPICLK(when used on pin muxed with Even, Odd 1.5 ns

PMBUS - GPIO2, 3, 9, or 32)
Setup time, SPIPOCI valid before
8 tsu(POCI)M SPICLK(when used on pin muxed with USB Even, Odd 1.5 ns
- GPIO23, or 41)
9 th(POCI)M Hold time, SPIPOCI valid after SPICLK Even, Odd 6.5 ns
Normal Mode
8 tsu(POCI)M Setup time, SPIPOCI valid before SPICLK Even, Odd 15 ns
Setup time, SPIPOCI valid before
8 tsu(POCI)M SPICLK(when used on pin muxed with Even, Odd 16.5 ns
PMBUS - GPIO2, 3, 9, or 32)
9 th(POCI)M Hold time, SPIPOCI valid after SPICLK Even, Odd 0 ns

(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
(2) GPIOs 2, 3, 9, 23, 32, or 41 do not support full High-Speed Mode(37.5MHz) SPI operation

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6.16.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER (1) (2) (4) (BRR + 1)(3) MIN MAX UNIT
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
2 tw(SPC1)M Pulse duration, SPICLK, first pulse 0.5tc(SPC)M + ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
3 tw(SPC2)M Pulse duration, SPICLK, second pulse 0.5tc(SPC)M – ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
1.5tc(SPC)M –

ADVANCE INFORMATION
Even 1.5tc(SPC)M – 3tc(SYSCLK) – 3
3tc(SYSCLK) + 3
23 td(SPC)M Delay time, SPIPTE active to SPICLK ns
1.5tc(SPC)M –
Odd 1.5tc(SPC)M – 4tc(SYSCLK) – 3
4tc(SYSCLK) + 3
1.5tc(SPC)M –
Delay time, SPIPTE active to Even 1.5tc(SPC)M – 3tc(SYSCLK) – 4
3tc(SYSCLK) + 3
23 td(SPC)M SPICLK(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) 1.5tc(SPC)M –
Odd 1.5tc(SPC)M – 4tc(SYSCLK) – 4
4tc(SYSCLK) + 3
1.5tc(SPC)M –
Even 1.5tc(SPC)M – 3tc(SYSCLK) – 3 3tc(SYSCLK) +
Delay time, SPIPTE active to 5.5
23 td(SPC)M SPICLK(when used on pin muxed with ns
USB - GPIO23 or GPIO41) 1.5tc(SPC)M –
Odd 1.5tc(SPC)M – 4tc(SYSCLK) – 3 4tc(SYSCLK) +
5.5
Even 0.5tc(SPC)M – 3 0.5tc(SPC)M + 3
24 tv(STE)M Valid time, SPICLK to SPIPTE inactive 0.5tc(SPC)M – ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
0.5tc(LSPCLK) + 3

Valid time, SPICLK to SPIPTE Even 0.5tc(SPC)M – 4 0.5tc(SPC)M + 3

24 tv(STE)M inactive(when used on pin muxed with 0.5tc(SPC)M – ns
PMBUS - GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4
0.5tc(LSPCLK) + 3
0.5tc(SPC)M +
Even 0.5tc(SPC)M – 3
Valid time, SPICLK to SPIPTE 5.5
24 tv(STE)M inactive(when used on pin muxed with 0.5tc(SPC)M – ns
USB - GPIO23 or GPIO41) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3 0.5tc(LSPCLK) +
5.5
High-Speed Mode
4 td(PICO)M Delay time, SPICLK to SPIPICO valid Even, Odd 1 ns
Delay time, SPICLK to SPIPICO
4 td(PICO)M valid(when used on pin muxed with Even, Odd 2 ns
PMBUS - GPIO2, 3, 9, or 32)
Even 0.5tc(SPC)M – 3
5 tv(PICO)M Valid time, SPIPICO valid after SPICLK ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Valid time, SPIPICO valid after Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M SPICLK(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

Normal Mode
4 td(PICO)M Delay time, SPICLK to SPIPICO valid Even, Odd 2 ns
Even 0.5tc(SPC)M – 3
5 tv(PICO)M Valid time, SPIPICO valid after SPICLK ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3

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6.16.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0 (continued)

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER (1) (2) (4) (BRR + 1)(3) MIN MAX UNIT
Valid time, SPIPICO valid after Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M SPICLK(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

(1) 10-pF load on pin for High-Speed Mode.

(2) 20-pF load on pin for Normal Mode.
(3) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
(4) GPIOs 2, 3, 9, 23, 32, or 41 do not support full High-Speed Mode(37.5MHz) SPI operation
ADVANCE INFORMATION

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6.16.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER(1) (2) (4) (BRR + 1) (3) MIN MAX UNIT
General
Even 4tc(LSPCLK) 128tc(LSPCLK)
1 tc(SPC)M Cycle time, SPICLK ns
Odd 5tc(LSPCLK) 127tc(LSPCLK)
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
2 tw(SPCH)M Pulse duration, SPICLK, first pulse 0.5tc(SPC)M – ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
3 tw(SPC2)M Pulse duration, SPICLK, second pulse 0.5tc(SPC)M + ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
2tc(SPC)M –

ADVANCE INFORMATION
23 td(SPC)M Delay time, SPIPTE valid to SPICLK Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 3 ns
3tc(SYSCLK) + 3
Delay time, SPIPTE valid to
2tc(SPC)M –
23 td(SPC)M SPICLK(when used on pin muxed with Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 4 ns
3tc(SYSCLK) + 3
PMBUS - GPIO2, 3, 9, or 32)
Delay time, SPIPTE valid to 2tc(SPC)M –
23 td(SPC)M SPICLK(when used on pin muxed with Even, Odd 2tc(SPC)M – 3tc(SYSCLK) – 3 3tc(SYSCLK) + ns
USB - GPIO23 or GPIO41) 5.5
Even –3 3
24 td(STE)M Delay time, SPICLK to SPIPTE invalid ns
Odd –3 3
Delay time, SPICLK to SPIPTE Even -4 3
24 td(STE)M invalid(when used on pin muxed with ns
PMBUS - GPIO2, 3, 9, or 32) Odd -4 3

Delay time, SPICLK to SPIPTE Even –3 5.5

24 td(STE)M invalid(when used on pin muxed with ns
USB - GPIO23 or GPIO41) Odd –3 5.5

High-Speed Mode
Even 0.5tc(SPC)M – 2
4 td(PICO)M Delay time, SPIPICO valid to SPICLK ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
Delay time, SPIPICO valid to SPICLK Even 0.5tc(SPC)M – 3
4 td(PICO)M (when used on pin muxed with PMBUS ns
- GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3

Even 0.5tc(SPC)M – 3
5 tv(PICO)M Valid time, SPIPICO valid after SPICLK ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Valid time, SPIPICO valid after SPICLK Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M (when used on pin muxed with PMBUS ns
- GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

Normal Mode
Even 0.5tc(SPC)M – 2
4 td(PICO)M Delay time, SPIPICO valid to SPICLK ns
Odd 0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
Even 0.5tc(SPC)M – 3
5 tv(PICO)M Valid time, SPIPICO valid after SPICLK ns
Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Valid time, SPIPICO valid after SPICLK Even 0.5tc(SPC)M – 4.5
5 tv(PICO)M (when used on pin muxed with PMBUS ns
- GPIO2, 3, 9, or 32) Odd 0.5tc(SPC)M – 0.5tc(LSPCLK) – 4.5

(1) 10-pF load on pin for High-Speed Mode.

(2) 20-pF load on pin for Normal Mode.
(3) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
(4) GPIOs 2, 3, 9, 23, 32, or 41 do not support full High-Speed Mode(37.5MHz) SPI operation

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6.16.5.1.4 SPI Controller Mode Timing Diagrams

1

SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Controller out data
ADVANCE INFORMATION

SPIPICO is valid
8
9
Controller out
SPIPOCI data must be valid

23 24

SPIPTE
A. On the trailing end of the word, SPIPTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.

Figure 6-64. SPI Controller Mode External Timing (Clock Phase = 0)

1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Controller out data
SPIPICO is valid

8
9
Controller out
SPIPOCI data must be valid

24
23
SPIPTE

A. On the trailing end of the word, SPIPTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.

Figure 6-65. SPI Controller Mode External Timing (Clock Phase = 1)

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6.16.5.2 SPI Peripheral Mode Timings

The following section contains the SPI Peripheral Mode Timings.
6.16.5.2.1 SPI Peripheral Mode Timing Requirements
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK, first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK, second pulse 2tc(SYSCLK) – 1 ns
19 tsu(PICO)S Setup time, SPIPICO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(PICO)S Hold time, SPIPICO valid after SPICLK 1.5tc(SYSCLK) ns
Setup time, SPIPTE valid before SPICLK
2tc(SYSCLK) + 15 ns
(Clock Phase = 0)
25 tsu(STE)S
Setup time, SPIPTE valid before SPICLK

ADVANCE INFORMATION
2tc(SYSCLK) + 15 ns
(Clock Phase = 1)
26 th(STE)S Hold time, SPIPTE invalid after SPICLK 1.5tc(SYSCLK) ns

6.16.5.2.2 SPI Peripheral Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
NO. PARAMETER(1) MIN MAX UNIT
Delay time, SPICLK to SPIPOCI valid
15 td(POCI)S 17 ns
(non-high speed mode)
Delay time, SPICLK to SPIPOCI valid
12.5 ns
(high-speed mode)
Delay time, SPICLK to SPIPOCI valid
(high-speed mode)(when used on pins 14 ns
15 td(POCI)S
muxed with PMBUS - GPIO2, 3, 9, or 32)
Delay time, SPICLK to SPIPOCI valid
(high-speed mode)(when used on pins 16.7 ns
muxed with USB - GPIO23 or 41)
16 tv(POCI)S Valid time, SPIPOCI valid after SPICLK 0 ns

(1) 20-pF load on pin.

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6.16.5.2.3 SPI Peripheral Mode Timing Diagrams

12

SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15 16
ADVANCE INFORMATION

SPIPOCI SPIPOCI data is valid

19
20
SPIPICO data
SPIPICO must be valid

25 26

SPIPTE

Figure 6-66. SPI Peripheral Mode External Timing (Clock Phase = 0)

12

SPICLK
(clock polarity = 0)
13 14

SPICLK
(clock polarity = 1)

15

SPIPOCI SPIPOCI data is valid Data valid Data valid

19 16
20

SPIPICO SPIPICO data

must be valid
25 26

SPIPTE

Figure 6-67. SPI Peripheral Mode External Timing (Clock Phase = 1)

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6.16.6 Local Interconnect Network (LIN)

This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN 2.1
standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial interface
designed for applications where the CAN protocol may be too expensive to implement, such as small
subnetworks for cabin comfort functions like interior lighting or window control in an automotive application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-
commander and multiple-responder with a message identification for multicast transmission between any
network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an SCI.
The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a universal
asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the register/bit

ADVANCE INFORMATION
usage in different modes. Because of this, code written for this module cannot be directly ported to the stand-
alone SCI module and vice versa.
The LIN module has the following features:
• Compatibility with LIN 1.3, 2.0 and 2.1 protocols
• Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)
• Two external pins: LINRX and LINTX
• Multibuffered receive and transmit units
• Identification masks for message filtering
• Automatic commander header generation
– Programmable synchronization break field
– Synchronization field
– Identifier field
• Responder automatic synchronization
– Synchronization break detection
– Optional baud rate update
– Synchronization validation
• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver
• Automatic wake-up support
– Wakeup signal generation
– Expiration times on wakeup signals
• Automatic bus idle detection
• Error detection
– Bit error
– Bus error
– No-response error
– Checksum error
– Synchronization field error
– Parity error
• Capability to use direct memory access (DMA) for transmit and receive data
• Two interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error, and status
• Support for LIN 2.0 checksum
• Enhanced synchronizer finite state machine (FSM) support for frame processing
• Enhanced handling of extended frames
• Enhanced baud rate generator

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• Update wakeup/go to sleep

READ DATA BUS

WRITE DATA BUS

ADDRESS BUS

CHECKSUM
CALCULATOR INTERFACE
ADVANCE INFORMATION

ID PARTY
CHECKER

BIT
MONITOR

TXRX ERROR
DETECTOR (TED)

TIME-OUT
CONTROL

COUNTER

LINRX/
SCIRX COMPARE

LINTX/ MASK 8 RECEIVE DMA

SCITX FSM
FILTER BUFFERS CONTROL
8 TRANSMIT
SYNCHRONIZER
BUFFERS

Figure 6-68. LIN Block Diagram

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6.16.7 Fast Serial Interface (FSI)

The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust
high-speed communications. The FSI is designed to ensure data robustness across many system conditions
such as chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as
CRC, start- and end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified
after receipt without additional CPU interaction. Line breaks can be detected using periodic transmissions, all
managed and monitored by hardware. The FSI is also tightly integrated with other control peripherals on the
device. To ensure that the latest sensor data or control parameters are available, frames can be transmitted on
every control loop period. An integrated skew-compensation block has been added on the receiver to handle
skew that may occur between the clock and data signals due to a variety of factors, including trace-length
mismatch and skews induced by an isolation chip. With embedded data robustness checks, data-link integrity
checks, skew compensation, and integration with control peripherals, the FSI can enable high-speed, robust
communication in any system. These and many other features of the FSI follow.

ADVANCE INFORMATION
The FSI module includes the following features:
• Independent transmitter and receiver cores
• Source-synchronous transmission
• Dual data rate (DDR)
• One or two data lines
• Programmable data length
• Skew adjustment block to compensate for board and system delay mismatches
• Frame error detection
• Programmable frame tagging for message filtering
• Hardware ping to detect line breaks during communication (ping watchdog)
• Two interrupts per FSI core
• Externally triggered frame generation
• Hardware- or software-calculated CRC
• Embedded ECC computation module
• Register write protection
• DMA support
• SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (60 MHz) at dual data rate (120Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis.
The Fast Serial Interface (FSI) Skew Compensation Application Report provides example software on how to
configure and set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in
the FSI Transmitter section and the FSI Receiver section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual, respectively.

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6.16.7.1 FSI Transmitter

The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU (or the CLA) program,
control, and monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU, CLA,
and the DMA.
The transmitter has the following features:
• Automated ping frame generation
• Externally triggered ping frames
• Externally triggered data frames
• Software-configurable frame lengths
• 16-word data buffer
• Data buffer underrun and overrun detection
ADVANCE INFORMATION

• Hardware-generated CRC on data bits

• Software ECC calculation on select data
• DMA support
• CLA task triggering
Figure 6-69 shows the FSITX CPU interface. Figure 6-70 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLK

PCLKCR18

SYSCLK

SYSRSN

C28x ePIE

FSITXyINT1

FSITXyINT2

CLA
Register Interface

Registers

FSITXyCLK
GPIO MUX

FSITXyD0
DMA FSITX
FSITXyD1
FSITXyDMA
Trigger Muxes(A)

32

A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.

Figure 6-69. FSITX CPU Interface

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FSITX
PLLRAWCLK

SYSRSN

SYSCLK
FSI Mode:
Transmit Clock TXCLKIN
TXCLK = TXCLKIN/2
Generator SPI Signaling Mode:
Register Interface TXCLK = TXCLKIN

Core Reset
FSITXINT1
Control Registers, TXCLK
FSITXINT2 Interrupt Management
FSITX_DMA_EVT Ping Time-out Counter
TXD0
Transmitter Core

External Frame Triggers TXD1

ADVANCE INFORMATION
Transmit Data
Buffer

ECC Logic

Figure 6-70. FSITX Block Diagram

6.16.7.1.1 FSITX Electrical Data and Timing

6.16.7.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER(1) MIN MAX UNIT
1 tc(TXCLK) Cycle time, TXCLK 16.67 ns
Cycle time, TXCLK(when any FSI signal is
1 tc(TXCLK) used on pins muxed with PMBUS - GPIO2, 3, 26.67 ns
9, or 32)
2 tw(TXCLK) Pulse width, TXCLK low or TXCLK high (0.5tc(TXCLK)) – 1 (0.5tc(TXCLK)) + 1 ns
Delay time, TXCLK rising or falling toTXD
3 td(TXCLK–TXD) (0.25tc(TXCLK)) – 2 (0.25tc(TXCLK)) + 2 ns
valid
Delay time, TXCLK rising or falling toTXD
3 td(TXCLK–TXD) valid(when used on pin muxed with PMBUS - (0.25tc(TXCLK)) – 2 (0.25tc(TXCLK)) + 2.5 ns
GPIO2, 3, 9, or 32)
TXCLK delay compensation at
4 td(TXCLK) 9.4 30 ns
TX_DLYLINE_CTRL[TXCLK_DLY]=31
TXD0 delay compensation at
5 td(TXD0) 9.4 30 ns
TX_DLYLINE_CTRL[TXD0_DLY]=31
TXD1 delay compensation at
6 td(TXD1) 9.4 30 ns
TX_DLYLINE_CTRL[TXD1_DLY]=31
Incremental delay of each delay line element
7 td(DELAY_ELEMENT) 0.29 1 ns
for TXCLK, TXD0, and TXD1

(1) 10-pF load on pin.

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6.16.7.1.1.2 FSITX Timings

FSITXCLK 2

FSITXD0

FSITXD1
3

Figure 6-71. FSITX Timings

ADVANCE INFORMATION

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6.16.7.2 FSI Receiver

The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they pass
through an optional programmable delay line. The receiver core handles the data framing, CRC computation,
and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is
asynchronous to the device system clock.
The receiver control registers let the CPU program (or the CLA), control, and monitor the operation of the FSIRX.
The receive data buffer is accessible by the CPU, CLA, and the DMA.
The receiver core has the following features:
• 16-word data buffer
• Multiple supported frame types
• Ping frame watchdog
• Frame watchdog

ADVANCE INFORMATION
• CRC calculation and comparison in hardware
• ECC detection
• Programmable delay line control on incoming signals
• DMA support
• SPI compatibility mode
• CLA task triggering
Figure 6-72 shows the FSIRX CPU interface. Figure 6-73 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18

SYSCLK

SYSRSN

C28x ePIE

FSIRXyINT1
FSIRXyINT2

CLA
Register Interface

Registers

FSIRXyCLK
GPIO MUX

FSIRXyD0
DMA FSIRX
FSIRXyD1

FSIRXyDMA

Figure 6-72. FSIRX CPU Interface

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FSIRX
SYSRSn

SYSCLK

Frame Watchdog

Register Interface
Core Reset
FSIRXINT1 Control Registers,
FSIRXINT2 Interrupt Management
RXCLK
FSIRX_DMA_EVT Ping Watchdog
Receiver Core Skew
RXD0
Control

RXD1
ADVANCE INFORMATION

Receive Data
Buffer
ECC Check
Logic

Figure 6-73. FSIRX Block Diagram

6.16.7.2.1 FSIRX Electrical Data and Timing

6.16.7.2.1.1 FSIRX Timing Requirements
NO. MIN MAX UNIT
1 tc(RXCLK) Cycle time, RXCLK 16.67 ns
Cycle time, RXCLK(when any FSI signal is
1 tc(RXCLK) used on pins muxed with PMBUS - GPIO2, 3, 26.67 ns
9, or 32)
2 tw(RXCLK) Pulse width, RXCLK low or RXCLK high. 0.35tc(RXCLK) 0.65tc(RXCLK) ns
Setup time with respect to RXCLK, applies to
3 tsu(RXCLK–RXD) 1.7 ns
both edges of the clock
Setup time with respect to RXCLK, applies
3 tsu(RXCLK–RXD) to both edges of the clock(when used on pin 2.6 ns
muxed with PMBUS - GPIO2, 3, 9, or 32)
Hold time with respect to RXCLK, applies to
4 th(RXCLK–RXD) 2 ns
both edges of the clock

6.16.7.2.1.2 FSIRX Switching Characteristics

NO. PARAMETER(1) MIN MAX UNIT
RXCLK delay compensation at
1 td(RXCLK) 9.7 30 ns
RX_DLYLINE_CTRL[RXCLK_DLY]=31
RXD0 delay compensation at
2 td(RXD0) 9.7 30 ns
RX_DLYLINE_CTRL[RXD0_DLY]=31
RXD1 delay compensation
3 td(RXD1) 9.7 30 ns
at RX_DLYLINE_CTRL[RXD1_DLY]=31
Incremental delay of each delay line element
4 td(DELAY_ELEMENT) 0.29 1 ns
for RXCLK, RXD0, and RXD1
Delay skew introduced between RXCLK-
TDM1 tskew(TDM_CLK-TDM_Dx ) -3 3 ns
TDM_CLK delay and RXDx-TDM_Dx delays
TDM1 td(RXCLK-TDM_CLK ) Delay time, RXCLK input to TDM_CLK output 2 14.5 ns

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6.16.7.2.1.2 FSIRX Switching Characteristics (continued)

NO. PARAMETER(1) MIN MAX UNIT
TDM2 td(RXD0-TXD0) Delay time, RXD0 input to TXD0 output 2 14.5 ns
TDM3 td(RXD1-TXD1) Delay time, RXD1 input to TXD1 output 2 14.5 ns

(1) 10-pF load on pin.

6.16.7.2.1.3 FSIRX Timings

FSIRXCLK 2

ADVANCE INFORMATION
FSIRXD0

FSIRXD1
3

Figure 6-74. FSIRX Timings

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6.16.7.3 FSI SPI Compatibility Mode

The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In this
mode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the
FSI is able to physically interface with a SPI in this mode, the external device must be able to encode and
decode an FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases with
the exception of the preamble and postamble. The FSI provides the same data validation and frame checking
as if it was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the ping
frame watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of SPI compatibility
mode follows:
• Data will transmit on rising edge and receive on falling edge of the clock.
• Only 16-bit word size is supported.
• TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
ADVANCE INFORMATION

• No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
• No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phase
is finished.
• It is not possible to transmit in the SPI peripheral configuration because the FSI TXCLK cannot take an
external clock source.
6.16.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Special timings are not required for the FSIRX in SPI signaling mode. FSIRX timings listed in the FSIRX Timing
Requirements table are applicable in SPI compatibility mode. Setup and Hold times are only valid on the falling
edge of FSIRXCLK because this is the active edge in SPI signaling mode.
6.16.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO. PARAMETER(1) MIN MAX UNIT
1 tc(TXCLK) Cycle time, TXCLK 16.67 ns
Cycle time, TXCLK(when any FSI signal is
1 tc(TXCLK) used on pins muxed with PMBUS - GPIO2, 3, 26.67 ns
9, or 32)
2 tw(TXCLK) Pulse width, TXCLK low or TXCLK high (0.5tc(TXCLK)) – 1 (0.5tc(TXCLK)) + 1 ns
3 td(TXCLKH–TXD0) Delay time, TXD0 valid after TXCLK high 3 ns
4 td(TXD1-TXCLK) Delay time, TXCLK high after TXD1 low tw(TXCLK) – 3 ns
5 td(TXCLK-TXD1) Delay time, TXD1 high after TXCLK low tw(TXCLK) ns

(1) 10-pF load on pin

6.16.7.3.1.2 FSITX SPI Signaling Mode Timings

1

2
FSITXCLK
3

FSITXD0

5
4
FSITXD1

Figure 6-75. FSITX SPI Signaling Mode Timings

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6.16.8 Universal Serial Bus (USB)

The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
• USB 2.0 full-speed and low-speed operation
• Integrated PHY
• Three transfer types: control, interrupt, and bulk
• 32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB of dedicated endpoint memory
Figure 6-76 shows the USB block diagram.

ADVANCE INFORMATION
Endpoint Control

Transmit
EP0 –31
Control
Receive
CPU Interface
Interrupt Interrupts
Host
Combine Control
Transaction
Endpoints
Scheduler
EP Reg.
Decoder

Common CPU Bus

UTM Packet FIFO RAM
Synchronization Encode/Decode Controller Regs
Rx Rx
Data Sync Packet Encode
Buff Buff Cycle
Control
HNP/SRP Packet Decode Tx Tx
Buff Buff
USB FS/LS
PHY FIFO
Timers CRC Gen/Check Cycle Control
Decoder
USB DataLines
D+ andD-

Figure 6-76. USB Block Diagram

Note
The accuracy of the on-chip zero-pin oscillator (see the INTOSC Characteristics section) will not
meet the accuracy requirements of the USB protocol. An external clock source must be used for
applications using USB. For applications using the USB boot mode, see the Boot ROM and Peripheral
Booting section for clock frequency requirements.

6.16.8.1 USB Electrical Data and Timing

6.16.8.1.1 USB Input Ports DP and DM Timing Requirements
MIN MAX UNIT
V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic-low level 0.8 V
VIH Static SE input logic-high level 2.0 V
VDI Differential input voltage 0.2 V

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6.16.8.1.2 USB Output Ports DP and DM Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH D+, D– single-ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D– single-ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D– impedance 28 44 Ω
Full speed, differential, CL = 50 pF, 10%/90%,
tr Rise time 4 20 ns
Rpu on D+
Full speed, differential, CL = 50 pF, 10%/90%,
tf Fall time 4 20 ns
Rpu on D+
ADVANCE INFORMATION

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7 Detailed Description
7.1 Overview
The TMS320F28P55x (F28P55x) is a member of the C2000™ real-time microcontroller family of scalable,
ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power
density, high switching frequencies, and supporting the use of GaN and SiC technologies.
These include such applications as:
• Industrial motor drives
• Motor control
– Traction inverter motor control
– HVAC motor control
– Mobile robot motor control
• Solar inverters

ADVANCE INFORMATION
– Central inverter
– Micro inverter
– String inverter
• Digital power
• Electrical vehicles and transportation
• EV charging infrastructure
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 150 MIPS of signal-
processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM.
The C28x CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy
Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended
instruction sets enable IEEE double-precision 32-bit floating-point math. Finally, the Control Law Accelerator
(CLA) enables an additional 150 MIPS per core of independent processing ability.
To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update
(LFU) have been added to F28P55x.
High-performance analog blocks are tightly integrated with the processing and control units to provide optimal
real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to
39 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of
oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware
redundancy checker has been added that provides the ability to compare ADC conversion results from multiple
ADC modules for consistency without additional CPU cycles. Three Programmable Gain Amplifiers(PGAs) are
present, supporting unity gain as well as up to 64x of non-inverting gain. Twenty-four frequency-independent
PWMs, 16 with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to
advanced multilevel power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Industry-standard protocols like CAN FD and USB 2.0 are available on this device. The Fast Serial Interface
(FSI) enables up to 200 Mbps of robust communications across an isolation boundary. Enhancements have
been made to the PMBUS module to support Fast Plus mode.
Want to learn more about features that make C2000 MCUs the right choice for your real-time control system?
Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™
real-time control MCUs page.

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7.2 Functional Block Diagram

Figure 7-1 shows the CPU system and associated peripherals.

C28x CPU
(150 MHz)
FPU32 CLA
Boot ROM
TMU (150 MHz)
VCRC
Secure ROM

Flash Bank0
128 Sectors, 256KB CLA to CPU MSG RAM
SYSTEM CONTROL
CPU Timers
XTAL Flash Bank1 CPU to CLA MSG RAM
INTOSC1, INTOSC2 128 Sectors, 256KB
PLL
ePIE
Windowed WD Flash Bank2 CLA Data ROM
NMI WD 128 Sectors, 256KB
CLA Program ROM
Flash Bank3
ADVANCE INFORMATION

128 Sectors, 256KB

SECURITY
JTAG Lock Flash Bank4 CLA to DMA MSG RAM
Secure Boot 32 Sectors, 64 KB
DMA to CLA MSG RAM

M0-M1 RAM
4KB
DIAGNOSTICS Buses Legend
DCC
MPOST LS0-LS9 RAM CPU
ERAD 64KB
NNPU CLA
JTAG/cJTAG
DMA

GS0-GS3 RAM NNPU

64KB DMA
OTHERS
EPG 6 Channels Secure Memories Shown in Red

PF1 PF3 PF4 PF2 PF7 PF8 PF9 PF10 PF11 PF12

Result Data 1x PMBUS 2x CAN FD 1x LIN 3x SCI 2x CLB 1x USB 1x AES LFU
24x ePWM Channels
4x CMPSS NNPU 2x I2C
(16Ch Hi-Res Capable) 5x 12-Bit ADC 65x GPIO 2x SPI
1x FSI RX
Input XBAR
2x eCAP 1x Buffered DAC 1x FSI TX
Output XBAR
ePWM XBAR
3x eQEP CLB XBAR
3x PGA
(CW/CCW Support)
CLB Input XBAR
CLB Output XBAR

A. The internal DAC from one of the CMPSS modules can be configured as an output DAC.
B. The LIN module can also be used as a SCI module.

Figure 7-1. Functional Block Diagram

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7.3 Memory
7.3.1 Memory Map
The Memory Map table describes the memory map. See the Memory Controller Module section of the System
Control chapter in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual.
Table 7-1. Memory Map
CPU1.CLA1
START CPU1.DMA CPU1.CLA1 ECC/
MEMORY SIZE (x16) END ADDRESS PROGRAM SECURITY PART NUMBER
ADDRESS ACCESS DATA ACCESS Parity
ACCESS
M0 RAM 1024 0x0000_0000 0x0000_03FF - - - ECC - All
M1 RAM 1024 0x0000_0400 0x0000_07FF - - - ECC - All
PIE Vector Table 512 0x0000_0D00 0x0000_0EFF - - - Parity - All
CLAtoCPU MSG
128 0x0000_1480 0x0000_14FF - YES - Parity - All
RAM
CPUtoCLA MSG
128 0x0000_1500 0x0000_157F - YES - Parity - All

ADVANCE INFORMATION
RAM
CLAtoDMA MSG
128 0x0000_1680 0x0000_16FF YES YES - Parity - All
RAM
DMAtoCLA MSG
128 0x0000_1700 0x0000_177F YES YES - Parity - All
RAM
F28P559SJ9-
Q1,F28P550SJ9,F28P
559SG9-
LS8 RAM - CLA
8192 0x0000_4000 0x0000_5FFF - - YES Parity YES Q1,F28P550SG9,F28P
Prog
550SG8,F28P559SG8-
Q1, F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-
Q1,F28P550SJ9,F28P
559SG9-
LS9 RAM - CLA
8192 0x0000_6000 0x0000_7FFF - - YES Parity YES Q1,F28P550SG9,F28P
Prog
550SG8,F28P559SG8-
Q1, F28P559SJ6-
Q1,F28P550SJ6
LS0 RAM 2048 0x0000_8000 0x0000_87FF - YES YES Parity YES All
LS1 RAM 2048 0x0000_8800 0x0000_8FFF - YES YES Parity YES All
LS2 RAM 2048 0x0000_9000 0x0000_97FF - YES YES Parity YES All
LS3 RAM 2048 0x0000_9800 0x0000_9FFF - YES YES Parity YES All
LS4 RAM 2048 0x0000_A000 0x0000_A7FF - YES YES Parity YES All
LS5 RAM 2048 0x0000_A800 0x0000_AFFF - YES YES Parity YES All
LS6 RAM 2048 0x0000_B000 0x0000_B7FF - YES YES Parity YES All
LS7 RAM 2048 0x0000_B800 0x0000_BFFF - YES YES Parity YES All
GS0 RAM 8192 0x0000_C000 0x0000_DFFF YES - - Parity - All
GS1 RAM 8192 0x0000_E000 0x0000_FFFF YES - - Parity - All
F28P559SJ9-
Q1,F28P550SJ9,F28P
559SG9-
CLA Data ROM 4096 0x0000_F000 0x0000_FFFF - YES - Parity - Q1,F28P550SG9,F28P
550SG8,F28P559SG8-
Q1, F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-
Q1,F28P550SJ9,F28P
GS2 RAM 8192 0x0001_0000 0x0001_1FFF YES - - Parity - 559SJ2-
Q1,F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-
Q1,F28P550SJ9,F28P
GS3 RAM 8192 0x0001_2000 0x0001_3FFF YES - - Parity - 559SJ2-Q1,
F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-
Q1,F28P550SJ9,F28P
559SG9-
Q1,F28P550SG9,F28P
559SG8-Q1,
LS8 RAM - CPU 8192 0x0001_4000 0x0001_5FFF - - - Parity YES
F28P559SG2-
Q1,F28P559SJ2-Q1,
F28P550SG8,
F28P559SJ6-
Q1,F28P550SJ6

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Table 7-1. Memory Map (continued)

CPU1.CLA1
START CPU1.DMA CPU1.CLA1 ECC/
MEMORY SIZE (x16) END ADDRESS PROGRAM SECURITY PART NUMBER
ADDRESS ACCESS DATA ACCESS Parity
ACCESS
F28P559SJ9-
Q1,F28P550SJ9,F28P
559SG9-
Q1,F28P550SG9,F28P
559SG8-Q1,
LS9 RAM - CPU 8192 0x0001_6000 0x0001_7FFF - - - Parity YES
F28P559SG2-
Q1,F28P559SJ2-Q1,
F28P550SG8,
F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-
Q1,F28P550SJ9,F28P
559SG9-
USB RAM 2048 0x0004_1000 0x0004_17FF YES - - - -
Q1,F28P550SG9,
F28P559SJ6-
Q1,F28P550SJ6
MCANA
ADVANCE INFORMATION

Message RAM
2048 0x0005_8000 0x0005_87FF YES - - ECC - All
(CPU Access
mode)
MCANA
Message RAM
4096 0x0005_8000 0x0005_8FFF YES - - ECC - All
(Peripheral
mode)
MCANB
Message RAM
4096 0x0005_A000 0x0005_AFFF YES - - ECC - All
(Peripheral
mode)
MCANB
Message RAM
2048 0x0005_A000 0x0005_A7FF YES - - ECC - All
(CPU Access
mode)
TI OTP Bank 0 1536 0x0007_2000 0x0007_25FF - - - ECC - All
UID_REGS 6 0x0007_2172 0x0007_2177 - - - ECC - All
F28P559SJ9-
Q1,F28P550SJ9,F28P
TI OTP Bank 1 1536 0x0007_3000 0x0007_35FF - - - ECC - 559SJ2-Q1,
F28P559SJ6-
Q1,F28P550SJ6
TI OTP Bank 2 1536 0x0007_4000 0x0007_45FF - - - ECC - All
F28P559SJ9-
Q1,F28P550SJ9,F28P
TI OTP Bank 3 1536 0x0007_5000 0x0007_55FF - - - ECC - 559SJ2-Q1,
F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
TI OTP Bank 4 1536 0x0007_6000 0x0007_65FF - - - ECC - F28P559SJ6-Q1,
F28P550SJ6,
F28P559SG9-Q1,
F28P550SG9
DCSM BANK0
512 0x0007_8000 0x0007_81FF - - - ECC YES All
Z1 OTP
DCSM BANK0
512 0x0007_8200 0x0007_83FF - - - ECC YES All
Z2 OTP
F28P559SJ9-
Q1,F28P550SJ9,F28P
User OTP Bank
1024 0x0007_8800 0x0007_8BFF - - - ECC - 559SJ2-Q1,
1
F28P559SJ6-
Q1,F28P550SJ6
User OTP Bank
1024 0x0007_9000 0x0007_93FF - - - ECC - All
2
F28P559SJ9-
Q1,F28P550SJ9,F28P
User OTP Bank
1024 0x0007_9800 0x0007_9BFF - - - ECC - 559SJ2-Q1,
3
F28P559SJ6-
Q1,F28P550SJ6
User OTP Bank F28P559SG9-Q1,
1024 0x0007_A000 0x0007_A3FF - - - ECC -
4 F28P550SG9
Flash Bank 0 131072 0x0008_0000 0x0009_FFFF - - - ECC YES All

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Table 7-1. Memory Map (continued)

CPU1.CLA1
START CPU1.DMA CPU1.CLA1 ECC/
MEMORY SIZE (x16) END ADDRESS PROGRAM SECURITY PART NUMBER
ADDRESS ACCESS DATA ACCESS Parity
ACCESS
F28P559SJ9-
Q1,F28P550SJ9,F28P
Flash Bank 1 131072 0x000A_0000 0x000B_FFFF - - - ECC YES 559SJ2-Q1,
F28P559SJ6-
Q1,F28P550SJ6
Flash Bank 2 131072 0x000C_0000 0x000D_FFFF - - - ECC YES All
F28P559SJ9-
Q1,F28P550SJ9,F28P
Flash Bank 3 131072 0x000E_0000 0x000F_FFFF - - - ECC YES 559SJ2-Q1,
F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,F28P559
SJ2-Q1, F28P559SJ6-
Flash Bank 4 32768 0x0010_0000 0x0010_7FFF - - - ECC YES
Q1, F28P550SJ6,
F28P559SG9-Q1,

ADVANCE INFORMATION
F28P550SG9
Z1-SecureBoot
3072 0x003F_4000 0x003F_4BFF - - - Parity YES All
Functions
Z1-Safe
1536 0x003F_4C00 0x003F_51FF - - - Parity YES All
Functions
Z2-Safe
1536 0x003F_5600 0x003F_5BFF - - - Parity YES All
Functions
CPU STL 9216 0x003F_5C00 0x003F_7FFF - - - Parity - All
Boot ROM 32768 0x003F_8000 0x003F_FFFF - - - Parity - All
PIE Vector Table
512 0x0100_0900 0x0100_0AFF - - - Parity - All
Swap
F28P559SJ9-
Q1,F28P550SJ9,F28P
559SG9-
CLA Data ROM
4096 0x0100_1000 0x0100_1FFF - - - Parity - Q1,F28P550SG9,F28P
(CPU Mapped)
550SG8,F28P559SG8-
Q1, F28P559SJ6-
Q1,F28P550SJ6
TI OTP Bank 0
192 0x0107_0400 0x0107_04BF - - - - - All
ECC
F28P559SJ9-
Q1,F28P550SJ9,F28P
TI OTP Bank 1
192 0x0107_0600 0x0107_06BF - - - - - 559SJ2-Q1,
ECC
F28P559SJ6-
Q1,F28P550SJ6
TI OTP Bank 2
192 0x0107_0800 0x0107_08BF - - - - - All
ECC
F28P559SJ9-
Q1,F28P550SJ9,F28P
TI OTP Bank 3
192 0x0107_0A00 0x0107_0ABF - - - - - 559SJ2-Q1,
ECC
F28P559SJ6-
Q1,F28P550SJ6
F28P559SJ9-Q1,
F28P550SJ9,
F28P559SJ2-Q1,
TI OTP Bank 4
192 0x0107_0C00 0x0107_0CBF - - - - - F28P559SJ6-Q1,
ECC
F28P550SJ6,
F28P559SG9-Q1,
F28P550SG9

7.3.1.1 Dedicated RAM (Mx RAM)

The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are small
nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
7.3.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are accessible to the CPU and CLA. All LSx RAM blocks have parity. These
memories are secure and have CPU access protection (CPU write/CPU fetch).

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7.3.1.3 Global Shared RAM (GSx RAM)

Global shared RAMs (GSx RAMs) are accessible from the CPU and DMA. The CPU and DMA have full read
and write access to these memories. All GSx RAM blocks have parity. The GSx RAMs have access protection
(CPU write/CPU fetch/DMA write/HIC write).
7.3.1.4 Message RAM
There are two types of message RAMs on this device that can be used to share between CPU, CLA and DMA.
CLA-CPU message RAM shares data between the CLA and CPU while the CLA-DMA message RAM shares
data between the CLA and DMA.
7.3.2 Control Law Accelerator (CLA) Memory Map
Table 7-2 shows the CLA data ROM memory map.
Table 7-2. CLA Data ROM Memory Map
ADVANCE INFORMATION

MEMORY START ADDRESS LENGTH

FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

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7.3.3 Flash Memory Map

On the F28P55x devices, five flash banks (1084KB) are available. 4 banks are 256KB and the 5th bank is 64KB
in size. Flash operations (erase and program) are performed at the bank level. Code cannot be executed from
the same bank as an operation is being performed. Code can be allocated in a different flash bank, SRAM, or
ROM while these operations are in progress. The Addresses of Flash Sectors table lists the addresses of flash
sectors available for each part number.
7.3.3.1 Addresses of Flash Sectors
Table 7-3. Flash Memory Map
PART ADDRESS ECC ADDRESS
SECTOR
NUMBER SIZE START END SIZE START END
OTP Sectors
TI OTP Bank 0
1520 x 16 0x0007 2000 0x0007 25EF 190 x 16 0x0107 0400 0x0107 04BD

ADVANCE INFORMATION
(Unsecure)
All F28P55x TI OTP Bank 0
16 x 16 0x0007 25F0 0x0007 25FF 2 x 16 0x0107 04BE 0x0107 04BE
(Secure)
TI OTP Bank 2 1536 x 16 0x0007 4000 0x0007 45FF 192 x 16 0x0107 0800 0x0107 08BF
TI OTP Bank 1 1536 x 16 0x0007 3000 0x0007 35FF 192 x 16 0x0107 0600 0x0107 06BF
F28P55xSJx TI OTP Bank 3 1536 x 16 0x0007 5000 0x0007 55FF 192 x 16 0x0107 0A00 0x0107 0ABF
TI OTP Bank 4 1536 x 16 0x0007 6000 0x0007 65FF 192 x 16 0x0107 0C00 0x0107 0CBF
User
configurable
512 x 16 0x0007 8000 0x0007 81FF 64 x 16 0x0107 1000 0x0107 103F
DCSM Z1 OTP
Bank 0
User
All F28P55x configurable
512 x 16 0x0007 8200 0x0007 83FF 64 x 16 0x0107 1040 0x0107 107F
DCSM Z2 OTP
Bank 0
User
configurable 1K x 16 0x0007 9000 0x0007 93FF 128 x 16 0x0107 1100 0x0107 117F
OTP Bank 2
User
configurable 1K x 16 0x0007 8800 0x0007 8BFF 128 x 16 0x0107 1080 0x0107 10FF
OTP Bank 1
User
F28P55xSJx configurable 1K x 16 0x0007 9800 0x0007 9BFF 128 x 16 0x0107 1180 0x0107 11FF
OTP Bank 3
User
configurable 1K x 16 0x0007 A000 0x0007 A3FF 128 x 16 0x0107 1200 0x0107 127F
OTP Bank 4
Bank 0 Sectors
Sector 0 1K x 16 0x0008 0000 0x0008 03FF 128 x 16 0x0108 0000 0x0108 007F
Sector 1 1K x 16 0x0008 0400 0x0008 07FF 128 x 16 0x0108 0080 0x0108 00FF
Sector 2 1K x 16 0x000800800 0x0008 0BFF 128 x 16 0x0108 0100 0x0108 017F
All ... ... ... ... ... ... ...
Sector 29 1K x 16 0x0008 7400 0x0008 77FF 128 x 16 0x0108 0E80 0x0108 0EFF
Sector 30 1K x 16 0x0008 7800 0x0008 7BFF 128 x 16 0x0108 0F00 0x0108 0F7F
Sector 31 1K x 16 0x0008 7C00 0x0008 7FFF 128 x 16 0x0108 0F80 0x0108 0FFF

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Table 7-3. Flash Memory Map (continued)

PART ADDRESS ECC ADDRESS
SECTOR
NUMBER SIZE START END SIZE START END
Sector 32 1K x 16 0x0008 8000 0x0008 83FF 512 x 16 0x0108 1000 0x0108 107F
Sector 33 1K x 16 0x0008 8400 0x0008 87FF 512 x 16 0x0108 1080 0x0108 10FF
Sector 34 1K x 16 0x0008 8800 0x0008 8BFF 512 x 16 0x0108 1100 0x0108 117F
F28P55xSJx,
F28P55xSGx, ... ... ... ... ... ... ...
F28P55xSDx
Sector 61 1K x 16 0x0008 F400 0x0008 F7FF 512 x 16 0x0108 1E80 0x0108 1EFF
Sector 62 1K x 16 0x0008 F800 0x0008 FBFF 512 x 16 0x0108 1F00 0x0108 1F7F
Sector 63 1K x 16 0x0008 FC00 0x0008 FFFF 512 x 16 0x0108 1F80 0x0108 1FFF
Sector 64 1K x 16 0x0009 0000 0x0009 03FF 512 x 16 0x0108 2000 0x0108 207F
Sector 65 1K x 16 0x0009 0400 0x0009 07FF 512 x 16 0x0108 2080 0x0108 20FF
ADVANCE INFORMATION

Sector 66 1K x 16 0x0009 0800 0x0009 0BFF 512 x 16 0x0108 2100 0x0108 217F
F28P55xSJx,
... ... ... ... ... ... ...
F28P55xSGx
Sector 93 1K x 16 0x0009 7400 0x0009 77FF 512 x 16 0x0108 2E80 0x0108 2EFF
Sector 94 1K x 16 0x0009 7800 0x0009 7BFF 512 x 16 0x0108 2F00 0x0108 2F7F
Sector 95 1K x 16 0x0009 7C00 0x0009 7FFF 512 x 16 0x0108 2F80 0x0108 2FFF
Sector 96 1K x 16 0x0009 8000 0x0009 83FF 512 x 16 0x0108 3000 0x0108 307F
Sector 97 1K x 16 0x0009 8400 0x0009 87FF 512 x 16 0x0108 3080 0x0108 30FF
Sector 98 1K x 16 0x0009 8800 0x0009 8BFF 512 x 16 0x0108 3100 0x0108 317F
F28P55xSJx ... ... ... ... ... ... ...
Sector 125 1K x 16 0x0009 F400 0x0009 F7FF 512 x 16 0x0108 3E80 0x0108 3EFF
Sector 126 1K x 16 0x0009 F800 0x0009 FBFF 512 x 16 0x0108 3F00 0x0108 3F7F
Sector 127 1K x 16 0x0009 FC00 0x0009 FFFF 512 x 16 0x0108 3F80 0x0108 3FFF
Bank 1 Sectors
Sector 0 1K x 16 0x000A 0000 0x000A 03FF 128 x 16 0x0108 4000 0x0108 407F
Sector 1 1K x 16 0x000A 0400 0x000A 07FF 128 x 16 0x0108 4080 0x0108 40FF
Sector 2 1K x 16 0x000A 0800 0x000A 0BFF 128 x 16 0x0108 4100 0x0108 417F
F28P55xSJx
... ... ... ... ... ... ...
only
Sector 125 1K x 16 0x000B F400 0x000B F7FF 128 x 16 0x0108 7E80 0x0108 7EFF
Sector 126 1K x 16 0x000B F800 0x000B FBFF 128 x 16 0x0108 7F00 0x0108 7F7F
Sector 127 1K x 16 0x000B FC00 0x000B FFFF 128 x 16 0x0108 7F80 0x0108 7FFF
Bank 2 Sectors
Sector 0 1K x 16 0x000C 0000 0x000C 03FF 128 x 16 0x0108 0000 0x0108 007F
Sector 1 1K x 16 0x000C 0400 0x000C 07FF 128 x 16 0x0108 0080 0x0108 00FF
Sector 2 1K x 16 0x000C 0800 0x000C 0BFF 128 x 16 0x0108 0100 0x0108 017F
All ... ... ... ... ... ... ...
Sector 29 1K x 16 0x000C 7400 0x000C 77FF 128 x 16 0x0108 0E80 0x0108 0EFF
Sector 30 1K x 16 0x000C 7800 0x000C 7BFF 128 x 16 0x0108 0F00 0x0108 0F7F
Sector 31 1K x 16 0x000C 7C00 0x000C 7FFF 128 x 16 0x0108 0F80 0x0108 0FFF
Sector 32 1K x 16 0x000C 8000 0x000C 83FF 512 x 16 0x0108 1000 0x0108 107F
Sector 33 1K x 16 0x000C 8400 0x000C 87FF 512 x 16 0x0108 1080 0x0108 10FF
Sector 34 1K x 16 0x000C 8800 0x000C 8BFF 512 x 16 0x0108 1100 0x0108 117F
F28P55xSJx,
F28P55xSGx, ... ... ... ... ... ... ...
F28P55xSDx
Sector 61 1K x 16 0x000C F400 0x000C F7FF 512 x 16 0x0108 1E80 0x0108 1EFF
Sector 62 1K x 16 0x000C F800 0x000C FBFF 512 x 16 0x0108 1F00 0x0108 1F7F
Sector 63 1K x 16 0x000C FC00 0x000C FFFF 512 x 16 0x0108 1F80 0x0108 1FFF

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Table 7-3. Flash Memory Map (continued)

PART ADDRESS ECC ADDRESS
SECTOR
NUMBER SIZE START END SIZE START END
Sector 64 1K x 16 0x000D 0000 0x000D 03FF 512 x 16 0x0108 2000 0x0108 207F
Sector 65 1K x 16 0x000D 0400 0x000D 07FF 512 x 16 0x0108 2080 0x0108 20FF
Sector 66 1K x 16 0x000D 0800 0x000D 0BFF 512 x 16 0x0108 2100 0x0108 217F
F28P55xSJx,
... ... ... ... ... ... ...
F28P55xSGx
Sector 93 1K x 16 0x000D 7400 0x000D77FF 512 x 16 0x0108 2E80 0x0108 2EFF
Sector 94 1K x 16 0x000D 7800 0x000D 7BFF 512 x 16 0x0108 2F00 0x0108 2F7F
Sector 95 1K x 16 0x000D 7C00 0x000D 7FFF 512 x 16 0x0108 2F80 0x0108 2FFF
Sector 96 1K x 16 0x000D 8000 0x000D 83FF 512 x 16 0x0108 3000 0x0108 307F
Sector 97 1K x 16 0x000D 8400 0x000D 87FF 512 x 16 0x0108 3080 0x0108 30FF

ADVANCE INFORMATION
Sector 98 1K x 16 0x000D 8800 0x000D 8BFF 512 x 16 0x0108 3100 0x0108 317F
F28P55xSJx ... ... ... ... ... ... ...
Sector 125 1K x 16 0x000D F400 0x000D F7FF 512 x 16 0x0108 3E80 0x0108 3EFF
Sector 126 1K x 16 0x000D F800 0x000D FBFF 512 x 16 0x0108 3F00 0x0108 3F7F
Sector 127 1K x 16 0x000D FC00 0x000D FFFF 512 x 16 0x0108 3F80 0x0108 3FFF
Bank 3 Sectors
Sector 0 1K x 16 0x000E 0000 0x000E 03FF 128 x 16 0x0108 C000 0x0108 C07F
Sector 1 1K x 16 0x000E 0400 0x000E 07FF 128 x 16 0x0108 C080 0x0108 C0FF
Sector 2 1K x 16 0x000E 0800 0x000E 0BFF 128 x 16 0x0108 C100 0x0108 C17F
F28P55xSJx
... ... ... ... ... ... ...
only
Sector 125 1K x 16 0x000F F400 0x000F F7FF 128 x 16 0x0108 FE80 0x0108 FEFF
Sector 126 1K x 16 0x000F F800 0x000F FBFF 128 x 16 0x0108 FF00 0x0108 FF7F
Sector 127 1K x 16 0x000F FC00 0x000F FFFF 128 x 16 0x0108F F80 0x0108 FFFF
Bank 4 Sectors
Sector 0 1K x 16 0x0010 0000 0x0010 03FF 128 x 16 0x0109 0000 0x0109 007F
Sector 1 1K x 16 0x0010 0400 0x0010 07FF 128 x 16 0x0109 0080 0x0190 00FF
Sector 2 1K x 16 0x0010 0800 0x0010 0BFF 128 x 16 0x0109 0100 0x0109 0180
F28P55xSJx
... ... ... ... ... ... ...
only
Sector 29 1K x 16 0x0010 7400 0x0010 77FF 128 x 16 0x0109 0E80 0x0109 0EFF
Sector 30 1K x 16 0x0010 7800 0x0010 7BFF 128 x 16 0x0109 0F00 0x0109 0F7F
Sector 31 1K x 16 0x0010 7C00 0x0010 7FFF 128 x 16 0x0109 0F80 0x0109 0FFF

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7.3.4 Peripheral Registers Memory Map

Table 7-4. Peripheral Registers Memory Map
Structure DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1 Pipeline Protected
Peripheral Frame 0 (PF0)
CPUTIMER_REGS CPUTIMER0_BASE 0x0000_0C00 YES - - -
CLA_ONLY_REGS CLA1_ONLY_BASE 0x0000_0C00 - - YES -
CPUTIMER_REGS CPUTIMER1_BASE 0x0000_0C08 YES - - -
CPUTIMER_REGS CPUTIMER2_BASE 0x0000_0C10 YES - - -
PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES - - -
CLA_SOFTINT_REGS CLA1_SOFTINT_BASE 0x0000_0CE0 - - YES -
PIE_VECT_TABLE PIEVECTTABLE_BASE 0x0000_0D00 YES - - -
DMA_REGS DMA_BASE 0x0000_1000 YES - - -
DMA_CH_REGS DMA_CH1_BASE 0x0000_1020 YES - - -
ADVANCE INFORMATION

DMA_CH_REGS DMA_CH2_BASE 0x0000_1040 YES - - -

DMA_CH_REGS DMA_CH3_BASE 0x0000_1060 YES - - -
DMA_CH_REGS DMA_CH4_BASE 0x0000_1080 YES - - -
DMA_CH_REGS DMA_CH5_BASE 0x0000_10A0 YES - - -
DMA_CH_REGS DMA_CH6_BASE 0x0000_10C0 YES - - -
CLA_REGS CLA1_BASE 0x0000_1400 YES - - -
ADC_RESULT_REGS ADCARESULT_BASE 0x0000_1800 YES YES YES -
ADC_RESULT_REGS ADCBRESULT_BASE 0x0000_1880 YES YES YES -
ADC_RESULT_REGS ADCCRESULT_BASE 0x0000_1900 YES YES YES -
ADC_RESULT_REGS ADCDRESULT_BASE 0x0000_1980 YES YES YES -
ADC_RESULT_REGS ADCERESULT_BASE 0x0000_1A00 YES YES YES -
PCTRACE_BUFFER_REGS ERAD_PCTRACE_BUFFER_BASE 0x0005_FE00 YES - - YES
UID_REGS UID_BASE 0x0007_2172 YES - - -
DCSM_Z1_OTP DCSM_Z1OTP_BASE 0x0007_8000 YES - - -
DCSM_Z2_OTP DCSM_Z2OTP_BASE 0x0007_8200 YES - - -
Peripheral Frame 1 (PF1)
EPWM_REGS EPWM1_BASE 0x0000_4000 YES YES YES YES
EPWM_REGS EPWM2_BASE 0x0000_4100 YES YES YES YES
EPWM_REGS EPWM3_BASE 0x0000_4200 YES YES YES YES
EPWM_REGS EPWM4_BASE 0x0000_4300 YES YES YES YES
EPWM_REGS EPWM5_BASE 0x0000_4400 YES YES YES YES
EPWM_REGS EPWM6_BASE 0x0000_4500 YES YES YES YES
EPWM_REGS EPWM7_BASE 0x0000_4600 YES YES YES YES
EPWM_REGS EPWM8_BASE 0x0000_4700 YES YES YES YES

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Table 7-4. Peripheral Registers Memory Map (continued)

Structure DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1 Pipeline Protected
EPWM_REGS EPWM9_BASE 0x0000_4800 YES YES YES YES
EPWM_REGS EPWM10_BASE 0x0000_4900 YES YES YES YES
EPWM_REGS EPWM11_BASE 0x0000_4A00 YES YES YES YES
EPWM_REGS EPWM12_BASE 0x0000_4B00 YES YES YES YES
EQEP_REGS EQEP1_BASE 0x0000_5100 YES YES YES YES
EQEP_REGS EQEP2_BASE 0x0000_5140 YES YES YES YES
EQEP_REGS EQEP3_BASE 0x0000_5180 YES YES YES YES
ECAP_REGS ECAP1_BASE 0x0000_5200 YES YES YES YES
ECAP_REGS ECAP2_BASE 0x0000_5240 YES YES YES YES
CMPSS_REGS CMPSS1_BASE 0x0000_5500 YES YES YES YES
CMPSS_REGS CMPSS2_BASE 0x0000_5540 YES YES YES YES

ADVANCE INFORMATION
CMPSS_REGS CMPSS3_BASE 0x0000_5580 YES YES YES YES
CMPSS_REGS CMPSS4_BASE 0x0000_55C0 YES YES YES YES
PGA_REGS PGA1_BASE 0x0000_5B00 YES YES YES YES
PGA_REGS PGA2_BASE 0x0000_5B10 YES YES YES YES
PGA_REGS PGA3_BASE 0x0000_5B20 YES YES YES YES
DAC_REGS DACA_BASE 0x0000_5C00 YES YES YES YES
Peripheral Frame 2 (PF2)
SPI_REGS SPIA_BASE 0x0000_6100 YES YES YES YES
SPI_REGS SPIB_BASE 0x0000_6110 YES YES YES YES
PMBUS_REGS PMBUSA_BASE 0x0000_6400 YES YES YES YES
FSI_TX_REGS FSITXA_BASE 0x0000_6600 YES YES YES YES
FSI_RX_REGS FSIRXA_BASE 0x0000_6680 YES YES YES YES
Peripheral Frame 3 (PF3)
ADC_REGS ADCC_BASE 0x0000_6A00 YES - YES YES
ADC_REGS ADCD_BASE 0x0000_6C00 YES - YES YES
ADC_REGS ADCE_BASE 0x0000_6E00 YES - YES YES
ADC_REGS ADCA_BASE 0x0000_7400 YES - YES YES
ADC_REGS ADCB_BASE 0x0000_7600 YES - YES YES
Peripheral Frame 4 (PF4)
INPUT_XBAR_REGS INPUTXBAR_BASE 0x0000_7900 YES - - YES
XBAR_REGS XBAR_BASE 0x0000_7920 YES - - YES
SYNC_SOC_REGS SYNCSOC_BASE 0x0000_7940 YES - - YES
INPUT_XBAR_REGS CLBINPUTXBAR_BASE 0x0000_7960 YES - - YES
DMA_CLA_SRC_SEL_REGS DMACLASRCSEL_BASE 0x0000_7980 YES - - YES

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Table 7-4. Peripheral Registers Memory Map (continued)

Structure DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1 Pipeline Protected
EPWM_XBAR_REGS EPWMXBAR_BASE 0x0000_7A00 YES - - YES
CLB_XBAR_REGS CLBXBAR_BASE 0x0000_7A40 YES - - YES
OUTPUT_XBAR_REGS OUTPUTXBAR_BASE 0x0000_7A80 YES - - YES
OUTPUT_XBAR_REGS CLBOUTPUTXBAR_BASE 0x0000_7BC0 YES - - YES
GPIO_CTRL_REGS GPIOCTRL_BASE 0x0000_7C00 YES - - YES
GPIO_DATA_REGS GPIODATA_BASE 0x0000_7F00 YES - YES YES
GPIO_DATA_READ_REGS GPIODATAREAD_BASE 0x0000_7F80 YES - YES YES
DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - YES
CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES - - YES
CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES - - YES
SYS_STATUS_REGS SYSSTAT_BASE 0x0005_D400 YES - - YES
PERIPH_AC_REGS PERIPHAC_BASE 0x0005_D500 YES - - YES
ADVANCE INFORMATION

ANALOG_SUBSYS_REGS ANALOGSUBSYS_BASE 0x0005_D700 YES - - YES

Peripheral Frame 6 (PF6)
ERAD_GLOBAL_REGS ERAD_GLOBAL_BASE 0x0005_E800 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP1_BASE 0x0005_E900 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP2_BASE 0x0005_E908 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP3_BASE 0x0005_E910 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP4_BASE 0x0005_E918 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP5_BASE 0x0005_E920 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP6_BASE 0x0005_E928 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP7_BASE 0x0005_E930 YES - - YES
ERAD_HWBP_REGS ERAD_HWBP8_BASE 0x0005_E938 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER1_BASE 0x0005_E980 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER2_BASE 0x0005_E990 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER3_BASE 0x0005_E9A0 YES - - YES
ERAD_COUNTER_REGS ERAD_COUNTER4_BASE 0x0005_E9B0 YES - - YES
ERAD_CRC_GLOBAL_REGS ERAD_CRC_GLOBAL_BASE 0x0005_EA00 YES - - YES
ERAD_CRC_REGS ERAD_CRC1_BASE 0x0005_EA10 YES - - YES
ERAD_CRC_REGS ERAD_CRC2_BASE 0x0005_EA20 YES - - YES
ERAD_CRC_REGS ERAD_CRC3_BASE 0x0005_EA30 YES - - YES
ERAD_CRC_REGS ERAD_CRC4_BASE 0x0005_EA40 YES - - YES
ERAD_CRC_REGS ERAD_CRC5_BASE 0x0005_EA50 YES - - YES
ERAD_CRC_REGS ERAD_CRC6_BASE 0x0005_EA60 YES - - YES
ERAD_CRC_REGS ERAD_CRC7_BASE 0x0005_EA70 YES - - YES

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Table 7-4. Peripheral Registers Memory Map (continued)

Structure DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1 Pipeline Protected
ERAD_CRC_REGS ERAD_CRC8_BASE 0x0005_EA80 YES - - YES
PCTRACE_REGS ERAD_PCTRACE_BASE 0x0005_EAD0 YES - - YES
EPG_REGS EPG1_BASE 0x0005_EC00 YES - - YES
EPG_MUX_REGS EPG1MUX_BASE 0x0005_ECD0 YES - - YES
DCSM_Z1_REGS DCSM_Z1_BASE 0x0005_F000 YES - - YES
DCSM_Z2_REGS DCSM_Z2_BASE 0x0005_F080 YES - - YES
DCSM_COMMON_REGS DCSMCOMMON_BASE 0x0005_F0C0 YES - - YES
MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES - - YES
ACCESS_PROTECTION_REGS ACCESSPROTECTION_BASE 0x0005_F500 YES - - YES
MEMORY_ERROR_REGS MEMORYERROR_BASE 0x0005_F540 YES - - YES
TEST_ERROR_REGS TESTERROR_BASE 0x0005_F590 YES - - YES

ADVANCE INFORMATION
FLASH_CTRL_REGS FLASH0CTRL_BASE 0x0005_F800 YES - - YES
FLASH_ECC_REGS FLASH0ECC_BASE 0x0005_FB00 YES - - YES
Peripheral Frame 7 (PF7)
NNPU_EXT_EVT_REGS NNPU_EXTEVT_BASE 0x0005_4000 YES - - YES
NNPU_EXT_GPRCM_REGS NNPU_EXTGPRCM_BASE 0x0005_400A YES - - YES
NNPU_IPSTANDARD_REGS NNPU_IPSTANDARD_BASE 0x0005_4020 YES - - YES
NNPU_IPSPECIFIC_REGS NNPU_IPSPECIFIC_BASE 0x0005_4100 YES - - YES
NNPU_DATA_REGS NNPU_DATA_BASE 0x0005_4700 YES - - YES
NNPU_ACC_REGS NNPU_ACC_BASE 0x0005_4C00 YES - - YES
NNPU_INSTRUCTION_REGS NNPU_INSTRUCTION_BASE 0x0005_5000 YES - - YES
NNPU_RFDATA_REGS NNPU_RFDATA_BASE 0x0005_5800 YES - - YES
MCANSS_REGS MCANASS_BASE 0x0005_9400 YES - - YES
MCAN_REGS MCANA_BASE 0x0005_9600 YES - - YES
MCAN_ERROR_REGS MCANA_ERROR_BASE 0x0005_9800 YES - - YES
MCANSS_REGS MCANBSS_BASE 0x0005_B400 YES - - YES
MCAN_REGS MCANB_BASE 0x0005_B600 YES - - YES
MCAN_ERROR_REGS MCANB_ERROR_BASE 0x0005_B800 YES - - YES
DCC_REGS DCC0_BASE 0x0005_E700 YES - - YES
DCC_REGS DCC1_BASE 0x0005_E740 YES - - YES
Peripheral Frame 8 (PF8)
LIN_REGS LINA_BASE 0x0000_6800 YES YES YES YES
Peripheral Frame 9 (PF9)
WD_REGS WD_BASE 0x0000_7000 YES - - YES
NMI_INTRUPT_REGS NMI_BASE 0x0000_7060 YES - - YES

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Table 7-4. Peripheral Registers Memory Map (continued)

Structure DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1 Pipeline Protected
XINT_REGS XINT_BASE 0x0000_7070 YES - - YES
SCI_REGS SCIA_BASE 0x0000_7200 YES - - YES
SCI_REGS SCIB_BASE 0x0000_7210 YES - - YES
SCI_REGS SCIC_BASE 0x0000_7220 YES - - YES
I2C_REGS I2CA_BASE 0x0000_7300 YES - - YES
I2C_REGS I2CB_BASE 0x0000_7340 YES - - YES
Peripheral Frame 10 (PF10)
CLB_LOGIC_CONFIG_REGS CLB1_LOGICCFG_BASE 0x0000_3000 YES - YES YES
CLB_LOGIC_CONTROL_REGS CLB1_LOGICCTRL_BASE 0x0000_3100 YES - YES YES
CLB_DATA_EXCHANGE_REGS CLB1_DATAEXCH_BASE 0x0000_3180 YES - YES YES
CLB_LOGIC_CONFIG_REGS CLB2_LOGICCFG_BASE 0x0000_3400 YES - YES YES
CLB_LOGIC_CONTROL_REGS CLB2_LOGICCTRL_BASE 0x0000_3500 YES - YES YES
ADVANCE INFORMATION

CLB_DATA_EXCHANGE_REGS CLB2_DATAEXCH_BASE 0x0000_3580 YES - YES YES

Peripheral Frame 11 (PF11)
USB_REGS USBA_BASE 0x0004_0000 YES YES - YES
AES_REGS AESA_BASE 0x0004_2000 YES YES - YES
AES_SS_REGS AESA_SS_BASE 0x0004_2C00 YES YES - YES
Peripheral Frame 12 (PF12)
LFU_REGS LFU_BASE 0x0000_7FE0 YES - YES YES

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7.4 Identification
Table 7-5 lists the Device Identification Registers. Additional information on these device identification registers
can be found in the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual. See the register
descriptions of PARTIDH and PARTIDL for identification of production status (TMX or TMS) and other device
information.
Table 7-5. Device Identification Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
Bits Options
14-13 1 = InstaSPIN-FOC
INSTASPIN 2 = NONE
3 = NONE
10-8 0 = 56 pin (QFN)

ADVANCE INFORMATION
PIN_COUNT 1 = 64 pin (QFP)
PARTIDL 0x0005 D008 2
2 = 80 pin (QFP)
3 = 100 pin (QFP)
4 = 128 pin (QFP)
7-6 0 = Engineering Sample (TMX)
QUAL 1 = Pilot Production (TMP)
2 = Fully Qualified (TMS)
Device part identification number
TMS320F28P55xSJ9 0x09FF 0500
TMS320F28P55xSJ6 0x09FC 0500
TMS320F28P55xSJ2 0x09F8 0500
PARTIDH 0x0005 D00A 2
TMS320F28P55xSG9 0x09F5 0500
TMS320F28P55xSG8 0x09F4 0500
TMS320F28P55xSG2 0x09EE 0500
TMS320F28P55xSD7 0x09E9 0500
Silicon revision number
REVID 0x0005 D00C 2
Revision 0 0x0000 0001
Unique identification number. This number is different on each
individual device with the same PARTIDH. This unique number
UID_UNIQUE 0x0007 2172 4
can be used as a serial number in the application. This number
is present only on TMS devices.

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7.5 Bus Architecture – Peripheral Connectivity

The Peripheral Connectivity table lists a broad view of the peripheral and configuration register accessibility from
each bus controller.
Table 7-6. Peripheral Connectivity
PERIPHERAL DMA CLA C28
SYSTEM PERIPHERALS
CPU Timers Y
ERAD Y
GPIO Data Y Y
GPIO Pin Mapping and Configuration Y
XBAR Configuration Y
System Configuration Y
ADVANCE INFORMATION

AES Y Y
EPG Y
LFU Y Y
DCC Y
MEMORY
M0/M1 Y
LSx Y Y
GSx Y Y
ROM Y
FLASH Y
CONTROL PERIPHERALS
ePWM/HRPWM Y Y Y
eCAP Y Y Y
(1)
eQEP Y Y Y
CLB Y Y
ANALOG PERIPHERALS
(1)
CMPSS Y Y Y
(1)
DAC Y Y Y
ADC Configuration Y Y
(1)
ADC Results Y Y Y
(1)
PGA Y Y Y
COMMUNICATION PERIPHERALS
(1)
MCAN(CAN-FD) Y Y
FSITX/FSIRX Y Y Y
I2C Y
LIN Y Y Y
PMBus Y Y Y
SCI Y
SPI Y Y Y
(1)
USB Y Y

(1) These modules are accessible from DMA but cannot trigger a DMA transfer.

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7.6 C28x Processor

The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
7.6.1 Floating-Point Unit (FPU)

ADVANCE INFORMATION
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-priority
interrupts for fast context save and restore of the floating-point registers.
For more information on the C28x Floating Point Unit (FPU), see the TMS320C28x Extended Instruction Sets
Technical Reference Manual.
7.6.2 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and
leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 7-7.
Table 7-7. TMU Supported Instructions
Instructions C Equivalent Operation Pipeline Cycles
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation
of floating-point power function for the nonlinear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a
typical of 300 cycles using library emulation to less than 10 cycles.
No changes have been made to existing instructions, pipeline, or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out the operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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7.6.3 VCRC Unit

Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial 1 = 0x8005
• CRC16 polynomial 2 = 0x1021
• CRC24 polynomial = 0x5d6dcb
• CRC32 polynomial 1 = 0x04c11db7
• CRC32 polynomial 2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
ADVANCE INFORMATION

CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to three cycles when using a custom polynomial.
For more information on the Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended
Instruction Sets Technical Reference Manual.

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7.7 Control Law Accelerator (CLA)

The CLA Type-2 is an independent, fully programmable, 32-bit floating-point math processor that brings
concurrent control-loop execution to the C28x family. The low interrupt-latency of the CLA allows it to read
ADC samples "just-in-time." This significantly reduces the ADC sample to output delay to enable faster system
response and higher MHz control loops. By using the CLA to service time-critical control loops, the main CPU is
free to perform other system tasks such as communications and diagnostics.
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical
control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster
system response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main
CPU to perform other system and communication functions concurrently.
The following is a list of major features of the CLA:
• C compilers are available for CLA software development

ADVANCE INFORMATION
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent 8-stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0 to MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and a
main background task.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high-priority
events trigger a foreground task.
• Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership.
– Task8 can be set to be the background task, while Tasks 1 to 7 take peripheral triggers.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– Two dedicated message RAMs for communication between the CLA and the DMA

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CLA Control
Register Set

MIFR(16)
MPERINT1 MIOVF(16) CLA_INT1
From Shared to to
Peripherals MPERINT8 MICLR(16) CLA_INT8
MICLROVF(16) C28x
PIE INT11
MIFRC(16) CPU
MIER(16) INT12
MIRUN(16)
LVF
MCTLBGRND(16)
LUF
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable MVECT1(16)
CPU Read/Write Data Bus
SYSRS MVECT2(16)
ADVANCE INFORMATION

MVECT3(16)
MVECT4(16) CLA Program
MVECT5(16) CLA Program Bus Memory (LSx)
MVECT6(16)
MVECT7(16)
MVECT8(16) LSxMSEL[MSEL_LSx]
MVECTBGRND(16) LSxCLAPGM[CLAPGM_LSx]
MVECTBGRNDACTIVE(16)
MPSACTL(16)

CPU Data Bus

MPSA1(32) CLA Data
MPSA2(32) Memory (LSx)

MCTL(16)

CLA Data Bus

CLA Message
CLA Execution
RAMs
Register Set

MPC(16)
MSTF(32)
MR0(32)
MR1(32) Shared
MR2(32) MEALLOW Peripherals
MR3(32)
MAR0(16)
MAR1(16)
CPU Read Data Bus

Figure 7-2. CLA Block Diagram

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7.8 Embedded Real-Time Analysis and Diagnostic (ERAD)

The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and system-
analysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consists
of the Enhanced Bus Comparator units and the System Event Counter units. The Enhanced Bus Comparator
units are used to generate hardware breakpoints, hardware watch points, and other output events. The System
Event Counter units are used to analyze and profile the system. The ERAD module is accessible by the
debugger and by the application software, which significantly increases the debug capabilities of many real-time
systems, especially in situations where debuggers are not connected. In the TMS320F28P55x devices, the
ERAD module contains eight Enhanced Bus Comparator units (which increases the number of Hardware
breakpoints from two to ten) and four Benchmark System Event Counter units.

ADVANCE INFORMATION

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7.9 Direct Memory Access (DMA)

The DMA module provides a hardware method of transferring data between peripherals and/or memory without
intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has
the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing. Figure 7-3 shows a
device-level block diagram of the DMA.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– External Interrupts
– ePWM SOC signals
– CPU timers
ADVANCE INFORMATION

– eCAP
– SPI transmit and receive
– LIN transmit and receive
• Data sources and destinations:
– GSx RAM
– ADC result registers
– Control peripheral registers (ePWM, eQEP, eCAP)
– SPI, LIN, CAN, and PMBus registers
– USB
– PGA control registers
• Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
• Throughput: Four cycles per word without arbitration

ADC ADC Global Shared (GS0-

CAN LIN USB AES XINT TIMER
WRAPPER RESULTS 3) RAM

DMA bus C28x bus

TINT (0-2)

XINT(1-5)

ADCx.INT(1-5), ADCx.EVT
AESA_ContextIn, AESA_ContextOut, AESA_DataIn, AESA_DataOut
DMA_CHx(1-6)
LINxTXDMA, LINxRXDMA
C28x

DMA Trigger
Source Selection

ECAP(1-2)DMA PIE
DMACHSRCSEL1.CHx DMA
DMACHSRCSEL2.CHx
EPWM(1-12).SOCA, EPWM(1-12).SOCB CHx.MODE.PERINTSEL
(x = 1 to 6)
CLB1-2INT
EPGAINT
SPITXDMA(A-B)
SPIRXDMA(A-B)

FSITXADMA, FSIRXADMA
FSI_DATA_TAG_MATCH,
FSI_PING_TAG_MATCH

PM
PGA DAC CMPSS eQEP eCAP EPWM EPG CLB SPI FSI
Bus

Figure 7-3. DMA Block Diagram

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7.10 Device Boot Modes

This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general-purpose input/output (GPIO) pins to determine the boot
mode configuration.
Table 7-8 shows the boot mode options available for selection by the default boot mode select pins. Users have
the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot
mode select pin GPIOs used.
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA, SPIA,
I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as SCI boot, it is
actually referring to the first module instance, which means the SCI boot on the SCIA port. The same applies to
the other peripheral boots.
See the Reset - XRSn - Switching Characteristics table and the Power-on Reset figure for tboot-flash, the boot

ADVANCE INFORMATION
ROM execution time to first instruction fetch in flash.
Table 7-8. Device Default Boot Modes
GPIO24 GPIO32
BOOT MODE
(DEFAULT BOOT MODE SELECT PIN 1) (DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO 0 0
(1)
SCI / Wait Boot 0 1
CAN(MCAN-NONFD) 1 0
(2)
Flash(USB) 1 1

(1) SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.
(2) If the default flash entry address is not programmed, the boot mode will switch to USB Boot for those devices that include the USB
peripheral. On devices without a USB, the action will be to enter the ITRAP ISR if the default flash entry address is not programmed.
The switch to USB boot is only supported for the default flash entry address option and not all entry address options.

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7.10.1 Device Boot Configurations

This section details what boot configurations are available and how to configure them. This device supports
from 0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot mode up to 8
configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to select
between 3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
ADVANCE INFORMATION

and BMSP2 left as default which is disabled). Refer to Section 7.10.1.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to
the decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 7.10.1.2 for all
the details on setting up and configuring the custom boot mode table.
Additionally, the Boot Mode Example Use Cases section of the TMS320F28P55x Real-Time Microcontrollers
Technical Reference Manual provides some example use cases on how to configure the BMSPs and custom
boot tables.

Note
The CAN boot mode turns on the XTAL. Be sure an XTAL is installed in the application before using
CAN boot mode.

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7.10.1.1 Configuring Boot Mode Pins

This section explains how the boot mode select pins can be customized by the user, by programming
the BOOTPIN-CONFIG location (refer to Table 7-9) in the user-configurable dual-zone security module
(DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG.
When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTP-
BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.

Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will take
priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTP-
BOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTP-
BOOTPIN-CONFIG.

ADVANCE INFORMATION
Table 7-9. BOOTPIN-CONFIG Bit Fields
BIT NAME DESCRIPTION
31:24 Key Write 0x5A to these 8-bits to indicate the bits in this register are valid
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description except for BMSP2
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description except for BMSP1
Set to the GPIO pin to be used during boot (up to 255):
- 0x0 = GPIO0
- 0x01 = GPIO1
7:0 Boot Mode Select Pin 0 (BMSP0)
- and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to select
the boot mode.

The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM automatically
selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the BMSP).
• GPIO 20 and GPIO 21
• GPIO 36 and GPIO 38
• GPIO 62 to GPIO 223

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Table 7-10. Standalone Boot Mode Select Pin Decoding

BOOTPIN_CONFIG
BMSP0 BMSP1 BMSP2 REALIZED BOOT MODE
KEY
!= 0x5A Don’t Care Don’t Care Don’t Care Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode
0xFF 0xFF 0xFF 0
(All BMSPs disabled)
Boot as defined by the value of BMSP0
Valid GPIO 0xFF 0xFF
(BMSP1 and BMSP2 disabled)
Boot as defined by the value of BMSP1
0xFF Valid GPIO 0xFF
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
0xFF 0xFF Valid GPIO
(BMSP0 and BMSP1 disabled)
Boot as defined by the values of BMSP0 and
Valid GPIO Valid GPIO 0xFF BMSP1
ADVANCE INFORMATION

(BMSP2 disabled)
Boot as defined by the values of BMSP0 and
Valid GPIO 0xFF Valid GPIO BMSP2
(BMSP1 disabled)
= 0x5A Boot as defined by the values of BMSP1 and
0xFF Valid GPIO Valid GPIO BMSP2
(BMSP0 disabled)
Boot as defined by the values of BMSP0,
Valid GPIO Valid GPIO Valid GPIO
BMSP1, and BMSP2
BMSP0 is reset to the factory default BMSP0
GPIO
Invalid GPIO Valid GPIO Valid GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
BMSP1 is reset to the factory default BMSP1
GPIO
Valid GPIO Invalid GPIO Valid GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
BMSP2 is reset to the factory default state,
which is disabled
Valid GPIO Valid GPIO Invalid GPIO
Boot as defined by the values of BMSP0 and
BMSP1

Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significant-
bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.

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7.10.1.2 Configuring Boot Mode Table Options

This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to the TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual
for examples on how to set up the BOOTPIN_CONFIG and BOOTDEF values.

Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead of Z1-

ADVANCE INFORMATION
OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG is
configured. Refer to Configuring Boot Mode Pins for more details on BOOTPIN_CONFIG usage.

Table 7-11. BOOTDEF Bit Fields

BYTE
BOOTDEF NAME NAME DESCRIPTION
POSITION
Set the boot mode for index 0 of the boot table.

Different boot modes and their options can include,

for example, a boot mode that uses different GPIOs
for a specific bootloader or a different flash entry
BOOT_DEF0 7:0 BOOT_DEF0 Mode/Options point address. Any unsupported boot mode will
cause the device to either go to wait boot or boot to
flash.

Refer to GPIO Assignments for valid BOOTDEF

values to set in the table.
BOOT_DEF1 15:8 BOOT_DEF1 Mode/Options
BOOT_DEF2 23:16 BOOT_DEF2 Mode/Options
BOOT_DEF3 31:24 BOOT_DEF3 Mode/Options
BOOT_DEF4 39:32 BOOT_DEF4 Mode/Options Refer to BOOT_DEF0 description
BOOT_DEF5 47:40 BOOT_DEF5 Mode/Options
BOOT_DEF6 55:48 BOOT_DEF6 Mode/Options
BOOT_DEF7 63:56 BOOT_DEF7 Mode/Options

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7.10.2 GPIO Assignments

This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTP-
BOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure BOOT_DEF. When
selecting a boot mode option, make sure to verify that the necessary pins are available in the pin mux options for
the specific device package being used.
Table 7-12. SCI Boot Options
OPTION BOOTDEF VALUE SCITXDA GPIO SCIRXDA GPIO
0 (default) 0x01 GPIO29 GPIO28
1 0x21 GPIO16 GPIO17
2 0x41 GPIO8 GPIO9
3 0x61 GPIO2 GPIO3
ADVANCE INFORMATION

4 0x81 GPIO16 GPIO3

Table 7-13. MCAN Boot Options

OPTION BOOTDEF VALUE CANTXA GPIO CANRXA GPIO
0 (default) 0x08 GPIO4 GPIO5
1 0x28 GPIO1 GPIO0
2 0x48 GPIO13 GPIO12

Table 7-14. CAN(MCAN in non-FD mode) Boot Options

OPTION BOOTDEF VALUE CANTXA GPIO CANRXA GPIO
0 (default) 0x02 GPIO4 GPIO5
1 0x22 GPIO1 GPIO0
2 0x42 GPIO13 GPIO12

Table 7-15. I2C Boot Options

OPTION BOOTDEF VALUE SDAA GPIO SCLA GPIO
0 0x07 GPIO0 GPIO1
1 0x27 GPIO32 GPIO33
2 0x47 GPIO5 GPIO4

Table 7-16. RAM Boot Options

RAM ENTRY POINT
OPTION BOOTDEF VALUE
(ADDRESS)
0 0x05 0x0000 0000

Table 7-17. Flash/Secure Flash Boot Options

FLASH ENTRY POINT
OPTION BOOTDEF VALUE FLASH SECTOR
(ADDRESS)
0 (default) 0x03 0x0008 0000 Bank0 Sector 0
1 0x23 0x0008 8000 Bank 0 Sector 32
2 0x43 0x000C 0000 Bank 2 Sector 0
3 0x63 0x000C 8000 Bank 2, Sector 32
4 0x83 0x0010 0000 Bank 4, Sector 0

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Table 7-18. LFU Flash Boot Options

FLASH ENTRY POINT
OPTION BOOTDEF VALUE BANK
(ADDRESS)
0 (default) 0x0B 0x0008 0000 Bank0
0x000C 0000 Bank2
1 0x2B 0x0008 8000 Bank0
0x000C 8000 Bank2

Table 7-19. Wait Boot Options

OPTION BOOTDEF VALUE WATCHDOG
0 0x04 Enabled
1 0x24 Disabled

Table 7-20. SPI Boot Options

ADVANCE INFORMATION
OPTION BOOTDEF VALUE SPIPICOA SPIPOCIA SPICLKA SPISPTE
0 0x06 GPIO2 GPIO1 GPIO3 GPIO5
1 0x26 GPIO16 GPIO1 GPIO3 GPIO0
2 0x46 GPIO8 GPIO10 GPIO9 GPIO11
3 0x66 GPIO8 GPIO17 GPIO9 GPIO11

Table 7-21. Parallel Boot Options

28x(DSP) CONTROL
OPTION BOOTDEF VALUE D0-D7 GPIO HOST CONTROL GPIO
GPIO
0 (default) 0x00 D0 - GPIO0 GPIO16 GPIO29
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
1 0x20 D0 - GPIO0 GPIO12 GPIO13
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7

Table 7-22. USB Boot Options

OPTION BOOTDEF VALUE USB0 DM USB0 DP
0 (default) 0x09 GPIO23 GPIO41

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7.11 Security
Security features are enforced by the Dual Code Security Module (DCSM). The primary layer of defense is
securing the boundary of the chip, which should always be enabled. Additionally, the Dual Zone Security feature
is available to support code partitioning.
7.11.1 Securing the Boundary of the Chip
The following two features, along with authentication in the firmware update code, should be used to help to
prevent unauthorized code from running on the device.
7.11.1.1 JTAGLOCK
Enabling the JTAGLOCK feature in the USER OTP disables JTAG access (for example, debug probe) to
resources on the device.
7.11.1.2 Zero-pin Boot
ADVANCE INFORMATION

Enabling the Zero-pin Boot option along with Flash Boot in the USER OTP blocks all pin-based external
bootloader options (for example, SCI, CAN, Parallel).
7.11.2 Dual-Zone Security
The dual-zone security mechanism offers protection for two zones: Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both zones is identical. Each zone has its own dedicated secure resource (OTP memory and
secure ROM) and allocated secure resource (LSx RAM and flash sectors).
7.11.3 Disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.

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7.12 Watchdog
The watchdog module is the same as the one on previous TMS320C2000™ microcontrollers, but with an
optional lower limit on the time between software resets of the counter. This windowed countdown is disabled by
default, so the watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 7-4 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV WDCR.WDPS WDCR.WDDIS

WDCNTR

WDCLK
(INTOSC1) Overflow 1-count

ADVANCE INFORMATION
delay
8-bit
WDCLK Watchdog Watchdog
Divider Prescaler Counter

SYSRSn
Clear
Count

WDWCR.MIN
WDKEY (7:0)
Out of Window Watchdog
Watchdog Good Key
Window
Key Detector Detector
WDCR(WDCHK(2:0))
55 + AA

Bad Key

WDRSTn Generate
1 0 1 512-WDCLK Watchdog Time-out
WDINTn Output Pulse

SCSR.WDENINT

Figure 7-4. Windowed Watchdog

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7.13 C28x Timers

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLK (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
ADVANCE INFORMATION

• X1 (XTAL)

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7.14 Dual-Clock Comparator (DCC)

The DCC module is used for evaluating and monitoring the clock input based on a second clock, which can
be a more accurate and reliable version. This instrumentation is used to detect faults in clock source or clock
structures, thereby enhancing the system's safety metrics.
7.14.1 Features
The DCC has the following features:
• Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
• Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
• Supports continuous monitoring without requiring application intervention.
• Supports a single-sequence mode for spot measurements.
• Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
7.14.2 Mapping of DCCx Clock Source Inputs

ADVANCE INFORMATION
Table 7-23. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0] CLOCK NAME
0x0 XTAL/X1
0x1 INTOSC1
0x2 INTOSC2
0x4 TCK
0x5 CPU1.SYSCLK
0x8 AUXCLKIN
0xC INPUT XBAR (Output16 of input-xbar)
others Reserved

Table 7-24. DCCx Clock Source1 Table

DCCxCLKSRC1[4:0] CLOCK NAME
0x0 PLLRAWCLK
0x2 INTOSC1
0x3 INTOSC2
0x6 CPU1.SYSCLK
0x9 Input XBAR (Output15 of the input-xbar)
0xA AUXCLKIN
0xB EPWMCLK
0xC LSPCLK
0xD ADCCLK
0xE WDCLK
0xF CAN0BITCLK
others Reserved

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7.15 Configurable Logic Block (CLB)

The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware for
C2000 MCUs package (C2000Ware_2_00_00_03 and higher):
ADVANCE INFORMATION

• C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
• CLB Tool User's Guide
• Designing With the C2000™ Configurable Logic Block (CLB) Application Report
• How to Migrate Custom Logic From an FPGA/CPLD to C2000™ Microcontrollers Application Report
The CLB module and its interconnections are shown in Figure 7-5.

GPIO0 Asynchronous
to Synchronous Input X-BAR
GPIOx Sync. + Qual

IN P U T 1 – IN P U T 6 CLBx T ILE
O t h er OU T 4 /5
S o u rc es

CLB X-BAR

O t her AU XSIG 0 – AU XSIG 7

So u rc es
CLB INPUT X-BAR CLB
CLB TILE1
GPREG CELL
CLB Global Signals IN0-7

Local OUT 0-7

Signals
.
. C L B T i l e O ut p ut s
. I nte rs ec t o t he r
I N P U T 1 – IN P U T 1 6 Pe r i ph eral s
CLB TILEx O U T P U T X-BAR

GPREG CELL
IN0-7

Local OUT 0-7

Signals

All C LB T i l e
Ou t p u t s

CLB OUTPUT X-BAR

GP IO M U X

Figure 7-5. GPIO to CLB Tile Connections

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Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality.

ADVANCE INFORMATION

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8 Applications, Implementation, and Layout

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

The Hardware Design Guide for F2800x C2000™ Real-Time MCU Series Application Note is an essential guide
for hardware developers using C2000 devices, and helps to streamline the design process while mitigating the
potential for faulty designs. Key topics discussed include: power requirements; general-purpose input/output
(GPIO) connections; analog inputs and ADC; clocking generation and requirements; and JTAG debugging
among many others.
ADVANCE INFORMATION

8.1 TI Reference Design

The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market.
Search and download TI reference designs at Select TI reference designs.

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MCU
devices and support tools. Each TMS320 ™ MCU commercial family member has one of three prefixes: TMX,
TMP, or TMS (for example, TMS320F28P559SJ-Q1). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX and TMDX) through fully qualified production devices
and tools (TMS and TMDS).
Device development evolutionary flow:

ADVANCE INFORMATION
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZ).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.

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Generic Part Number: TMS 320 F28 P 559 S J -Q1

Orderable Part Number: X F28 P 559 S J 9 PDT R Q1

PREFIX(A)
TMX (X) = experimental device AUTOMOTIVE AEC-Q100 QUALIFICATION
TMS (blank) = qualified device (blank) = Not AEC-Q100 qualified
Q1 = AEC-Q100 qualification

DEVICE FAMILY
320 = TMS320 MCU Family SHIPPING OPTIONS
(blank) = Tray
R = Tape and Reel
CPU ARCHITECTURE
F28 = C28 CPU
PACKAGE TYPE
PDT = 128-pin Thin Quad Flatpack (TQFP)
SERIES PZ = 100-pin Low-profile Quad Flatpack (LQFP)
PNA = 80-pin TQFP
P = Performance (150 MIPS to 600 MIPS)
ADVANCE INFORMATION

PM = 64-pin LQFP
RSH = 56-pin Very Thin Quad Flatpack No-Lead (VQFN)

MAJOR FAMILY (PLATFORM)

P = 30x to 69x SPECIAL FEATURES CODE
Industrial = Third digit is between 0 and 4
Automotive = Third digit is between 5 and 9 2 = Base + 8 PWM pairs
6 = Base + CLA + CLB + USB + 12 PWM pairs + 64KB Flash
7 = Base + CLA + CLB + 12 PWM pairs + 24KB RAM
8 = Base + CLA + CLB + 12 PWM pairs
CORE 9 = Base + CLA + CLB + USB + NNPU + 12 PWM pairs + 64KB Flash
S=1

MEMORY
J = 1MB Flash, 133KB RAM
G = 512KB Flash, 101KB RAM
D = 256KB Flash, 45KB RAM

A. Prefix X is used in orderable part numbers.

Figure 9-1. Device Nomenclature

9.2 Markings
Figure 9-2, Figure 9-3, Figure 9-4, Figure 9-5, Figure 9-6, Figure 9-7, Figure 9-8, and Figure 9-9 show the
package symbolization. Table 9-1 lists the silicon revision codes.

YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P559 S = Assembly Site Code
SJ9PDTQ $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = ECAT

Package
Pin 1
Figure 9-2. Package Symbolization for PDT Package – Automotive

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YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P559 S = Assembly Site Code
SJ9PZQ $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = ECAT

Package
Pin 1
Figure 9-3. Package Symbolization for PZ Package – Automotive

ADVANCE INFORMATION
YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P550 S = Assembly Site Code
SJ9PZ $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = ECAT

Package
Pin 1
Figure 9-4. Package Symbolization for PZ Package – Non-Automotive

YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P559 S = Assembly Site Code
SJ9PNAQ $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = ECAT

Package
Pin 1
Figure 9-5. Package Symbolization for PNA Package – Automotive

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YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P550 S = Assembly Site Code
SJ9PNA $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = ECAT

Package
Pin 1
Figure 9-6. Package Symbolization for PNA Package – Non-Automotive
ADVANCE INFORMATION

YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P559 S = Assembly Site Code
SJ9PMQ $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = ECAT

Package
Pin 1
Figure 9-7. Package Symbolization for PM Package – Automotive

YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

LLLL = Assembly Lot Code
XF28P550 S = Assembly Site Code
SJ9PM $$ = Wafer Fab Code (one or two characters) as applicable
$$#-YMLLLLS # = Silicon Revision Code
G4
G4 = ECAT

Package
Pin 1
Figure 9-8. Package Symbolization for PM Package – Non-Automotive

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YMLLLLS = Lot Trace Code

YM = 2-digit Year/Month Code

XF28P550 LLLL = Assembly Lot Code
S = Assembly Site Code
SJ9RSH $$ = Wafer Fab Code (one or two characters) as applicable
$$#YMLLLLS # = Silicon Revision Code
TI G4
G4 = ECAT

Package
Pin 1
Figure 9-9. Package Symbolization for RSH Package – Non-Automotive

Table 9-1. Revision Identification

ADVANCE INFORMATION
REVID(1)
SILICON REVISION CODE SILICON REVISION COMMENTS
ADDRESS: 0x5D00C
Blank 0 0x0000 0000 This silicon revision is available as TMX.

(1) Silicon Revision ID

9.3 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance
of the device, generate code, and develop solutions follow. To view all available tools and software for C2000™
real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
TI Resource Explorer
To enhance your experience, be sure to check out the TI Resource Explorer to browse examples, libraries, and
documentation for your applications.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000™ MCUs is a cohesive set of software and documentation created to minimize
development time. It includes device-specific drivers, libraries, and peripheral examples.
DigitalPower SDK
DigitalPower SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based digital power system development time targeted for various AC-DC, DC-DC and DC-AC
power supply applications. The software includes firmware that runs on C2000 digital power evaluation modules
(EVMs) and TI designs (TIDs), which are targeted for solar, telecom, server, electric vehicle chargers and
industrial power delivery applications. DigitalPower SDK provides all the needed resources at every stage of
development and evaluation in a digital power applications.
MotorControl SDK
MotorControl SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based motor control system development time targeted for various three-phase motor control
applications. The software includes firmware that runs on C2000 motor control evaluation modules (EVMs) and
TI designs (TIDs), which are targeted for industrial drive and other motor control, MotorControl SDK provides
all the needed resources at every stage of development and evaluation for high-performance motor control
applications.
Code Composer Studio™ integrated development environment (IDE)
Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and
processors. It comprises a suite of tools used to develop and debug embedded applications. Code Composer
Studio is available for download across Windows®, Linux® and macOS® desktops. It can also be used in

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the cloud by visiting https://dev.ti.com. Code Composer Studio includes an optimizing C/C++ compiler, source
code editor, project build environment, debugger, profiler and many other features. The intuitive IDE takes you
through each step of the application development flow. Familiar tools and interfaces make getting started faster
than ever before. The desktop version of Code Composer Studio combines the advantages of the Eclipse
software framework with advanced capabilities from TI resulting in a compelling feature-rich environment. The
cloud-based Code Composer Studio leverages the Theia application framework enabling development in the
cloud without needing to download and install large amounts of software.
SysConfig System configuration tool
SysConfig is a comprehensive collection of graphical utilities for configuring pins, peripherals, radios,
subsystems, and other components. SysConfig helps you manage, expose and resolve conflicts visually so
that you have more time to create differentiated applications. The tool's output includes C header and code files
that can be used with software development kit (SDK) examples or used to configure custom software. The
SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The SysConfig
ADVANCE INFORMATION

tool is delivered integrated in CCS, as a standalone installer, or can be used via the dev.ti.com cloud tools portal.
For more information about the SysConfig system configuration tool, visit the System configuration tool page.
C2000 Third-party search tool
TI has partnered with multiple companies to offer a wide range of solutions and services for TI C2000 devices.
These companies can accelerate your path to production using C2000 devices. Download this search tool to
quickly browse third-party details and find the right third-party to meet your needs.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
Models
Various models are available for download from the product Design & development pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL)
Models. To view all available models, visit the Design tools & simulation section of the Design & development
page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable
hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000
microcontroller family. These training resources have been designed to decrease the learning curve, while
reducing development time, and accelerating product time to market. For more information on the various
training resources, visit the C2000™ real-time control MCUs – Support & training site.
9.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
follows.

Note
TI is transitioning to use more inclusive terminology. Some language may be different than what you
would expect to see for certain technology areas.

Errata
TMS320F28P55x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.

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Technical Reference Manual

TMS320F28P55x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in
the F28P55x real-time microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides

ADVANCE INFORMATION
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v22.6.0.LTS User’s Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v22.6.0.LTS User’s Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
The Essential Guide for Developing With C2000™ Real-Time Microcontrollers provides a deeper look into the
components that differentiate the C2000 Microcontroller Unit (MCU) as it pertains to Real-Time Control Systems.
9.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

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9.6 Trademarks
C2000™, TMS320C2000™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
Windows® is a registered trademark of Microsoft Corporation.
Linux® is a registered trademark of Linus Torvalds.
macOS® is a registered trademark of Apple Inc.
All trademarks are the property of their respective owners.
9.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.8 Glossary
ADVANCE INFORMATION

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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www.ti.com SPRSP85 – APRIL 2024

10 Revision History
DATE REVISION NOTES
April 2024 * Initial Release
TI is transitioning to use more inclusive terminology. Some language
may be different than what you would expect to see for certain
technology areas.
For SPI, all instances of legacy terminology have been changed
to controller and peripheral. All instances of legacy pin names
have been changed to: POCI (Peripheral OUT Controller IN); PICO
(Peripheral IN Controller OUT); and CS (Chip Select).
For the I2C Bus Interface, all instances of legacy terminology have
been changed to controller and target.

ADVANCE INFORMATION
For the CAN and LIN Interface/BUS, all instances of legacy
terminology have been changed to commander and responder.
For the EtherCAT Controller, all instances of legacy terminology have
been changed to MainDevice (or MDevice) and SubordinateDevice
(or SubDevice).

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION

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 TMS320F28P550SJ, TMS320F28P559SJ-Q1
www.ti.com SPRSP85 – APRIL 2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS
K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

ADVANCE INFORMATION
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

All dimensions are nominal.

Reel Reel
Package Package Diameter Width W1 A0 B0 K0 P1 W Pin1
Device Type Drawing Pins SPQ (mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
XF28P550SJ6RSHR VQFN RSH 56 4000 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2
XF28P559SJ6PMRQ1 LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
XF28P550SJ6PMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
XF28P559SJ6PNARQ1 TQFP PNA 80 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
XF28P550SJ6PNAR TQFP PNA 80 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
XF28P559SJ6PZRQ1 LQFP PZ 100 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2
XF28P550SJ6PZR LQFP PZ 100 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2
XF28P559SJ6PDTRQ1 TQFP PDT 128 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2
XF28P550SJ6PDTR TQFP PDT 128 1000 330.0 32.4 16.9 16.9 2.0 24.0 32.0 Q2

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SPRSP85 – APRIL 2024 www.ti.com

TAPE AND REEL BOX DIMENSIONS

ADVANCE INFORMATION

Width (mm)
H
W

L
All dimensions are nominal.
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
XF28P550SJ6RSHR VQFN RSH 56 4000 367.0 367.0 35.0
XF28P559SJ6PMRQ1 LQFP PM 64 1000 336.6 336.6 41.3
XF28P550SJ6PMR LQFP PM 64 1000 336.6 336.6 41.3
XF28P559SJ6PNARQ1 TQFP PNA 80 1000 336.6 336.6 41.3
XF28P550SJ6PNAR TQFP PNA 80 1000 336.6 336.6 41.3
XF28P559SJ6PZRQ1 LQFP PZ 100 1000 367.0 367.0 55.0
XF28P550SJ6PZR LQFP PZ 100 1000 367.0 367.0 55.0
XF28P559SJ6PDTRQ1 TQFP PDT 128 1000 367.0 367.0 55.0
XF28P550SJ6PDTR TQFP PDT 128 1000 367.0 367.0 55.0

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 TMS320F28P550SJ, TMS320F28P559SJ-Q1
www.ti.com SPRSP85 – APRIL 2024

TRAY

L - Outer tray length without tabs KO -

Outer
tray
height

W-
Outer
tray
width

ADVANCE INFORMATION
Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

All dimensions are nominal.

Max
Package Package Unit Array CL
Device Pins SPQ Temp. L (mm) W (mm) K0 (μm) P1 (mm) CW (mm)
Type Name Matrix (mm)
(Deg C)
XF28P550SJ9PDT TQFP PDT 128 90 6 x 15 150 315 135.9 7620 15.4 20.3 21
XF28P559SJ9PDTQ1 TQFP PDT 128 90 6 x 15 150 315 135.9 7620 15.4 20.3 21
XF28P550SJ9PZ LQFP PZ 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.4
XF28P559SJ9PZQ1 LQFP PZ 100 90 6 x 15 150 315 135.9 7620 20.3 15.4 15.4
XF28P550SJ9PNA TQFP PNA 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
XF28P559SJ9PNAQ1 TQFP PNA 80 119 7 x 17 150 315 135.9 7620 17.9 14.3 13.95
XF28P550SJ9PM LQFP PM 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13
XF28P559SJ9PMQ1 LQFP PM 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13
XF28P550SJ9RSH VQFN RSH 56 260 10 x 26 150 315 135.9 7620 11.8 10 10.35

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 PACKAGE OUTLINE
PDT0128A SCALE 1.000
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

14.05
PIN 1 ID B
13.95
A 128 97

1 96

14.05 16.1
TYP
13.95 15.9

32
65

33
64
124X 0.4 0.23
128X
0.13
4X 12.4 0.05 C A B

SEE DETAIL A 1.2 MAX

C
(0.13) TYP
SEATING PLANE

0.08 C

0.25
GAGE PLANE (1)

0.75 0.05 MIN

0 -5
0.45

DETAIL A
TYPICAL
DETAIL A
SCALE: 12

4215171/A 10/2023
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
PDT0128A TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM

128 97

128X (1.45)

1
96
128X (0.2)

124X (0.4)

(R0.05) TYP

SYMM
(15.35)

32 65

SEE DETAILS

33 64

(15.35)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
EXPOSED EXPOSED
METAL METAL

METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS
4215171/A 10/2023
NOTES: (continued)

3. Publication IPC-7351 may have alternate designs.

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
5. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and
SLMA004 (www.ti.com/lit/slma004).

www.ti.com
 EXAMPLE STENCIL DESIGN
PDT0128A TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM

128 97

128X (1.45)

1
96

128X (0.2)

124X (0.4)

SYMM
(15.35)

(R0.05) TYP

32 65

33 64

(15.35)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:6X

4215171/A 10/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17
75 51

76 50

100 26 0,13 NOM

1 25
12,00 TYP Gage Plane
14,20
SQ
13,80
16,20 0,25
SQ 0,05 MIN 0°– 7°
15,80

1,45 0,75
1,35 0,45

Seating Plane

1,60 MAX 0,08

4040149 /B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

 PACKAGE OUTLINE
PNA0080A SCALE 1.500
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

10.1
PIN 1 ID B
9.9
80 61
A

1 60

12.22
TYP
11.82

10.1
9.9

20 41

21 40
0.21
76X 0.4 80X
0.15
4X 7.6 0.05 C A B
SEE DETAIL A

1.2 MAX
C
(0.13) TYP
SEATING PLANE

0.08 C

0.25
GAGE PLANE (1)

0.15
0 -5 0.7 0.05
0.5
DETAIL A
DETAIL A
SCALE: 14

TYPICAL

4229169/D 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.

www.ti.com
 EXAMPLE BOARD LAYOUT
PNA0080A TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM

80 61

80X (1.45)

1
60

80X (0.2)

76X (0.4) SYMM

(11.4)

(R0.05) TYP

20 41

21 40

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

0.05 MAX
EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN
ALL AROUND

METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS
4229169/D 02/2024
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com
 EXAMPLE STENCIL DESIGN
PNA0080A TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK

SYMM

80 61

80X (1.45)

1
60

80X (0.2)

76X (0.4) SYMM

(11.4)
(R0.05) TYP

20 41

21 40

(11.4)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:8X

4229169/D 02/2024

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PM0064A SCALE 1.400
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

10.2
B
9.8
NOTE 3
64 49
PIN 1 ID

1 48

10.2 12.2
TYP
9.8 11.8
NOTE 3

16 33

17 32
A
0.27
60X 0.5 64X
0.17
4X 7.5 0.08 C A B

C
(0.13) TYP
SEATING PLANE

0.08
SEE DETAIL A

0.25 (1.4) 1.6 MAX

GAGE PLANE

0 -7 0.75 0.05 MIN

0.45
DETAIL A
DETAIL A
SCALE: 14

TYPICAL
4215162/A 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.

www.ti.com
 EXAMPLE BOARD LAYOUT
PM0064A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM
64 49

64X (1.5)

1
48

64X (0.3)

SYMM
60X (0.5) (11.4)

(R0.05) TYP

16 33

17 32
(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

0.05 MAX
EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN
ALL AROUND

METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS

4215162/A 03/2017
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com
 EXAMPLE STENCIL DESIGN
PM0064A LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK

SYMM

64 49

64X (1.5)

1
48

64X (0.3)

SYMM

60X (0.5) (11.4)

(R0.05) TYP

16 33

17 32
(11.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4215162/A 03/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
RSH0056G SCALE 2.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

7.1
B A
6.9

PIN 1 INDEX AREA

0.25
45 0.15

7.1
6.9

(0.17)

(0.175)

DETAIL A
A35.000

1.0
0.8 TYPICAL
C

SEATING PLANE
0.05 0.08 C
0.00
2X 5.2

SYMM
EXPOSED (0.1) TYP
THERMAL PAD 15 28

14 29

SYMM 57
2X 5.2 5.3 0.1

1 42
52X 0.4 0.225
56X
43 0.125
56
PIN 1 ID 0.1 C A B
(45 X 0.3) 0.65
56X 0.05 C
0.45
SEE DETAIL A
4229539/B 08/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RSH0056G VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 5.3)

SYMM
56 43 SEE SOLDER MASK
56X (0.75) DETAIL

56X (0.2)
1
42

(1.12) TYP
52X (0.4)

(R0.05) TYP (1.28) TYP

SYMM 57
(6.65)

( 0.2) TYP
VIA

14 29

15 28
(1.28) TYP (1.12)
TYP

(6.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 12X

0.05 MIN
0.05 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4229539/B 08/2023
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RSH0056G VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.64) TYP (1.28) TYP

56 43
56X (0.75)

56X (0.2)
1
42

52X (0.4) (1.28) TYP

57 (0.64) TYP
SYMM (6.65)

(R0.05) TYP

16X (1.08)

14 29

15 28
SYMM 16X
(1.08)

(6.65)

SOLDER PASTE EXAMPLE

BASED ON 0.100 MM THICK STENCIL
SCALE: 12X

EXPOSED PAD 57
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4229539/B 08/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 12-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

XF28P550SJ9PDT ACTIVE TQFP PDT 128 90 TBD Call TI Call TI -40 to 150 Samples

XF28P550SJ9PM ACTIVE LQFP PM 64 160 TBD Call TI Call TI -40 to 150 Samples

XF28P550SJ9PZ ACTIVE LQFP PZ 100 90 TBD Call TI Call TI -40 to 150 Samples

XF28P550SJ9RSH ACTIVE VQFN RSH 56 3000 TBD Call TI Call TI -40 to 150 Samples

XF28P559SJ9PDTQ1 ACTIVE TQFP PDT 128 90 TBD Call TI Call TI -40 to 150 Samples

XF28P559SJ9PMQ1 ACTIVE TQFP PTF 128 160 TBD Call TI Call TI -40 to 150 Samples

XF28P559SJ9PZQ1 ACTIVE LQFP PZ 100 90 TBD Call TI Call TI -40 to 150 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 12-Apr-2024

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 IMPORTANT NOTICE AND DISCLAIMER
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