sn74lvc2g100 q1

SN74LVC2G100-Q1
SCLS975A – OCTOBER 2023 – REVISED APRIL 2024
SN74LVC2G100-Q1 Automotive Dual Configurable Multiple-Function Gates

with Flip-Flop
1 Features 3 Description
• AEC-Q100 qualified for automotive applications: The SN74LVC2G100-Q1 is a dual, sequential,
configurable multiple function device with Schmitt
– Device temperature grade 1: -40°C to +125°C
Trigger inputs. Sixteen patterns of a 4-bit input
– Device HBM ESD classification level 2
determines the output state. The output state serves
– Device CDM ESD classification level C4B
as the input to a D-Flip Flop, which is transferred to
• Available in wettable flank QFN (WBQA) package
the Q output on the positive going CLK edge. The
• Operating range from 1.1V to 3.6V
user can choose the logic functions MUX, AND, OR,
• 5.5V tolerant input pins
NAND, NOR, inverter, and non-inverter.
• Supports standard pinouts
• Latch-up performance exceeds 250mA Package Information
per JESD 17 PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)(3)
• ESD protection exceeds JESD 22 SN74LVC2G100-Q1

BQB (WQFN, 16) 3.5mm × 2.5mm 3.5mm × 2.5mm
PW (TSSOP, 16)(4)
– 2000V Human-Body Model (A114-A) 5mm × 6.4mm 5mm × 4.4mm
– 1000V Charged-Device Model (C101) (1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and
2 Applications includes pins, where applicable
(3) The body size (length × width) is a nominal value and does
• Combining power good signals
not include pins.
• Enable digital signals (4) Preview packages only
Y Q
C D Q
CLK
D CLR
CLK
CLR
Functional Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G100-Q1
SCLS975A – OCTOBER 2023 – REVISED APRIL 2024 www.ti.com
Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................12
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................14
3 Description.......................................................................1 7.5 Combinatorial Logic Configurations.......................... 15
4 Pin Configuration and Functions...................................3 8 Application and Implementation.................................. 16
5 Specifications.................................................................. 4 8.1 Application Information............................................. 16
5.1 Absolute Maximum Ratings........................................ 4 8.2 Typical Application.................................................... 16
5.2 ESD Ratings............................................................... 4 8.3 Power Supply Recommendations.............................18
5.3 Recommended Operating Conditions.........................4 8.4 Layout....................................................................... 18
5.4 Thermal Information....................................................5 9 Device and Documentation Support............................19
5.5 Electrical Characteristics.............................................5 9.1 Documentation Support............................................ 19
5.6 Switching Characteristics ...........................................6 9.2 Receiving Notification of Documentation Updates....19
5.7 Timing Characteristics ................................................7 9.3 Support Resources................................................... 19
5.8 Noise Characteristics.................................................. 8 9.4 Trademarks............................................................... 19
5.9 Typical Characteristics................................................ 8 9.5 Electrostatic Discharge Caution................................19
6 Parameter Measurement Information.......................... 11 9.6 Glossary....................................................................19
7 Detailed Description......................................................12 10 Revision History.......................................................... 19
7.1 Overview................................................................... 12 11 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 12 Information.................................................................... 19
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: SN74LVC2G100-Q1

SN74LVC2G100-Q1
www.ti.com SCLS975A – OCTOBER 2023 – REVISED APRIL 2024
4 Pin Configuration and Functions
CLR1
VCC
CLR1 1 16 VCC
DA1 2 15 CLR2
16
DA1 2 15 CLR2 DB1 3 14 DA2
DB1 3 14 DA2 DC1 4 13 DB2
DD1 5 12 DC2
DC1 4 Thermal 13 DB2
Pad Q1 6 11 DD2
DD1 5 12 DC2
CLK1 7 10 Q2
Q1 6 11 DD2
GND 8 9 CLK2
CLK1 7 10 Q2
8
Not to scale
Not to scale Figure 4-2. PW Package, 16-Pin TSSOP (Preview)

GND
CLK2
(Top View)
Figure 4-1. BQB Package, 16-Pin WQFN (Top View)
Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
CLR1 1 I Clear for Channel 1, active low
DA1 2 I Channel 1, Input A
DB1 3 I Channel 1, Input B
DC1 4 I Channel 1, Input C
DD1 5 I Channel 1, Input D
Q1 6 O Channel 1, Output Q
CLK1 7 I Clock for Channel 1, rising edge triggered
GND 8 G Ground
CLK2 9 I Clock for Channel 2, rising edge triggered
Q2 10 O Channel 2, Output Q
DD2 11 I Channel 2, Input D
DC2 12 I Channel 2, Input C
DB2 13 I Channel 2, Input B
DA2 14 I Channel 2, Input A
CLR2 15 I Clear for Channel 2, active low
VCC 16 P Positive Supply
The thermal pad can be connected to GND or left floating. Do not connect to any other
Thermal Pad(2) —
signal or supply.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

(2) BQB package only
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

SN74LVC2G100-Q1
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range -0.5 6.5 V
VI Input voltage range(2) -0.5 6.5 V
VO Output voltage range(2) -0.5 VCC + 0.5 V
IIK Input clamp current VI < 0V -50 mA
IOK Output clamp current VO < 0V -50 mA
IO Continuous output current ±50 mA
IO Continuous output current through VCC or GND ±100 mA
TJ Junction temperature -65 150 °C
Tstg Storage temperature -65 150 °C
Ptot Power dissipation(3) (4) 500 mW
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) For the D package: above 70°C, the value of Ptot derates linearly with 8mW/°C.
(4) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5mW/°C.
5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1) ±2000
Electrostatic
V(ESD) Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level V
discharge ±1000
C4B
(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
Specification Description Condition MIN MAX UNIT
VCC Supply voltage Operating 1.1 3.6 V
VI Input voltage 5.5 V
VO Output voltage (High or low state) VCC V
VCC = 1.8V -4
VCC = 2.3V -8
IOH High-level output current mA
VCC = 2.7V -12
VCC = 3V -24
VCC = 1.8V 4
VCC = 2.3V 8
IOL Low-level output current mA
VCC = 2.7V 12
VCC = 3V 24
Δt/Δv Input transition rise or fall rate 10 ns/V
TA Operating free-air temperature -40 125 °C

SN74LVC2G100-Q1
5.4 Thermal Information

Package Options
THERMAL METRIC(1) PW (TSSOP) BQB (WQFN) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 141.8 98.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 74.0 94.3 °C/W
RθJB Junction-to-board thermal resistance 87.1 67.6 °C/W
ΨJT Junction-to-top characterization parameter 22.3 15.4 °C/W
YJB Junction-to-board characterization parameter 86.6 67.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance - 46.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.5 Electrical Characteristics

-40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX
VT+ Positive-going input threshold voltage 1.1V 0.5 0.8 V
VT+ Positive-going input threshold voltage 1.65 V 0.4 1.3 V
VT+ Positive-going input threshold voltage 1.95 V 0.6 1.5 V
VT+ Positive-going input threshold voltage 2.7V 0.8 2 V
VT+ Positive-going input threshold voltage 3V 0.9 2 V
VT+ Positive-going input threshold voltage 3.6V 1.1 2 V
VT- Negative-going input threshold voltage 1.1V 0.2 0.6 V
VT- Negative-going input threshold voltage 1.65 V 0.2 0.9 V
VT- Negative-going input threshold voltage 1.95 V 0.3 1 V
VT- Negative-going input threshold voltage 3V 0.6 1.5 V
ΔVT Hysteresis (VT+ − VT−) 1.1V 0.07 0.53 V
ΔVT Hysteresis (VT+ − VT−) 1.65 V 0.1 1.2 V
ΔVT Hysteresis (VT+ − VT−) 1.95 V 0.2 1.3 V
ΔVT Hysteresis (VT+ − VT−) 3V 0.3 1.2 V
VOH IOH= –100μA 1.1V to 3.6V VCC - 0.2 V
VOH IOH= –4mA 1.65 V 1.2 V

SN74LVC2G100-Q1
5.5 Electrical Characteristics (continued)

-40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX
VOH IOH= –8mA 2.3V 1.75 V
VOH 2.7V 2.2 V
IOH= –12mA
VOH 3V 2.4 V
VOH IOH= –24mA 3V 2.2 V
VOL IOH= 100μA 1.1V to 3.6V 0.1 0.2 V
VOL IOH= 4mA 1.65 V 0.24 0.45 V
VOL IOH= 8mA 2.3V 0.3 0.7 V
VOL IOH= 12mA 2.7V 0.2 0.4 V
VOL IOH= 24mA 3V 0.55 V
II VI = VCC or GND 3.6V ±1 ±5 µA
Ioff VI or VO = VCC 0V ±1 ±10 µA
ICC VI = VCC or GND, IO = 0 3.6V 1 40 µA
One input at VCC - 0.6V, other inputs at VCC or
ΔICC 2.7V to 3.6V 500 5000 µA
GND
CI VI = VCC or GND 3.3V 5.39 pF
CO VO = VCC or GND 3.3V 6.3 pF
CPD f = 10MHz 1.8V 12 pF
5.6 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See #i#Parameter
Measurement Information
LOAD -40°C to 125°C
PARAMETER FROM (INPUT) TO (OUTPUT) VCC UNIT
CAPACITANCE MIN TYP MAX
1.2V ± 0.1V 15 33 ns
CL = 15pF
1.5V ± 0.12 V 13 18 ns
1.8V ± 0.15 V 13 ns
tpd CLK Q CL = 30pF
2.5V ± 0.2V 8 ns
2.7V 8 ns
CL = 50pF
3.3V ± 0.3V 1 3.5 7 ns
1.2V ± 0.1V 15 51 ns
CL = 15pF
1.5V ± 0.12 V 13 19 ns
1.8V ± 0.15 V 14 ns
tpd CLR Q CL = 30pF
2.5V ± 0.2V 10 ns
2.7V 9 ns
CL = 50pF
3.3V ± 0.3V 1 3.4 9 ns
tsk(o) 3.3V ± 0.3V 1 ns

SN74LVC2G100-Q1
5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
-40°C to 125°C
PARAMETER DESCRIPTION CONDITION VCC UNIT
MIN TYP MAX
1.2V ± 0.1V 10
MHz
1.5V ± 0.15 V 44
fclock Clock frequency 1.8V ± 0.15 V 73
2.5V ± 0.2V 150 MHz
3.3V ± 0.3V 150
1.2V ± 0.1V 4.3
1.5V ± 0.15 V 1.6
CLR low 1.8V ± 0.15 V 4.1
2.5 ± 0.2V 3.3
3.3V ± 0.3V 3.3
tW Pulse duration ns
1.2V ± 0.1V 6.95
1.5V ± 0.15 V 2.75
CLK 1.8V ± 0.15 V 4.1
2.5 ± 0.2V 3.3
3.3V ± 0.3V 3.3
1.2V ± 0.1V 26.4
1.5V ± 0.15 V 12.8
DAx, DBx and DCx 1.8V ± 0.15 V 8.34 ns
2.5 ± 0.2V 6.03
3.3V ± 0.3V 6.03
1.2V ± 0.1V 20.3
1.5V ± 0.15 V 10.793
tSU Setup time before CLK↑ DDx 1.8V ± 0.15 V 6.66 ns
2.5 ± 0.2V 4.824
3.3V ± 0.3V 4.824
1.2V ± 0.1V 11.6
1.5V ± 0.15 V 8.79
CLR Inactive 1.8V ± 0.15 V 4.34 ns
2.5 ± 0.2V 2.51
3.3V ± 0.3V 2.324
1.2V ± 0.1V 0
1.5V ± 0.15 V 0
DAx, DBx and DCx 1.8 ± 0.15 V 1
2.5 ± 0.2V 1
Hold time, data after 3.3 ± 0.3V 1

tH ns
CLK↑ 1.2V ± 0.1V 0
1.5V ± 0.15 V 0
DDx 1.8V ± 0.15 V 0.7
2.5V ± 0.2V 0.7
3.3V ± 0.3V 0.7

SN74LVC2G100-Q1
5.8 Noise Characteristics

VCC = 3.3V, CL = 50pF, TA = 25°C
PARAMETER DESCRIPTION MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.8 V
VOL(V) Quiet output, minimum dynamic VOL -0.8 -0.3 V
VOH(V) Quiet output, minimum dynamic VOH 2.2 3.3 V
VIH(D) High-level dynamic input voltage 2.0 V
VIL(D) Low-level dynamic input voltage 0.8 V
5.9 Typical Characteristics

TA = 25°C (unless otherwise noted)
60 800
1.8 V 3.3 V
54 2.5 V 720 5.0 V
48 640
ICC - Supply Current (µA)
ICC - Supply Current (µA)

42 560
36 480
30 400
24 320
18 240
12 160
6 80
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIN - Input Voltage (V) VIN - Input Voltage (V)
Figure 5-1. Supply Current Across Input Voltage 1.8V and 2.5V Figure 5-2. Supply Current Across Input Voltage 3.3V and 5.0V
Supply Supply
80 5
25°C
70 125°C 4.5
-40°C
60 4
50 3.5
ICC (nA)
VOH (V)
40 3
30 2.5
20 2 1.8 V
2.5 V
10 1.5 3.3 V
5.0 V
0
1
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25
VCC (V)
IOH (mA)
Figure 5-3. Supply Current Across Supply Voltage
Figure 5-4. Output Voltage vs Current in HIGH State
0.55 5
4.95
0.5
4.9
0.45 4.85
0.4 4.8
0.35 4.75
4.7
VOH (V)
VOL (V)
0.3
4.65
0.25 4.6
0.2 4.55
0.15 4.5
1.8 V 4.45
0.1 2.5 V -40°C
4.4 25°C
3.3 V
0.05 5.0 V 4.35 125°C
0 4.3
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 -25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -5 -2.5 0
IOL (mA) IOH (mA)
Figure 5-5. Output Voltage vs Current in LOW State Figure 5-6. Output Voltage vs Current in HIGH State; 5V Supply

SN74LVC2G100-Q1
5.9 Typical Characteristics (continued)

0.5 3.3
3.25
0.45 3.2
0.4 3.15
3.1
0.35 3.05
0.3 3
VOH (V)
VOL (V)
2.95
0.25 2.9
2.85
0.2 2.8
0.15 2.75
2.7
0.1 -40°C 2.65 -40°C
0.05 25°C 2.6 25°C
125°C 2.55 125°C
0 2.5
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 -25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -5 -2.5 0
IOL (mA) IOH (mA)
Figure 5-7. Output Voltage vs Current in LOW State; 5V Supply Figure 5-8. Output Voltage vs Current in HIGH State; 3.3V
Supply
0.6 2.5
0.55 2.45
0.5 2.4
0.45 2.35
0.4 2.3
0.35 2.25
VOH (V)
VOL (V)
0.3 2.2
0.25 2.15
0.2 2.1
0.15 2.05
0.1 -40°C 2 -40°C
25°C 25°C
0.05 125°C 1.95 125°C
0 1.9
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 -16 -14 -12 -10 -8 -6 -4 -2 0
IOL (mA) IOH (mA)
Figure 5-9. Output Voltage vs Current in LOW State; 3.3V Figure 5-10. Output Voltage vs Current in HIGH State; 2.5V
Supply Supply
0.4 1.8
1.775
0.35 1.75
1.725
0.3 1.7
1.675
0.25 1.65
VOH (V)
VOL (V)
1.625
0.2 1.6
1.575
0.15 1.55
1.525
0.1 1.5
-40°C 1.475 -40°C
0.05 25°C 1.45 25°C
125°C 1.425 125°C
0 1.4
0 2 4 6 8 10 12 14 16 -8 -7 -6 -5 -4 -3 -2 -1
IOL (mA) IOH (mA)
Figure 5-11. Output Voltage vs Current in LOW State; 2.5V Figure 5-12. Output Voltage vs Current in HIGH State; 1.8V
Supply Supply

SN74LVC2G100-Q1
5.9 Typical Characteristics (continued)

0.28
0.26
0.24
0.22
0.2
0.18
0.16
VOL (V)
0.14
0.12
0.1
0.08
0.06
-40°C
0.04 25°C
0.02 125°C
0
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
IOL (mA)
Figure 5-13. Output Voltage vs Current in LOW State; 1.8V Supply

SN74LVC2G100-Q1
6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All
input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt ≤ 2.5ns.
The outputs are measured individually with one input transition per measurement.
VCC Vt RL CL ΔV
1.2V ± 0.1V VCC/2 2kΩ 15pF 0.1V
1.5V ± 0.12V VCC/2 2kΩ 15pF 0.1V
1.8V ± 0.15V VCC/2 1kΩ 30pF 0.15V
2.5V ± 0.2V VCC/2 500Ω 30pF 0.15V
2.7V 1.5V 500Ω 50pF 0.3V
3.3V ± 0.3V 1.5V 500Ω 50pF 0.3V
Test VCC
Point
Input Vt Vt
0V
From Output
tPLH(1) tPHL(1)
Under Test
VOH
CL(1) RL
Output
50% 50%
Waveform 1
VOL
(1) CL includes probe and test-fixture capacitance.
tPHL(1) tPLH(1)
Figure 6-1. Load Circuit for Push-Pull Outputs
VOH
Output
50% 50%
Waveform 2
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms Propagation Delays
VCC
90% 90%
Input
10% 10%
0V
tr(1) tf(1)
VOH
90% 90%
Output
10% 10%
VOL
tr(1) tf(1)
(1) The greater between tr and tf is the same as tt.
Figure 6-3. Voltage Waveforms, Input and Output Transition Times

SN74LVC2G100-Q1
7 Detailed Description
7.1 Overview
The SN74LVC2G100-Q1 is a dual, sequential, configurable multiple function device with Schmitt Trigger inputs.
Sixteen patterns of a 4-bit input determines the output state. The output state serves as the input to a D-Flip
Flop, which is transferred to the Q output on the positive going CLK edge. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter, and non-inverter.
7.2 Functional Block Diagram
Y Q
C D Q
CLK
D CLR
CLK
CLR
7.3 Feature Description

7.3.1 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
7.3.2 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The SN74LVC2G100-Q1 can drive a load with a total capacitance less than or equal to the maximum load listed
in the Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the
data sheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the
provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between
the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
7.3.3 Clamp Diode Structure
Figure 7-1 shows the inputs and outputs to this device have negative clamping diodes only.

SN74LVC2G100-Q1
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
Figure 7-1. Electrical Placement of Clamping Diodes for Each Input and Output
7.3.4 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package Package
Solder
Weable Flank Lead Standard Lead
Pad
PCB
Figure 7-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with
automatic optical inspection (AOI). As shown in Figure 7-2, a wettable flank can be dimpled or step-cut to
provide additional surface area for solder adhesion which assists in reliably creating a side fillet. See the
mechanical drawing for additional details.

SN74LVC2G100-Q1
7.4 Device Functional Modes

Table 7-1. Function Table
INPUTS OUTPUT
A B C D Y
L L L L L
L L L H H
L L H L L
L L H H H
L H L L L
L H L H H
L H H L H
L H H H L
H L L L H
H L L H L
H L H L L
H L H H H
H H L L H
H H L H L
H H H L H
H H H H L
Table 7-2. Function Table

INPUTS(1) (2) OUTPUT
CLR CLK D Q
L X X L
H ↑ H H
H ↑ L L
H L X Q0
(1) H = high voltage level, L = low voltage level, X = don't care

(2) This configuration is nonstable; that is, it does not persist when
CLR returns to its inactive (high) level.

SN74LVC2G100-Q1
7.5 Combinatorial Logic Configurations
Y Q
C D Q
CLK
D CLR
CLK
CLR
Combinatorial Logic Configurations
A A
VCC
Y
B Y B
C C
VCC
D D
2 - Input AND Gate 2 - Input NOR Gate
A A
VCC
Y
B Y B
C C
VCC
D D
2 - Input NAND Gate 2 - Input OR Gate
VCC
A A
VCC
B B
C C
Y Y
D D
2 - Input XOR Gate 2 - Input XNOR Gate
Figure 7-3. Logic Configurations

SN74LVC2G100-Q1
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

The SN74LVC2G100-Q1 device offers flexible configuration for many design applications. The following example
describes basic power sequencing using the AND gate configuration. Power sequencing is often used in
applications that require a processor or other delicate device with specific voltage timing requirements to protect
the device from malfunctioning.
8.2 Typical Application
VCC
Temperature
EN
GPO Sensor
MCU
(MSP43x) VO
Figure 8-1. Typical Application Schematic
8.2.1 Design Requirements

8.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions.
The supply voltage sets the electrical characteristics of the device as described in the Electrical Characteristics
section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by
all outputs of the SN74LVC2G100-Q1, plus the maximum static supply current (ICC) listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Ensure the maximum total current through VCC listed in
the Absolute Maximum Ratings is not exceeded.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LVC2G100-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any
transient current required for switching. The logic device can only sink as much current that can be sunk into its
ground connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is
not exceeded.
The SN74LVC2G100-Q1 can drive a load with a total capacitance less than or equal to 50pF while still meeting
all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50pF.
The SN74LVC2G100-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in the CMOS Power Consumption
and Cpd Calculation application note.
Thermal increase can be calculated using the information provided in the Thermal Characteristics of Standard
Linear and Logic (SLL) Packages and Devices application note.

SN74LVC2G100-Q1
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
8.2.1.2 Input Considerations

Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LVC2G100-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10kΩ
resistor value is often used due to these factors.
The SN74LVC2G100-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
8.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
8.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 70pF. This is not a hard limit; by design, however, it will
optimize performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LVC2G100-Q1 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω, so that the maximum output current
from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in
mega ohms; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation

SN74LVC2G100-Q1
8.2.3 Application Curves
VCC
GPO
VO
EN
Figure 8-2. Typical Application Timing Diagram
8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass
capacitors to reject different frequencies of noise. The 0.1μF and 1μF capacitors are commonly used in parallel.
The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 8-3.
8.4 Layout
8.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
8.4.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to
Unused inputs tie to GND or VCC 0.1 F the device
CLR1 1 16 VCC
DA1 2 15 CLR2
DB1 3 14 DA2
DC1 4 13 DB2
DD1 5 12 DC2
Q1 6 11 DD2
CLK1 7 10 Q2
Avoid 90°
corners for GND 8 9 CLK2
signal lines Unused output
left floating
Figure 8-3. Example Layout for the SN74LVC2G100-Q1

SN74LVC2G100-Q1
9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
• Texas Instruments, Designing With Logic application note
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application note
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2023) to Revision A (April 2024) Page

• Changed the status of the datat sheet from: Advanced Information to: Production Data ................................. 1
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 12-Apr-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
CLVC2G100WBQBRQ1 ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC2G1Q Samples
PCLVC2G100WBQBRQ1 ACTIVE WQFN BQB 16 3000 TBD Call TI Call TI -40 to 125 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
OTHER QUALIFIED VERSIONS OF SN74LVC2G100-Q1 :
• Catalog : SN74LVC2G100
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CLVC2G100WBQBRQ1 WQFN BQB 16 3000 180.0 12.4 2.8 3.8 1.2 4.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CLVC2G100WBQBRQ1 WQFN BQB 16 3000 210.0 185.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DYY0016A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
3.36 C
3.16 SEATING PLANE
A PIN 1 INDEX
AREA 0.1 C
14X 0.5
1 16
4.3 2X
4.1
NOTE 3 3.5
8
9
16X 0.31
0.11
0.1 C A B 1.1 MAX
B 2.1
1.9
0.2 TYP
0.08
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.63 0.1
0.33 0.0
DETAIL A
TYP
4224642/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AA
www.ti.com
EXAMPLE BOARD LAYOUT
16X (1.05)
SYMM
1 16
16X (0.3)
SYMM
14X (0.5)
8 9
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK METAL UNDER

OPENING SOLDER MASK SOLDER MASK
METAL OPENING
NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224642/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.05)
SYMM
1 16
16X (0.3)
SYMM
14X (0.5)
8 9
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224642/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1 4.55
4.9
NOTE 3
8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
PW0016A TSSOP - 1.2 mm max height
16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16
SYMM
14X (0.65)
8 9
(5.8)

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
PW0016A TSSOP - 1.2 mm max height
16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16
SYMM
14X (0.65)
8 9
(5.8)

SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
BQB 16 WQFN - 0.8 mm max height
2.5 x 3.5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226161/A
www.ti.com
PACKAGE OUTLINE
BQB0016B WQFN - 0.8 mm max height
INDSTNAME
2.6 A
B 2.4
PIN 1 INDEX AREA 3.6

3.4
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
0.8 MAX C
SEATING PLANE
0.05 0.08 C
0.00
1.1
0.9
2X 0.5
(0.2) TYP
8 9
10X 0.5
7
10
SYMM (0.16)
2X SYMM 17 2.1
2.5 1.9
16X 0.3
0.2
0.1 C A B
15
2 0.05 C
PIN 1 ID 1 16
(OPTIONAL)
SYMM 16X 0.5
0.3
4226135/A 08/2020
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
INDSTNAME
(2.3)
(1)
1 16
16X (0.6)
16X (0.25)
2 15
10X (0.5)
SYMM 17
(2) (3.3)
2X (0.75)
7 10
(R0.05) TYP
(Ø 0.2) VIA 8 9
TYP 2X (0.5)
SYMM

EXPOSED METAL SHOWN
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
INDSTNAME
(2.3)
(0.95)
1 16
16X (0.6)
16X (0.25)
2 15
17
10X (0.5)
SYMM
(1.79) (3.3)
2X (0.75)
7 10
(R0.05) TYP
METAL TYP 8 9
2X (0.5)
SYMM

EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

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SN74LVC2G100-Q1

SCLS975A – OCTOBER 2023 – REVISED APRIL 2024

SN74LVC2G100-Q1 Automotive Dual Configurable Multiple-Function Gates

• ESD protection exceeds JESD 22 SN74LVC2G100-Q1

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC2G100-Q1

4 Pin Configuration and Functions

DB1 3 14 DA2 DC1 4 13 DB2

Not to scale Figure 4-2. PW Package, 16-Pin TSSOP (Preview)

Figure 4-1. BQB Package, 16-Pin WQFN (Top View)

Table 4-1. Pin Functions

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

5.2 ESD Ratings

5.3 Recommended Operating Conditions

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC2G100-Q1

5.4 Thermal Information

5.5 Electrical Characteristics

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

5.5 Electrical Characteristics (continued)

5.6 Switching Characteristics

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC2G100-Q1

5.7 Timing Characteristics

Hold time, data after 3.3 ± 0.3V 1

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

5.8 Noise Characteristics

5.9 Typical Characteristics

ICC - Supply Current (µA)

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC2G100-Q1

5.9 Typical Characteristics (continued)

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

5.9 Typical Characteristics (continued)

Figure 5-13. Output Voltage vs Current in LOW State; 1.8V Supply

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC2G100-Q1

6 Parameter Measurement Information

1.2V ± 0.1V VCC/2 2kΩ 15pF 0.1V

1.5V ± 0.12V VCC/2 2kΩ 15pF 0.1V

1.8V ± 0.15V VCC/2 1kΩ 30pF 0.15V

2.5V ± 0.2V VCC/2 500Ω 30pF 0.15V

2.7V 1.5V 500Ω 50pF 0.3V

3.3V ± 0.3V 1.5V 500Ω 50pF 0.3V

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

7.3 Feature Description

12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC2G100-Q1

7.3.4 Wettable Flanks

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

7.4 Device Functional Modes

Table 7-2. Function Table

(1) H = high voltage level, L = low voltage level, X = don't care

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LVC2G100-Q1

7.5 Combinatorial Logic Configurations

Combinatorial Logic Configurations

2 - Input AND Gate 2 - Input NOR Gate