Microprocessor Architecture

Intel 8085
Syllabus:
Main features of 8085. Block diagram. Components.
Pin-out diagram. Buses. Registers. ALU. Memory.
Stack memory. Timing and Control circuitry. Timing
states. Instruction cycle, Timing diagram of MOV
and MVI.
Evolution of Microprocessor

8085

3
 Intel 8085A processor
• Introduced by Intel March 1976
• 8-bit microprocessor chip
• 40 Pin in DIP Package
• 5V power supply
• Binary compatible
• 3 MHz clock
• 6500 Transistors
• 64K Byte addressable memory
• Instruction set
• allows simple and low cost
microcomputer systems to be built
4
 Block Diagram of Microcomputer system

8085A Microprocessor
Address
bus

ALU ROM RAM I/O I/O

Register interface devices
Array

Data bus Control

Control bus
The 8085A
• The 8085A is an 8-bit general purpose microprocessor
that can address 64K Bytes of memory.
• It has 40 pins and uses +5V for power. It can run at a
maximum frequency of 3 MHz.
– The pins on the chip can be grouped into 6 groups:
Address Bus
Data Bus
Control and Status Signals
Power supply and frequency
Externally Initiated Signals
Serial I/O ports

6
 8085A Pin Diagram

Clock

8085 A

Address ( Low order)

Address Bus
and data Bus
( High order)

8085 A Pin Diagram

7
8085A Pin Diagram

8
Logic pin out: 8085A

All dc signals can be classified in six groups

1. Address bus
Lower order address bus multiplexed with data bus
Higher order address bus
2. Data bus
Data bus multiplexed with low order address bus
3. Control and status signals
4. Power supply and frequency signals
5. Interrupts and peripheral/ externally initiated signals
6. Serial I/O ports
 8085A : 6 Groups GRD

1 2 40 20
SID 5 X1 X2 Vcc
Serial I/O Ports SOD 4
A15 26

TRAP 6 High – Order Address Bus

RST 7.5 7
RST 6.5 8 A8 21
RST 5.5 9 AD7 19
INTR 10
Interrupts & Multiplexed Address/ Data Bus
Externally Initiated AD0 12
Signals READY 35 30 ALE
HOLD 39 29 S0
33 S1
RESETIN 36
34 IO/M
32 RD
31 WR Control and
11 INTA Status Signals
38 HLDA

3 37
RESET CLK
OUT OUT 10
The 8085A: Bus Structure

The 8-bit 8085 (or Micro Processing Unit) communicates

with the other units using a 16-bit address bus, an 8-bit
data bus and a control bus

11
Bus system connection

12
Bus Organization

What is a Bus?
A bus is a shared set of pins, wires or signals, used
for communicating signals among devices, having
common functions as bus
What is system Bus?
A system bus is a bundle of wires grouped together
to serve a single purpose in microprocessor.
These are address bus, the data bus and control bus.

4 PCI Express bus card slots

(from top to bottom: x4, x16, x1 and x16),
compared to a traditional 32-bit PCI bus
card slot (very bottom).
Bus Definitions
What is an Address Bus?
The bus over which the microprocessor sends out the address of a
or I/O location is called as the address bus.
In 8085A µP, Address bus is of 16 bits A0 – A15. This means th
maximum 16 bit address which means it can address 65,536
locations

What is a Data Bus?

A data bus simply carries data. In 8085A it is of 8 bits parallel
bidirectional. Internal data buses carry information within the
external buses carry data between the processor and the memo
bus is used for both read/write operations. During write operat
will put the data on to the data bus. On a read operation, the m
will get the data from the specific memory location and put it in t

What is a control bus?

The control bus is used for sending control signals to the memor
The CPU sends control signal on the control bus to enable the ou
memory devices or I/O port devices. Some of the control bus sig
Memory read, Memory write, I/O read , I/O write.
 The Address and Data Bus: Interconnections between units

The address bus consists of 16 address lines of which

1. 8 signal lines A8 – A15 ; the Upper Address bus; are
unidirectional.
2. 8 address bits A0 – A7; the lower Address bus ; are
multiplexed (time shared) with the 8 data bits; the bits AD0
– AD7 are bi-directional and serve as A0 – A7 and D0 – D7
at the same time.

During the execution of any instruction, which requires 3

to 4 clock cycles; these lines (AD0 – AD7 ) carry the
address bits during the early part, then during the late
parts of the execution, they carry the 8 data bits.

Bus: A shared group of wires used for communicating signals among devices
15
The Address and Data Bus: Interconnections between units

Important Facts
– A latch is used for processing before the function of the bits
changes.
– Address latch Enable ALE: used in order to separate the
address from the data,
– 16 address lines are capable of addressing a total of 216 =
65,536 (64k) memory locations.
– are tri-state lines

Address locations: 0000 (Hex) – FFFF (Hex)

Data range: 00 (Hex) – FF (Hex)
The most significant bits (MSB) of address goes through Address bus and LSB
goes through multiplexed address - data bus.
16
The Control and Status Signals
There are 4 main control and status signals.
These are:
• ALE: Address Latch Enable. This signal is a pulse that
become 1 when the AD0 – AD7 lines have an address on
them. It becomes 0 after that. This signal can be used to
enable a latch to save the address bits from the AD lines.
• RD: Read. Active low.
• WR: Write. Active low.
• IO/M: This signal specifies whether the operation is a
memory operation (IO/M=0) or an I/O operation (IO/M=1).
• S1 and S0 : Status signals to specify the kind of
operation being performed .

Bus: A shared group of wires used for communicating signals among devices
17
De-multiplexing Address- data bus (AD7-AD0): The ALE Signal

– it is obvious that the AD7– AD0 lines are serving a dual

purpose (Address as well as data lines) and that they need
to be demultiplexed to be used in both situations.

– The high order bits of the address remain on the bus for
~three clock periods. However, the low order bits remain
for only one clock period and they would be lost if they are
not saved externally.

– To make sure an external latch to save the value of AD7–

AD0 when it is carrying the address bits is used. The ALE
signal enables this latch.

18
Address Latch Enable (ALE)
∙ This signal is an output signal early in a machine cycle to advise the
external circuitry that the AD0 - AD7 lines contain the lower 8 bits of a
memory address.

∙ It should be used to clock a catch-and-hold circuit ( latch circuit using an IC

Flip-flop 8 bit chip) such as a 74LS245 or 74LS373, so that the full address
will be available to the system for the rest of the machine cycle.

∙ The falling edge of ALE is the point at which the signals on the AD lines, as
well as the S0, S1, and IO/M lines will be stable and may be taken by the
external circuitry.

19
 The Latch in Detail
Enable
ALE is High the latch is transparent ALE

G
Output changes according to input data AD7 D Q A7
Output follows the input as long as G is
high

ALE Low Output of latch represents low 74LS373

order address bus

The output does not change and OC

retains the D input level which is the
low order address

8 such latches de-multiplex the AD bus D7

Figure 3.3 of Gaonkar 20

De- multiplexing AD7-AD0: Circuit

8085
A15-A8

ALE

Latch
AD7-AD0 A7- A0

D7- D0

The ALE operates as a pulse during first clock period T1

– the address is latched. Then when ALE goes low, the address
is saved
– The AD7– AD0 lines can be used for and as the bi-directional
data lines. Figure 3.3 of Gaonkar 21
Control and Status signals: Explanation

ALE - Address Latch Enable

• is an output signal from µP used to de-multiplex
AD0-AD7 contents.
• is a positive going pulse generated when a new
operation is started by µP.
• when pulse goes high it indicates that the
contents of AD0-AD7 are address.
• when it is low it indicates that the contents of
AD0-AD7 are data
• Pin 30
Control and Status signals: Explanation
RD
• is an output signal (3 state, active low) from µP
• used to Read data from memory or IO device.
• indicates that the selected memory location or I/O
device is to be read and the data bus is ready for
accepting data from the memory or I/O device to and
fro the µP
• pin32
WR
• is an output signal (3 state, active low) from µP
• used for Write data onto memory or IO device.
• indicates that the data on data bus is to be written
into the selected memory location or I/O device.
• pin31
Control and Status signals: Explanation

• is an output signal from µP

• used to select memory or an IO device..
• operation will be directed toward memory (line is low), or
toward I/O (line is high).
• is a status signal
• indicates that the read / write operation relates to the memory
or IO device.
• active high to indicate an I/O operation.
• active low for memory operations
• Pin 34
• approximates in one line what S0 and S1 lines do in two.

S0 & S1 (pin 29 & 33) status signals similar to IO/M; can identify various operations
and
INTA (11)and HLDA ( 38) the interrupt and hold acknowledge signals go low when
µP acknowledges an interrupt or responds to a HOLD request.
8085A μP: functions of groups pin wise

Power Supply
VCC :- Vcc is to be connected to +5V power supply at pin 40
Vss :- Ground reference at pin 20

Frequency Control Signals

There are 3 important pins in frequency control group in 8085A µP

• X1 and X2 (pin1&2) are the inputs from the crystal or clock

generating circuit. The frequency is internally divided by 2.
• to run the µP at 3 MHz, a clock running at 6 MHz should be
connected to the X1 and X2 pins.
• CLK (OUT): An output clock pin (37) provides a system clock
signal to external circuits which need to be in synchronization
with the μP
8085A μP: functions of groups pin wise
Interrupts and Externally initiated signals/ operations
Signals initiated by an external device to request the µP to do a particular task or work.

Interrupt & Interrupt Acknowledge (INTR & INTA):

Pins 10, 11
• These lines provide a vectored interrupt capability to the 8085.
• Upon receipt of INTR, the μP will complete the instruction in process, then
generate a low output INTA as it enters the next machine cycle to acknowledge
the interrupt.
• The interrupting device will jam a Restart (RST) instruction onto the data bus,
which the μP uses to locate an interrupt vector in low RAM.
RST 5.5, 6.5, 7.5:
Pins 7, 8, 9
• These three lines are additional interrupt lines which generate an automatic
Restart,.
• These lines have priority over the INTR line, and each other.
• They also have certain electrical characteristics for assertion, and may be masked
off or on by software.
TRAP: pin 6; This is an unmaskable interrupt with a fixed vector in RAM.
8085A μP: functions of groups
RESET IN (36) & RESET OUT (3)
These lines provide for both μP and system reset.
The RESET IN line is generated asynchronously by some sort of external
circuit, such as an RC network or Reset switch.
∙ the signal is an active low input signal to reset the μP
∙ program Counter inside the μP is set to zero
Upon receipt of this signal, the μP internally synchronizes the Reset with
the clock of the processor, then generate RESET OUT for other
devices in the system
● used to reset all devices connected with the μP when the system
is reset
READY (35)
∙ is an input signal used to delay the μP Read and Write cycle until a
slow responding peripheral is ready to send or accept data. It is
used often whenever a wait state is needed, since the RAM is not
able to provide the data or accept it in the time allowed by the μP .
∙ The negation of Ready, by being pulling it low, will cause the 8085
to enter wait states.
8085A μP: functions of groups

HOLD & HOLD ACKNOWLEDGE (HOLD & HLDA):

∙ These pins provide the 8085 with a DMA capability by allowing another
processor on the same system buses to request control of the buses.
∙ Upon receipt of HOLD ( an input signal at pin 39), the μP will tristate its
address, data, and certain control lines, then generate HLDA (output signal
low at pin 38).
∙ This signals also informs the other processor that it may proceed. As the μP
will remain off the buses until HOLD is negated.

SERIAL INPUT DATA & SERIAL OUTPUT DATA (SID & SOD):
∙ These two pins 5 and 4 provide for a single serial input or output line to/from
μP They implement the serial transmission of data
∙ The lines are brought into the device as D7, and may be tested or set by the
Read Interrupt Mask (RIM) or Set Interrupt Mask (SIM) instructions.
∙ These two instructions also have control over the mask which controls the
RST 5.5, 6.5, and 7.5, and TRAP, interrupts.
∙ The SID and SOD lines are simple single bit I/O lines; any timing required to
provide external communication via them must be provided by the software

28
Memory

Memory: Where instructions (programs) and data are stored

• Organized in arrays of locations (addresses) anywhere between 0000 to

FFFFH depending on the size of memory chip and chip select position
• Each Memory Location stores one byte (8 bits) of data ( 00 to FF H)
• There is a a lot of interaction between the μP and the memory for
• exchange of information during program execution
• control signals and their timing
• Memory has its requirements and the microprocessor has its
requirements as well the interfacing operation is simply the matching of
these requirements

Memory and its organization has been done in detail in the last unit
29
Memory structure & its requirements

Data Lines
ROM
RAM
Input Buffer WR

Address Address CS
CS
Lines Lines

Output Buffer RD Output Buffer RD

Data Lines
Date
Lines

• The process of interfacing the above two chips is the same with the μP

• The ROM does not have a WR signal

30
Interfacing Memory with μP

– Accessing memory can be summarized into the

following three steps:
– Select the chip.
– Identify the memory register.
– Enable the appropriate buffer.

– Translating this to microprocessor domain:

– The microprocessor places a 16-bit address on the address bus.
– Part of the address bus will select the chip and the other part will
go through the address decoder to select the register.
– The signals IO/M and RD combined indicate that a memory read
operation is in progress. The MEMR signal can be used to enable
the RD line on the memory chip.

31
Generating Control Signals

The 8085 generates a single RD signal. However, the signal needs to

be used with both memory and I/O. So, it must be combined with the
IO/M signal to generate different control signals for the memory and
I/O.
– Keeping in mind the operation of the IO/M signal the following
circuitry can be used to generate the right set of signals:

32
Address decoding in µP

The result of address decoding is the identification of a

register for a given address.
– A large part of the address bus is usually connected
directly to the address inputs of the memory chip.
– This portion is decoded internally within the chip.
– What concerns us is the other part that must be
decoded externally to select the chip.
– This can be done either using logic gates or a
decoder.

33
The Overall Picture

Putting all of the concepts learnt till now together, the figure explains
data flow from μP to memory

Chip Selection
A15- A10 Circuit

8085
CS
A15-A8

ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip

WR RD IO/M D7- D0
RD WR

34
Input Output
I/O devices enable μP to interact with the world
– Device interface hardware connects actual
device to bus
– The CPU views the I/O device registers just
like memory that can be accessed over the
bus. However, I/O registers are connected to
external wires, device control logic, etc.
– Problems envisaged
• Reads may not return last value written
• Writes may have side effects

35
The 8085A μP: Internal Data Operations

The internal architecture of the 8085 CPU is capable of

performing the following operations:

– Store 8-bit data (in Registers, Accumulator)

– Perform arithmetic and logic operations (ALU)

– Test for conditions (IF / THEN)

– Sequence the execution of instructions

– Store temporary data in RAM during execution

36
 The 8085A μP: CPU Internal Structure

To perform these operations the μP

requires
● registers
● an arithmetic and logic unit (ALU)
● control unit
and
● internal buses for information flow

37
8085A Functional Block Diagram

38
8085A Functional Block Diagram: Sections
Arithmetic and Logic section
– Instruction Decoder and Machine cycle Encoder
• accepts OPCODE from instruction register, decodes it and returns decoded
information to control logic.
• information includes what operation is to be executed, who is going to
execute it it, etc. It means it will understand the instruction in this block.
• decoded information is passed on to the timing and control unit that generates
control signals
– Address Buffer & Address/Data Buffer for transfer
– Incrementer / Decrementer Address Latch
• 8 bit contents of register or a memory location can be incremented or
decremented by 1
• 16-bit register is used to increment or decrement the content of program
counter and stack pointer register by 1
• Increment or decrement can be performed on any register or a memory
location
– Interrupt Control
– Serial I/O Control Group
– Timing And Control
39
8085A Functional Block Diagram: Sections
Register Section
• Temporary Register
– In 8085 available temporary register are W and Z registers; not available to the
programmer, but uses them internally to hold temporary data during execution
of some instructions. They are of 8 bits each
• General Purpose Register
– B,C,D,E,H & L are used as general purpose register of 8 bits each
– these registers can also be used to work in pairs to hold 16-bit data/ address,
such as B-C, D-E and H-L The H-L pair works as a memory pointer.
– A memory pointer holds the address of a particular memory location.
• Special Purpose Registers
– Accumulator 8 bits
– Status or Flag Register 5 bits
– Instruction Register 8 bits
– Program Counter 16 bits It also has
– Stack Pointer 16 bits Multiplexer for register select
Address Buffer & Address/Data Buffer
Incrementer/Decrementer Address Latch
40
8085A Functional Block Diagram: Sections

Timing And Control Section

– is a very important unit as it synchronizes the registers and flow of data
through various registers and other units.
– accepts data from instruction decoder and generates micro steps to
perform it
– in addition it accepts clock inputs for synchronizing operations.
– consists of an oscillator and controller sequencer which sends control
signals needed for internal and external control of data and other units.

• Control Signals: READY, RD, WR, ALE

• Status Signals: S0, S1, IO/M
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT

41
Control unit in simple words
• The circuitry that controls the flow of information
through the processor, and coordinates the
activities of the other units within it.
• it is the brain within the brain, as it controls what
happens inside the processor, which in turn
controls the rest of the PC.
• On a regular processor, the control unit performs
the tasks of fetching, decoding, managing
execution and then storing results.

42
Timing and control unit

43
The 8085: Simplified block diagram

44
Internal structure and basic operation of μP

Address bus
ALU Register
Section Section
Data bus

Control and timing

section Control bus

Block diagram of a microprocessor

45
 Arithmetic and logic unit (ALU)
• The unit performs arithmetic and logical operations
• the most important components in a μP
• typically the part of processor that is designed first.
• able to perform the basic logical operations (AND, OR),
including addition
• inclusion of inverters on the inputs enables the same ALU
hardware to perform subtraction (adding by 2’s
complement), and operations NAND and NOR.
• In addition to the arithmetic & logic circuits, ALU includes
accumulator, which is part of every arithmetic & logic op.
• includes a temporary register used for holding data
temporarily during the execution of the operation. This
temporary register is not accessible by the programmer
46
Internal structure of ALU

2 bits ALU 4 bits ALU

47
 The 8085: Registers

8085 has
six 8 bit general purpose programmable registers B, C, D, E, H, and L.
Accumulator and Flag register are part of ALU are also 8 bits, Program Counter
and Stack Pointer are 16 bit memory pointers which are specific purpose registers
48
Something about Register sets
• Registers are memory elements in the CPU of μP

• The register section/array consists completely of circuitry used to

temporarily store data or program codes until they are sent to the
ALU or to the control section or to memory.

• The number of registers are different for any particular CPU and the
more register a CPU has will result in easier programming tasks.

• Registers are normally measured by the number of bits they can hold,
for example, an 8 bit register stores 8 bit of data simultaneously.
Similarly, 32 bit register will have 32 bits of data

49
Registers: Details
Registers
– Six general purpose 8-bit registers: B, C, D, E, H, L
– They can also be combined as register pairs to perform 16-bit
operations: BC, DE, HL
– The H&L register pair may be used to store indirect addresses
– Registers are programmable (data load, move, etc).
Accumulator
– single 8-bit register that is part of the ALU
– specific purpose register
– used for arithmetic / logic operations
– the result is always stored in the accumulator
Example: accumulator use in summing a list of numbers.
– accumulator is initially set to zero, then each number in turn is added to the value in
the accumulator. The result of each addition is automatically reflected in the
Accumulator (A)
– Only when all numbers have been added is the result( held in the accumulator) written
to main memory or to another location, other registers, etc. 50
 The Flags Register (5 bits)
Flag register is a group of flip flops used to give status of different
operations result.
• is connected to ALU.
• Once an operation is performed by ALU the result is transferred
on internal data bus and status of result will be stored in flip
flops.
• Indicate the result of condition tests
• are called Zero (Z), Carry (CY), Sign (S), Parity (P), and
Auxiliary Carry (AC) flags.
• Conditional operations (IF / THEN) are executed based on the
condition of these flag bits
• Have critical importance in the decision making process of the μP
• The most commonly used flags are Zero and Carry
51
The Flag register
Flags
S-sign flag
The sign flag is set (=1) if bit D7 of the accumulator is 1 after an arithmetic or
logic operation indicating the number is negative
Z-zero flag
Set (=1) if the result of the ALU operation is 0. Otherwise is reset (=0). This flag
is affected by operations on the accumulator as well as other registers. (DCR B).
AC-Auxiliary Carry
This flag is set (=1) when a carry is generated from bit D3 and passed to D4 .
This flag is used only internally for BCD operations.
P-Parity flag
After an ALU operation if the result has an even number of 1’s the p-flag is se
t(=1). Otherwise it is reset (=0). The flag is used to indicate even / odd parity.
CY-carry flag
After an ALU operation if the operation results in a carry the carry flag is set (=1),
indicating that answer in the accumulator is larger than 8 bits. Otherwise it is
reset (=0). The flag is also used to indicate borrow for subtraction
D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

52
Flag Name Description

Z Zero flag Indicates that the result of a mathematical or logical operation was zero.

Indicates that the result of an operation produced an answer greater

than the number of available bits. (This flag may also be set before a
C Carry flag
mathematical operation as an extra operand to certain instructions, e.g.
"add with carry".)

Bits not used in the Flag Register. There are only five flipflops in the
X No Flag flag register that are of active use. These are D7, D6, D4, D2 and D0
bits of FR

Indicates that the result of a mathematical operation is negative or

positive. In some processors, the N and S flags have different
S Negative/ Sign flag meanings: the S flag indicates whether a subtraction or addition has
taken place, whereas the N flag indicates whether the last operation
result is positive or negative.

Indicates that the result of an operation has overflowed according to the

AC Auxiliary Carry Flag CPU's BCD word representation, similar to the carry flag but for BCD
operations.

Indicates that the accumulator after an operation has even or odd

P Parity
number of 1’s

53
Program counter (PC)
Contains the memory address (16 bits) of the instruction
that will be executed in the next step. It is
• 16 bit register, used to store the next address of the
operation code to be fetched by the CPU.
• Not much use in programming, but as an indicator to
user only.
• Purpose of PC in a μP is to
– store address of next instruction to be executed.
– count the number of instructions.
– store base address of the stack.
– store address of tos (top of stack)
54
Stack pointer (SP)

Contains the address information(16 bit) of the location of

the stack. SP is always incremented/decremented by 2
– The stack is configured as a data structure that grows
downward from high memory to low memory.

– At any given time, the SP holds the 16-bit address of the

next free location in the stack.

– The stack acts like any other stack when there is a

subroutine call or on an interrupt. ie. pushing the return
address on a jump, and retrieving it after the operation is
complete to come back to its original location.
55
 Microprocessor Timing

Fetch

Execute
Decoding and Executing an Instruction
• Fetching Cycle
– The fetch cycle takes the instruction required from memory,
stores it in the instruction register, and
– increments the program counter by one so that it points to the
next instruction.
• Execute cycle
– Places the memory address of the instruction on the address bus
– Indicates the operation status on the status lines
– Sends the MEMR control signal to enable memory, fetches the
instruction byte and places it in the instruction decoder
– Executes the instruction.

57
 Decoding and Executing an Instruction: Example
The Accumulator contains
data 82 H. The instruction
MOVC,A ( opcode 4F H) is
fetched from memory From Memory
location 2005 H.
The steps in decoding and 4F
Data
executing the instruction Bus
are Internal
Data Bus
1. The contents of data
Instruction
bus (4F) are placed in Register
the instruction register C 82H
82H 82H 4F B
and decoded
Temporary
2. The contents of Accumulator
Register Register B and C
accumulator (82 H) are Instruction
Decoder
transferred to the
temporary register in the
ALU Timing &
Control
3. The contents of
temporary register are 58
transferred to register C
Microprocessor clock
• the speed at which a microprocessor executes instructions is
called the clock rate, . Every computer contains an internal clock
that regulates the rate at which instructions are executed and
synchronizes all the various computer components.
• The CPU requires a fixed number of clock cycles to execute each
instruction. The faster the clock, the more instructions the CPU
can execute per second. Clock speeds are expressed in
megahertz (MHz) or gigahertz ((GHz).
• Some microprocessors are superscalar, which means that they
can execute more than one instruction per clock cycle.
• Like CPUs, expansion buses also have clock speeds. Ideally, the
CPU clock speed and the bus clock speed should be the same so
that neither component slows down the other. In practice, the bus
clock speed is often slower than the CPU clock speed, which
creates a bottleneck. This is why new local buses, such as AGP,
are being developed.

59
8085 μP: System Timing
The time required by the 8085 to fetch and execute
one machine language instruction is defined as an
Instruction Cycle.
The instructions may be of different complexities,
with the result that the more complicated
instructions take longer to execute.
The 8085’s method of instruction execution inside
the μP is more organized, however, and so the time
required to execute any instruction is more
predictable and more regular.

60
8085 μP: Cycles and States

– T- State: One subdivision of an operation. A

T-state lasts for one clock period.
• An instruction’s execution length is usually
measured in a number of T-states. (clock cycles).
– Machine Cycle: The time required to complete
one operation of accessing memory, I/O, or
acknowledging an external request.
• This cycle may consist of 3 to 6 T-states.
– Instruction Cycle: The time required to complete
the execution of an instruction.
• In the 8085, an instruction cycle may consist of 1 to
6 machine cycles.
61
More on the 8085 machine cycles
• The 8085 executes several types of instructions
with each requiring a different number of
operations of different types. However, the
operations can be grouped into a small set.
• The three main types are:
• Memory Read and Write.
• I/O Read and Write.
• Request Acknowledge.
• These can be further divided into various
operations (machine cycles).

62
8085 μP: The Processor cycle
● Each instruction is divided into one to five Machine Cycles.
● Each machine cycle is essentially the result of the need, by the
instruction being executed, to access the RAM.
● The shortest instruction would require just one machine cycle, in
which the instruction itself is obtained from RAM.
● The longest, of five machine cycles, would consist of five RAM
accesses, the first to obtain the instruction byte itself, and the
remaining four to be divided into fetching and saving other
bytes. For example, cycles numbers 2 & 3 may be needed to
fetch two more bytes of an address, while numbers 4 & 5 may
be needed to save a 2-byte address somewhere else in RAM.
● The type of machine cycle being executed is specified by the
status lines IO/M, S0, and S1, and the control lines RD, WR,
and INTA.

These six lines can define seven different machine cycle types 63
Machine Cycles :Types

1. OP CODE FETCH
2. MEMORY READ
3. MEMORY WRITE
4. I/O READ
5. I/O WRITE
6. INTERRUPT ACKNOWLEDGE
7. BUS IDLE

64
Control and Status signals
ALE, RD, WR, IO/M, S0 and S1
Machine cycle Status Control
IO/M S1 S0 Signals

Op-code Fetch 0 1 1 RD = 0
Memory Read 0 1 0 RD = 0
Memory Write 0 0 1 WR = 0
IO Read 1 1 0 RD = 0
IO Write 1 0 1 WR = 0
Interrupt 1 1 1 INTA = 0
Acknowledge
Halt Z 0 0 RD, WR = Z
Hold Z X X and INTA = 1

Reset Z X X

65
Generating Control Signals

The 8085 generates a single RD signal. However, the signal needs to

be used with both memory and I/O. So, it must be combined with
the IO/M signal to generate different control signals for the memory
and I/O.
– Keeping in mind the operation of the IO/M signal we can use
the following circuitry to generate the right set of signals:

A rewind of the signals

66
Example: Instruction Fetch Operation
– All instructions (program steps) are stored in memory.

– To run a program, the individual instructions must be read from

the memory in sequence, and executed.

• Program counter puts the 16-bit memory address of the

instruction on the address bus

• Control unit sends the Memory Read Enable signal to

access the memory

• The 8-bit instruction stored in memory is placed on the data

bus and transferred to the instruction decoder

• Instruction is decoded and executed

67
 Example: Instruction Fetch Operation

The instruction MOVC,A (code 4FH) is stored in memory location 2005 H.

The Accumulator has data byte 82 H. Illustrate the data flow and list the sequence of
events when the instruction code is fetched by the μP, execution of the instruction and
68
The execution time if the clock frequency is 2 MHz
 Example: Instruction Fetch Operation
Step 1
To fetch the instruction the following steps are performed

1. The Program Counter places the 16 bit address 2005 H

of the memory location on to the address bus
2. The control unit sends the memory read control signal
MEMR, active low to enable the memory chip
3. The instruction 4F stored in the memory location is
placed on the data bus and transferred to the
microprocessor

The instruction code 4FH ( MOVC,A) is stored in memory address 2005 H. Illustrate the
Data flow and list the sequence of events when the instruction code is fetched by the μP
69
Op-code Fetch Machine Cycle
The first step of executing any instruction is the
Op-code/Instruction fetch cycle.
– In this cycle, the μP brings in the instruction’s Op-code
from memory.
• To differentiate this machine cycle from the very similar memory
read cycle, the control & status signals are set as follows:
* IO/M=0, S0 and S1 are both 1.
– Opcode fetch machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the op-code.
• T4 (fourth T state) is used to decode and execute it i.e. transfer
accumulator contents to register C.
– It is also possible for an instruction to have 6 T-states in
an op-code fetch machine cycle.

70
Op-code Fetch: Timing Diagram

T1 T2 T3

CLK
Timing transfer of byte
from memory to μP for a
A15 –A8 Higher order MOVC,A instruction code
20H
address

AD7 – AD0 05H 4FH

Low order Memory

ALE address content

IO/M M

RD

71
Op-code Fetch: Timing Diagram MOVC,A

Explanation
1. The Program Counter places ….
At T1 the higher order memory address20 H is placed on the
address lines A15 - A8 abd low order 05H on to the bus AD7 –
AD0 and ALE goes high. The status signal IO/M goes low
indicating it is a memory related operation. S0 and S1 are both 1
and is implied in the figure as it is an opcode fetch cycle
2. The control unit sends … The control signal RD is sent during
clock period 2 (T2). The RD signal is active during two clock
periods
3. The instruction 4F stored …When memory is enabled the
instruction bye 4F is placed on the bus AD7-AD0 and transferred
to the μP. The RD signal causes 4F to be placed on data bus
shown by arrow and when RD goes high it causes the bus to go to
the high impedance state ( tri state)
72
 Execution of the instruction: MOVC,A
The μP does the following sequence
1. places the contents of the PC ( 2005H) on the address bus, 20 on
A15-A8 and 05 onto AD7-AD0
2. Causes the ALE to go high; demultiplexes the address/data bus
3. Identifies the nature of the machine cycle…opcode fetch…by using
the status signals IO/M=0, S0 and S1 are both 1.
4. During T2, control signal RD is sent to enable the memory and
increment the PC by 1 to next location 2006H. The contents of
2005H is placed on data bus (4F)
5. Reads the byte 4F and places it in instruction register (T3)
6. Decodes the instruction places the accumulator content (82H) in
temporary register and then transfers to register C (T4)
Memory Hex
Location code
(H) (H)

2005 4F
73
MOV C,A: Timing Diagram

T1 T2 T3 T4

CLK

A15 –A8 Higher order

20H
address unspecified

AD7 – AD0 05H 4FH

Low order Memory

ALE address content

IO/M IO/M =0, S0=S1=1 Opcode fetch

S0, S1

RD

74
 Memory Read Machine Cycle

The memory read machine cycle is exactly

the same as the Opcode fetch except:
– It only has 3 T-states
– The S0 signal is reset to 0 instead of it being 1
– IO/M=0, S0=0 and S1=1. (See)

75
Example: Memory Read Operation

76
 The Memory Read Machine Cycle
To understand the memory read machine cycle, let’s study the
execution of the following instruction:
– MVI A, 32 H
( Move immediately into the accumulator data 32H)
In memory, this instruction looks like:
– The first byte 3EH represents the opcode for loading a byte
into the accumulator (MVI A),
– the second byte is the data to be loaded (32H).
The 8085 needs to read these two bytes from memory before it
can execute the instruction. Therefore, it will need at least two
machine cycles.
– The first machine cycle is the opcode fetch as discussed
Memory Hex
Location code – The second machine cycle is the Memory Read Cycle.
(H) (H) – Figure 4.2 page 99 Goankar.
2000 3E
2001 32 77
MVI A 32H: Timing Diagram

78
 Reference

Microprocessor Architecture, Programming and

Applications with 8085; Ramesh S. Gaonkar;
Wiley Eastern Limited.