Outline

❑ Bubble Pushing
❑ Compound Gates
❑ Logical Effort Example
❑ Input Ordering
❑ Asymmetric Gates
❑
Lecture 9:
Skewed Gates
❑ Best P/N ratio
Combinational
Circuit Design

10: Combinational Circuits CMOS VLSI Design 4th Ed. 2

Example 1 Example 2
module mux(input s, d0, d1, 2) Sketch a design using NAND, NOR, and NOT gates.
output y);
Assume ~S is available.
assign y = s ? d1 : d0;
endmodule D0
S
1) Sketch a design using AND, OR, and NOT gates. Y
D0
D1
S S
Y
D1
S

10: Combinational Circuits CMOS VLSI Design 4th Ed. 3 10: Combinational Circuits CMOS VLSI Design 4th Ed. 4

Bubble Pushing Example 3

❑ Start with network of AND / OR gates 3) Sketch a design using one compound gate and one
❑ Convert to NAND / NOR + inverters NOT gate. Assume ~S is available.
❑ Push bubbles around to simplify logic
– Remember DeMorgan’s Law
D0
Y Y
S
(a) (b) Y
D1
S
Y Y

D
(c) (d)

10: Combinational Circuits CMOS VLSI Design 4th Ed. 5 10: Combinational Circuits CMOS VLSI Design 4th Ed. 6
 Compound Gates Example 4
❑ Logical Effort of compound gates ❑ The multiplexer has a maximum input capacitance of
unit inverter AOI21 AOI22 Complex AOI 16 units on each input. It must drive a load of 160
Y=A Y = A B+C Y = A B+C D Y = A (B + C) + D E units. Estimate the delay of the two designs.
D
A A E
A Y
B
C
Y
B
C
Y
A
B
Y
H = 160 / 16 = 10 B = 1 N = 2
D C
D0 D0
A 4 B 4 A 4 B 4 B 6
S S
A
2
Y
C 4
Y
C 4 D 4
Y
C 6 A 3
Y Y
1 A 2
C 1
A 2 C 2 D 6 E 6
Y D1
D1
B 2 B 2 D 2 E 2 A 2
D 2 B 2 C 2 S S
P =2+2=4 P = 4 +1 = 5
gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3
p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3 G = (4 / 3)g(4 / 3) = 16 / 9 G = (6 / 3)g(1) = 2
gC = 5/3 gC = 6/3 gC = 8/3 F = GBH = 160 / 9 F = GBH = 20
fˆ = N F = 4.5
p = 7/3 gD = 6/3 gD = 8/3
fˆ = N F = 4.2
p = 12/3 gE = 8/3
p = 16/3 D = Nfˆ + P = 12.4 D = Nfˆ + P = 14

10: Combinational Circuits CMOS VLSI Design 4th Ed. 7 10: Combinational Circuits CMOS VLSI Design 4th Ed. 8

Example 5
❑ Annotate your designs with transistor sizes that
achieve this delay.

8 8
8 10 10
8 25 25 10 10 24
Y Y
25 6 6 12
8 8 25 6 6
8
8
160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36
16

10: Combinational Circuits CMOS VLSI Design 4th Ed. 9 10: Combinational Circuits CMOS VLSI Design 4th Ed. 10

Cont.. Cont..

10: Combinational Circuits CMOS VLSI Design 4th Ed. 11 10: Combinational Circuits CMOS VLSI Design 4th Ed. 12
 Input Order Inner & Outer Inputs
❑ Our parasitic delay model was too simple ❑ Inner input is closest to output (A)
2 2 Y
– Calculate parasitic delay for Y falling ❑ Outer input is closest to rail (B)
• If A arrives latest? 2 A 2
B 2
• If B arrives latest? 2.33 ❑ If input arrival time is known
– Connect latest input to inner terminal
2 2 Y
A 2 6C

B 2x 2C

10: Combinational Circuits CMOS VLSI Design 4th Ed. 13 10: Combinational Circuits CMOS VLSI Design 4th Ed. 14

Asymmetric Gates Symmetric Gates

❑ Asymmetric gates favor one input over another ❑ Inputs can be made perfectly symmetric
❑ Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input A
2 2
reset
Y
Y
– So total resistance is same A 1 1
❑ gA = 10/9 2 2
Y
❑ gB = 2 A 4/3
B 1 1
reset 4
❑ gtotal = gA + gB = 28/9
❑ Asymmetric gate approaches g = 1 on critical input
❑ But total logical effort goes up

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Skewed Gates HI- and LO-Skew

❑ Skewed gates favor one edge over another ❑ Def: Logical effort of a skewed gate for a particular
❑ Ex: suppose rising output of inverter is most critical transition is the ratio of the input capacitance of that
– Downsize noncritical nMOS transistor gate to the input capacitance of an unskewed
HI-skew unskewed inverter unskewed inverter
inverter delivering the same output current for the
inverter (equal rise resistance) (equal fall resistance) same transition.
2 2 1
A Y A Y A Y
1/2 1 1/2
❑ Skewed gates reduce size of noncritical transistors
❑ Calculate logical effort by comparing to unskewed – HI-skew gates favor rising output (small nMOS)
inverter with same effective resistance on that edge. – LO-skew gates favor falling output (small pMOS)
– gu = 2.5 / 3 = 5/6 ❑ Logical effort is smaller for favored direction
– gd = 2.5 / 1.5 = 5/3 ❑ But larger for the other direction
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Catalog of Skewed Gates Asymmetric Skew
Inverter NAND2 NOR2 ❑ Combine asymmetric and skewed gates
2 2 B 4 – Downsize noncritical transistor on unimportant
Y
unskewed A
2
Y
A 2
A 4
Y
input
1 2 1 1
– Reduces parasitic delay for critical input
guu = 1 B guu = 4/3 guu = 5/3
gdd = 1 gdd = 4/3 gdd = 5/3
gavg
avg
=1 gavg
avg
= 4/3 gavg
avg
= 5/3

2 2 B 4
Y
2 A 4
HI-skew A Y
A 1
Y A
Y
1/2 gu = 5/6
u
B 1 guu = 1 1/2 1/2 guu = 3/2 reset
gdd = 5/3 gdd = 2 gdd = 3
gavg
avg
= 5/4 gavg
avg
= 3/2 gavg
avg
= 9/4
1 1 B 2 1 2
Y
A 2
Y
1 A 2
LO-skew A Y Y A 4/3
1 guu = 4/3 B 2 guu =2 1 1 guu =2
gdd = 2/3 gdd =1 gdd =1 reset 4
gavg
avg
=1 gavg
avg
= 3/2 gavg
avg
= 3/2

10: Combinational Circuits CMOS VLSI Design 4th Ed. 19 10: Combinational Circuits CMOS VLSI Design 4th Ed. 20

Best P/N Ratio P/N Ratios

❑ We have selected P/N ratio for unit rise and fall ❑ In general, best P/N ratio is sqrt of equal delay ratio.
resistance ( = 2-3 for an inverter). – Only improves average delay slightly for inverters
❑ Alternative: choose ratio for least average delay – But significantly decreases area and power
❑ Ex: inverter
– Delay driving identical inverter A
P
Inverter NAND2 NOR2
– tpdf = (P+1) 1
– tpdr = (P+1)(/P) 2 2
Y
B 2
2
fastest 1.414 A 2
A
– tpd = (P+1)(1+/P)/2 = (P + 1 +  + /P)/2 P/N ratio
A
1
Y
gu = 1.15 B 2 gu = 4/3 1 1
Y
gu = 2

– dtpd / dP = (1- /P2)/2 = 0

gd = 0.81 gd = 4/3 gd = 1
gavg = 0.98 gavg = 4/3 gavg = 3/2

– Least delay for P = 

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Observations
❑ For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in stages
– Latest-arriving input
❑ For area and power:
– Many simple stages vs. fewer high fan-in stages

10: Combinational Circuits CMOS VLSI Design 4th Ed. 23