Source: Synopsys & Intel

Lecture 7
• Thin-Body MOSFET’s Process I
– SOI vs. Bulk FinFETs
– Fin Patterning Techniques
– High-κ/Metal Gate Technologies

Reading: multiple research articles (reference

list at the end of this lecture)
 SOI vs. Bulk FinFET: Overall Structure
Bulk FinFET SOI FinFET (w/o BOX)

T. Hook (IBM), FDSOI Workshop (2013)

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 SOI FinFET Process Flow

• Fin heights are defined by the SOI film thickness.

• Higher (SOI) substrate cost; yet cheaper
doping/implantation cost.
A. Yagishita (Toshiba), SOI Short Course (2009)
10/7/2013 Nuo Xu EE 290D, Fall 2013 3
 Bulk FinFET Process Flow
• Fin heights are defined by the punch-
through stopping (PTS) layer position.

A. Yagishita (Toshiba), SOI Short Course (2009)

10/7/2013 Nuo Xu EE 290D, Fall 2013 4
 Fin Patterning
Spacer Lithography
a.k.a. Sidewall Image Transfer (SIT)
or Self-Aligned Double Patterning (SADP)

1. Deposit & pattern sacrificial layer 3. Etch back mask layer

to form “spacers”

SOI
SOI
BOX
BOX
2. Deposit mask layer (SiO2 or Si3N4)
4. Remove sacrificial layer;
etch SOI layer to form fins

SOI
fins
BOX
BOX • Extra lithography steps
required to etch the
• Note that fin pitch is 1/2 that of patterned layer unused fins.

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 Benefit on Multiple Device Pitch
• By using spacer lithography technique, multiple fin pitches can be
implemented using a single lithography step.

• 2n lines after nth lithography ! A. Yagishita (Toshiba), SOI Short Course (2009)

10/7/2013 Nuo Xu EE 290D, Fall 2013 6

 Benefit on Fin Edge Roughness
Y.-K. Choi, IEDM (2002)

Y.-K. Choi, IEDM (2002)

• Spacer lithography technique provides more uniform fin width than the
conventional lithography, due to σlitho > σCVD

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 Benefit on Gate Edge Roughness
X. Sun, TSM (2010)

Conventional Litho. Spacer Gate Litho. Tri-Gate Id-Vg Curves

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 Fin Sidewall Damage Removal
by H2 Annealing
Mobility Improvement by H2 Annealing Equivalent Gate Input Noise

H2 annealing causes Si atoms remigration at fin sidewall surfaces

 provides smaller surface roughness and lower Dit.
 reduces shape corners to mitigate “corner effect”.

Y.-K. Choi, IEDM (2002)

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 Fin Sidewall Damage Removal
by Neutral Beam Etching

• Neutral Beam Etching: negative ions in

the plasma can be neutralized by passing
through the carbon aperture.
• TEM picture shows more abrupt fin/oxide
interface after NBE → Lower Dit
• Higher fin mobility w/ NBE

K. Endo, TED (2006)

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 SOI vs. Bulk FinFET: Isolation
Bulk FinFET SOI FinFET (w/o BOX)

• Retrograde-well doping required as punch • No doping process needed to

through-stop (PTS) layer. avoid PT.
• HALO is also often adopted. • Rectangular fin shape.
• Tapered fin shape due to STI process.

T. Hook (IBM), FDSOI Workshop (2013)

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 Impacts of Retrograde Well Doping
w/ Retrograde Well Doping w/o Retrograde Well Doping

-3
10
w/o Retrograde Well
10
-4 w/ Retrograde Well
Normalized Current (A/um)

Ids
-5
10
-6
10

10
-7 • Even with the finite steepness of
10
-8 Isub
P-FinFET
retrograde well doping (~15nm/dec in Si), it
-9 Lg=20nm, WFin=9nm is still preferred to insert the doping peak
10
-10
around the fin base, causing some level of
10
-11
performance degradation in the fin.
10
-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Gate Voltage (V)
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 More Issues for Bulk FinFET Isolation

J. G. Fossum, SSE (2010)

T. Hook (IBM), FDSOI Workshop (2013)

• Single PTS doping can not be used for SoC circuits with multi-fin width.
• Additional STI required to separate N and P-bulk FinFET, to avoid CMOS
latchup effect.
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 Steep Retrograde Well Doping in Bulk
FinFET

A. Hokazono,
VLSI-T(2008) &
IEDM(2009)

H. Bu (IBM), SOI Workshop (2011)

10/7/2013 Nuo Xu EE 290D, Fall 2013 14
 Fin Shape Variations in Bulk FinFETs
Rectangular shape Trapezoidal shape (Intel’s Tri-Gate) “Hybrid”-shape

Chipworks, 2012 D. Shamiryan, SSE (2009)

Typical STI trench tilt: 70o ~ 85o

Key requirements for bulk fin shape (process perspective):

 Isolation trench refilling
 High aspect-ratio fin patterning
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 Impacts of Fin Shape on Electrostatics
assuming same top fin width:

T. Hook (IBM), FDSOI Workshop (2013)

A. Arsenov’s group, GSS Website (2012)

Key requirements for bulk fin shape (device performance/reliability

perspective):
 Good electrostatic control
 Low corner electric field, to prevent TDDB or BTI
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 Impacts of Fin Shape on Current
Charge concentration across a FinFET
X-section as increasing gate voltage

A. Arsenov’s group, GSS Website (2012)

Considering Quantum Mechanical + Strain Effect

P-FinFET N-FinFET
Simulation Data from Synopsys Inc., (2013)
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 High-κ/Metal Gate Technology
SiN Poly-Si
Metal Gate Process Flow
Low 
High  W MG Poly-Si
Si HK

Gate First / MIPS Si

(Metal-Inserted-
Poly-Si Gate) MG
W
HK Poly-Si

High- First Si

Gate Last / RMG MG

(Replaced Metal Gate)
W
Poly-Si HK
Si
High- Last

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 Gate First vs. Gate Last
L. Ragnarsson, IEDM (2009)

Gate-First (MIPS) Gate-Last (RMG)

High-κ Dielectric First First → Last

Metal Gate First Last
Thermal Budget High Low
EOT Thick Thin
Mobility Low High
Workfunction Control Bad Good
Cost Low High
Process Complexity Low High (CMP)
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 Thin-Body MOSFET Gate Process
A. Yagishita (Toshiba), SOI Short Course (2009)

IBM’s ETSOI MOSFET

A. Khakifirooz, EDL (2012)

• Extremely-thin UTB SOI is not compatible with high--last process,

due to the Si sacrifice during dummy (poly-Si) gate removal.
• FinFET RMG is challenging, due to the 3-D CMP process.
• Cost is the dominant issue.
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 References
1. T. Hook, “FinFET Isolation Approaches and Ramifications: Bulk vs. SOI,” FDSOI Workshop at
Hsinchu, Taiwan, April, 2013.
2. A. Yagishita, “Process and Device Technologies for FinFET and Its Alternative Devices,” IEEE SOI
Conference Short Course, Foster City, CA, October, 2009.
3. X. Sun, T.-J. King Liu, “Spacer Gate Lithography for Reduced Variability due to Line Edge
Roughness,” IEEE Transactions on Semiconductor Manufacturing, Vol.23, No.2, pp.311-315, 2010.
4. K. Endo, S. Noda, M. Masahara, T. Kubota, T. Ozaki et al., “Fabrication of FinFETs by Damage Free
Neutral Beam Etching Technology,” IEEE Transactions on Electron Devices, Vol.53, pp.1826-1833,
2006.
5. Y.-K. Choi, L. Chang, P. Renade, J.-S. Lee, D. Ha et al., “FinFET Process Refinements for Improved
Mobility and Gate Work Function Engineering,” IEEE International Electron Device Meeting Tech.
Dig., pp.259-262, 2002.
6. J. G. Fossum, Z. Zhou, L. Mathew, B.-Y. Nguyen, “SOI versus Bulk-Silicon Nanoscale FinFETs,”
Solid-State Electronics, Vol. 54, pp.86-89, 2010.
7. H. Bu, “FinFET Technology: A Substrate Perspective,” IEEE SOI Conference Short Course, Tempe,
Arizona, September, 2011.
8. D. Shamiryan, A. Redolfi, W. Boullart, “Dry Etching Process for Bulk FinFET Manufacturing,” Solid-
State Electroncis, Vol.86, pp.96-98, 2009.
9. Gold Standard Simulation website, 2012:
http://www.goldstandardsimulations.com/index.php/news/blog_search/simulation-analysis-of-the-
intel-22nm-finfet/
10. L.-A. Ragnarsson, Z. Li, J. Tseng, T. Schram, E. Rohr et al., “Ultra-Low EOT Gate First and Gate
Last High Performance CMOS Achieved by Gate-Electrode Optimization,” IEEE International
Electron Device Meeting Tech. Dig., pp.663-666, 2009. 21