EE382M: VLSI-II EXAM 1 March 13, 2019

EE382M - VLSI II
MID SEMESTER EXAM
SPRING 2019

Print Name Here _________________________________

UT – EID _________________________________
Signature _________________________________

This is a closed book, closed notes and closed electronic devices exam. The
exam is to be completed in ninety (90) minutes.

_______Please check here to indicate that you have received all parts of the
exam. (9 Pages including this one)

Problem 1 ________________ (25 Points)

Problem 2 ________________ (25 Points)

Problem 3 ________________ (25 Points)

Problem 4 ________________ (15 Points)

Problem 5 ________________ (10 Points)

Total for exam ________________ (100 Points)

1
EE382M: VLSI-II EXAM 1 March 13, 2019

Problem 1: Qualitative Questions (5 points each) 25 Points

a. What is power gating and what are its variants?

Ans: Power gating is a technique where we shut down power to a domain (block) when the block is
not in use. This helps in reduction of leakage power.

Power Gating Variants:

• Coarse-grained Power Gating
• Fine-grained Power Gating
• Selective Power Gating
• Super-cutoff Power Gating
• Zig -Zag Power Gating

b. Explain at least 2 techniques to reduce leakage power.

Ans: Explain any two of the following:

• Transistor Sizing
• Transistor Stacking
• Multi-VT cell swapping
• Body biasing (VTCMOS)
• DVS
• Power gating
• Input vector control

c. What is rush current and wake-up time?

Ans: Rush current is the current that flows through the switches when the switches transition from
open to closed. Wakeup time is the time required for the virtual rail to settle down to an operational
voltage after the switches have been closed.

2
EE382M: VLSI-II EXAM 1 March 13, 2019

d. In power gating technique, what are the disadvantages of having a large power gate size.
Explain at least 2 points.

Ans: Even though Large power gate size is better to get low voltage drop, they will occupy larger
area and have larger off-state leakage compared to smaller switches. Large size also implies a higher
capacitance to switch between sleep and active mode.

e. What is DIBL and how does it impact leakage current?

Ans: Drain Induced barrier lowering (DBL) is a short channel effect that leads to reduction of
threshold voltage of the transistor at high drain voltage values.

At high VDS (drain source voltage) values, the width of the region below the gate that is already
depleted (by the drain fields) increases and a smaller threshold voltage suffices to cause strong
inversion.

Lower threshold voltage leads to higher leakage current. Hence, DIBL increases leakage.

3
EE382M: VLSI-II EXAM 1 March 13, 2019

Problem 2: Transistor Characteristics 25 Points

Look at the circuit and graph below to answer the questions that follow.

a. Quantify VA (The voltage at node A) 5 points

Ans: MOSFET N1 needs to support 1uA of current. Ioff current is 1nA and Subthreshold swing (S)
is 100mV/decade. Therefore, 1uA current (3 orders of current change) will occur at VGS = 300mV
i.e. 0.3V.

VGS=1.2V-VA

VA=1.2V-0.3V=0.9V

Hence, VA = 0.9V.

4
EE382M: VLSI-II EXAM 1 March 13, 2019

b. Quantify VOut when Vin=0V. 10 points

Ans: Vin=0V => VGS of N3=0V

Hence, current through N3 (IN3) = 1nA as WN3 = 1um.

For N2 which is 10um wide, Ioff = 10nA. SS=100mV/decade. To support 1nA current through N2
(1 order of current less), VGS of N2 should be -100mV (-0.1V). VGS of N2 is VA-VOut. Since VA is
0.9V, VOut = 0.9+0.1=1V

Hence, VOut=1V.

c. Quantify VOut when Vin=1.2V. 10 points

Ans:

IN3=IN2

βW3(VGS_N3 – Vt) = βW2(VA – VOut - Vt)

β * 1 * (1.2 – 0.3) = β * 10 * (0.9-VOut – 0.3)

0.9 = 10(0.6 – VOut)

VOut=0.6-0.09=0.51V

Hence, VOut = 0.51V

5
EE382M: VLSI-II EXAM 1 March 13, 2019

Problem 3: Level Shifters 25 Points

a. Given the input voltage transition at in, plot the voltage response at points A, B and out.
Mention the voltage levels. Also, plot the currents I_lo1, I_hi1, I_hi2, Ignd1 and Ignd2.
(5+5+5+2+2+2+2+2 Points)

6
EE382M: VLSI-II EXAM 1 March 13, 2019

Problem 4: Flip-Flop Timing 15 Points

The logic gates of the flip-flop below all have a delay of 15ps. Write your approach and timing
equations.

a. What is the SETUP time? _______60ps_________

D – X: 6 gates Clk - Clk_B’: 3 gates

D – Y: 6 gates Clk – Clk_

A: 2 gates

Worst case: D-Y -> 4 gates = 60ps

b. What is the CLOCK-Q delay? _________60ps__________

Inv – inv – tg - inv => 4 gates = 60ps

7
EE382M: VLSI-II EXAM 1 March 13, 2019

c. What is the HOLD time? _________0ps__________

3inv (max clk) – 3inv (Data) = 0ps

Problem 5: Flip-Flop Timing 10 Points

In the flip-flop design given below, find the max and min combinational delay. Write your approach
and equations. Assume Tcycle = 100ps. Clock skew inverter delay is 10ps each.

Device Setup Clock-Q Hold

FF1 30ps 15ps 20ps

FF2 25ps 20ps 30ps

a. What is the MIN- DELAY (Tcomb_min)? _________35ps_________

Tclk-q1 + Tcd >= Thold2 + 2Tinv

Tcd >= 30ps + 20ps – 15ps

Tcd >= 35ps

Therefore, Tcomb_min = 35ps

8
EE382M: VLSI-II EXAM 1 March 13, 2019

b. What is the MAX- DELAY (Tcomb_max)? _________80ps_________

Tclk-q1 + Tpd + Tsu2 <= Tclk + 2Tinv

Tpd <= 100ps + 20ps – 25ps – 15ps

Tpd <=80ps

Therefore, Tcomb_max = 80ps