International Journal of

INTELLIGENT SYSTEMS AND APPLICATIONS IN

ENGINEERING
ISSN:2147-67992147-6799 www.ijisae.org Original Research Paper

Efficient Design of Configurable Logic Block with Customized LUT

using Reversible Fault Tolerant Gates
Ravi L. S.*1, Dr. Naveen K. B.2

Submitted: 10/12/2023 Revised: 14/01/2024 Accepted: 31/01/2024

Abstract: The parity of the input vector must match the parity of the output vector in a fault-tolerant reversible logic gate circuit. It
enables the circuit's problem to be discovered. As a result, parity-preserving reversible logic will assist in the development of fault-
tolerant systems for nanotechnology. It is commonly recognized that fault-tolerant (FT) reversible logic gates (RLG) are compatible with
revolutionary computing paradigms such as optical and quantum computing. We presented reversible fault-tolerant lookup tables (LUTs)
in this paper, which are employed in the development of Configurable logic blocks (CLB). CLB architecture employs fault-tolerant
reversible logic components such as D-Latch, MS-Flip-flop, and Multiplexer. The suggested architecture is simulated, tested logically,
and implemented using an FPGA Spartan 3. The simulation findings and implementation demonstrate the reversible fault tolerant gate
design's functioning. The power dissipation and delay in reversible fault tolerant gates are found to be less, with a power reduction of
around 95.5 % at 90 nm CLB technology.

Keywords: Look-Up Table, FPGA, Fault Tolerant, Reversible Logic, Low Power Dissipation, Garbage Output

examine a generic 4-input LUT-based logic block.

1. Introduction
The main objective of the project work are as follows:
Energy is dissipated as a result of irreversible hardware
computing, regardless of how it is realized due to the loss • To create a Configurable Logic Block (CLB) based
of information, is shown by R. Landaurer’s research in on Reversible Fault Tolerant Gates (RFTG)
early 1960. Each k: T: ln2 joule of information is
• Design of Reversible Fault Tolerant (RFT) D-latch,
dissipated, where k is the Boltzman constant is denoted by
Master Slave Flip Flop and Multiplexer using our
k and absolute temperature is denoted by T [1, 2]. The
proposed gate, which aims for the shortest unit delay,
huge energy dissipation is avoided by using reversible
the lowest quantum cost, and the smallest number of
logic gates for making a circuit, as shown by Benett
gates.
demonstrated in 1973. A system to continue to function
successfully by using the Fault tolerance even if any of its • A novel RFT multiplexer with a number of gates, unit
components fail (due to one or more faults). FPGAs are latency, and lower quantum cost has been presented.
typically made up of a set of customizable I/O blocks,
• The unit delay, quantum cost, garbage, and the
interconnects, and logic blocks [3,4]. The FPGA can be
number of gates is minimized by using the enhanced
customized to meet the needs of any application. FPGAs
RFT LUT-based FPGA CLB.
have evolved from simple logic to extremely sophisticated
programmable fabrics as a result of the same • The CLB Models' performance evaluation is
semiconductor technological advancements which have determined by using the FPGA technology with
brought processors to their performance limits. Plessy 90nm (Backend) logic.
logic blocks and Lookup-Table (LUT) are the most
The following is the structure of this paper, the previous
common logic blocks. A LUT can use fewer logic blocks
understanding of FPGA and reversible logic design as well
to implement more logic with more inputs. As a result, it
as a review of relevant research are shown in section 2.
aids in a smaller routing area [5,6]. The area and delay
Section 3 shows an enhanced architecture of a RFT 4 to 1
performance are increased by using the 3 to 4 input LUT
multiplexer, master slave flip flop and D-latch. The
size shown by the authors in the paper. As a result, we'll
simulation result and performance analysis are discussed in
_______________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________

1
Research Scholar, Dept. of Electronics and Communication Engg., B.G.S Section 4. Finally, the paper is concluded in the last
Institute of Technology, Adichunchanagiri University, B.G. Nagara, Section.
1
Assistant Professor, Rajeev Institute of Technology, Hassan.
ORCID ID : https://orcid.org/0009-0005-8405-5977
2
Professor, Dept. of Electronics and Communication Engg., B.G.S 2. Basic Definitions and Literature Survey
Institute of Technology, Adichunchanagiri University, B.G. Nagara,
Email: [email protected] The terms quantum cost, LUT, unit delay, garbage output,
* Corresponding Author Email: [email protected]
reversible fault tolerant gate is defined in this section. In
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addition, the most recent related studies are discussed 2.6. Delay
briefly.
A is expressed in terms of unit delay, which corresponds to
2.1. Reversible Gate a 1*1 or 2*2 elementary quantum gate's delay, like
controlled-V+ gate, Controlled-V gate, CNOT, and NOT.
A digital circuit is represented by a reversible gate with the
As a result, measuring delay requires the circuit's logical
same no. of outputs and inputs. There will be k outputs if
depth. The gate delay for Fredkin is 5.
there are k inputs. Each output pattern is distinct from the
input pattern. One-on-one correspondence is the term for 2.7. Power
this, which is represented by k*k.
The power of each reversible logic gate adds up to the total
2.2. Fault Tolerant Gate power of the circuit. There are n reversible logic gates with
powers p1; p2; p3; :::::::; pn in a reversible logic circuit
A fault-tolerant gate ensures input-output parity. The
then the reversible logic circuit's overall power is given by:
analytical expression for a k*k RFTG is,
𝐼1 _ 𝐼2. . . . _ 𝐼𝑁 = 𝑂1 _ 𝑂2. . . . _ 𝑂𝑁 P= P i
(1)
The ability to identify faulty signals is a key attribute of a Quantum-dot cellular automata circuits are designed by
fault tolerant gate. Fault tolerant reversible gates include using the layout strategy, described by the author in [7].
the new fault tolerant gate (NFT), Modified Islam gate Designing configurable memory and logic blocks at a Low
(MIG), Islam gate (IG), Double Feynman gate (F2G), and Cost are developed by using the presented technique. For
Fredkin gate (FRG). FPGA-based systems, a novel approximate adder design
2.3. Garbage Output methodology is proposed by the author in [8] with
enhanced performance of the system while keeping SWaP
Employing garbage outputs maintains the reversible benefits. The overall optimization is achieved, and also the
characteristic. These garbage outputs are either undesired long carry chain in light of FPGA hardware architecture is
or unusable outputs. Garbage outputs are kept expensive. fine-tuned by using this methodology with only a single
2.4. Quantum Cost Look-Up Table (LUT) delay, regardless of operand size.
When compared to the existing best-known LUT-based
A cascade of quantum gates can be used to replace a RLG
BCD adders, a parallel BCD adder is described by the
in a circuit. The RG is designed by using the 2×2, 1×1
author in [9], it gains a radical achievement VHDL is used
reversible gates or the number of quantum gates, is called
to code the proposed BCD adder and Virtex-6 platform is
the quantum cost. The q-bits are used in quantum gates
used for implementation with ISE 13.1. It has a -3 speed
whereas pure logic values are used in RLG. There are
grade for the Xilinx FPGA XC6VLX75T. The reversible
numerous basic quantum gates. Controlled-V+ gate,
PLAs is designed by the author in [10] that maximize the
controlled-V gate, controlled-NOT (CNOT) gate and NOT
utility of garbage outputs while lowering the amount of
gate are some examples. A single qbit is inverted using the
ancilla inputs. The range of these gates are analyzed by
NOT gate. Only if the control q-bit is 1, The CNOT gate
author in [11]. The reversible circuits are designed, and
(Controlled-NOT gate) performs the inversion of the input
implemented by using these gates for quantum
q-bit. The square root of NOT (SRN) gate is another name
computation. Using the reversible logic principle, the low-
for the controlled-V gate. Inversion operation is equal to
power Configurable Fault-Tolerant Embryonic Hardware
two consecutive V operations. The square root of the NOT
is designed by the author in [12] lower area overhead.
gate is the controlled-V+ gate. FRG has a quantum cost of
5, IG has a cost of 7, F2G has a cost of 2, MIG has a cost
3. Proposed Methodology
of 7 and NFT has a cost of 5.
This section describes the algorithms, design layout,
2.5. Quantum Gate Complexity
theoretical characteristics, and operation of the proposed
Elementary quantum gates such as Controlled-V+ gates, logic parts for use in RFT FPGAs based on LUTs.
Controlled-V, CNOT, and NOT are used to construct each
• “Mubin_Sworna_Hasan (MSH) Gate”
reversible logic gate. The RLG is designed by using the
number of elementary quantum gates, which is represented • “Mubin_Sworna_Babu (MSB) Gate”
as quantum gate complexity. The controlled-V+ gate and
The following section contains these two Gates Block-
Controlled-V gate (SRN) are similar gates. Four CNOT
Diagrams, Truth-Table and transistor-realization.
gates and three controlled-V & V+ gates make up a
Fredkin gate. Mubin_Sworna_Hasan (MSH) Gate: Consists of (a, b, c,
d} → inputs and {p.q.r.s} → output-vectors and with
Quantum-Realization. Figure 2 and 1 displays the quantum

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realization and block diagram of MSH gate. Truth table is represents the {a,b,c,d,e,f} → inputs and {p,q,r,s,t,u} →
displayed in table 1. output-vectors. Figure 4 and 3 shows the quantum
realization and block diagram of MSB gate.

Fig. 1. Block diagram of MSH – Gate

Fig. 3. Block diagram of MSB – Gate

Fig. 2. MSH – Quantum Realization

Table 1. MSH Gate

INPUT OUTPUT Parity

A B C D P Q R S 1=Odd
0=Even
Fig. 4. MSB – Quantum Realization
0 0 0 0 0 0 0 0 0
3.1. RFT D_Latch
0 0 0 1 0 0 0 1 1
By using proposed MSH-gate, we design the “Reversible-
0 0 1 0 0 1 1 1 1 Fault-Tolerant” D_latch”, and generates the required
0 0 1 1 0 1 1 0 0 output, s => clk’.Feed-back EXOR clk. D along with 2-g1
and g2 garbage output and 1-constant input. It is designed
0 1 0 0 0 1 0 0 1 by 4 MSH gate. The total quantum cost of this D-latch is
0 1 0 1 0 1 0 1 0 10. Figure 5 shows the RFT D latch designed by MSH
gate.
0 1 1 0 0 0 1 1 0
0 1 1 1 0 0 1 0 1
1 0 0 0 1 0 0 0 1
1 0 0 1 1 0 0 1 0
1 0 1 0 1 1 0 0 0
1 0 1 1 1 1 0 1 1
1 1 0 0 1 1 1 1 0
1 1 0 1 1 1 1 0 1 Fig. 5. RFT D_latch

1 1 1 0 1 0 1 1 1 3.2. RFT Master – Slave Flip – Flop (MS-FF)

1 1 1 1 1 0 1 0 0 The following fig: 6 represents the proposed “RFT-Master

slave FF” applying with 12-FRG, 2-F2G gate and
described 5-RFT D_latch, which generates the final output
Mubin_sworna_Babu (MSB) Gate: it’s Block-Diagram Q and Q+. and g1,g2,g3,g4 are the garbage outputs. The

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total quantum cost of this RFT MS-FF is 19. 3.4. RFT X-Input “LOOK-UP-TABLE” (LUT)
3.4.1. Three-Input “Look-up-Table”
The designed RFT-3_input “Look-up-Table” contains 20-
MSB gates and 9-FRG gate, and generates the garbage-
output and Omux final-output. The total quantum cost of
this RFT LUT is 164. Figure 8 shows the design of 3-input
LUT gate using MSB gates. Table 3 displays the truth table
for 3 – i/p LUT.
Fig. 6. Master Slave Flip Flop
3.3. RFT (4x1) – Multiplexer
For RFT (4x1)-mux design, we apply the proposed 8-MSB
Gate. This multiplexer produces the least amount of
garbage, which is proved in following theorem. The total
quantum cost of this RFT Multiplexer is 2.

Fig. 8. Three – input “LUT”

Omux =(a'b'c).(a'be).(ab'd).(abf)
Table 3. Truth Table of 3 – i/p LUT

a b Output
Fig. 7. 4x1 MUX
0 0 c
Figure 7 shows the design of RFT Multiplexer using MSB
gates. Table 2 shows the truth table of Truth Table “4x1 0 1 d
MUX. 1 0 e
Omux =a'b'c + a'be + ab'd + abf 1 1 f
Table 2. Truth Table “4x1 MUX”
3.5. Four – Input “Look Up table”
a b Output
In this we used “MSB” gates with four inputs and generate
0 0 c the G1, G2......G19 garbage values and Omux as output
0 1 d results. Figure 9 shows the design of 4-input LUT gate
using MSB gates. Truth table is displayed in table 4.
1 0 e
1 1 f

Theorem-1 : 4𝑥 − 𝑡𝑜 − 𝑥 “Reversible-fault-tolerant mux”

contains 4𝑥 + 1 garbage out-puts with no constant input
and 𝑥 => 𝑛𝑜. 𝑑𝑎𝑡𝑎 𝑏𝑖𝑡𝑠.
Lemma (i): The designed x-i/p “Reversible-fault-tolerant
D_latch” contains 𝑥 −Reversible-FT gates, 2𝑥 − Garbage-
outputs and 6𝑥 −Quantum_cost. Fig. 9. Four – input “Lookup table”
Lemma (ii): The x-input “Reversible-fault-tolerant Write
Enable Master_slave-Flip_Flop” contains at least 5𝑥-
Reversible-FT gates, 7𝑥-Garbage-outputs and 21𝑥 Qc.

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 Table 4. Truth table of 4 – i/p LUT programmable logics, provides functional elements, “I/O-
Blocks”: interface between internal signals and package
S3 S2 S1 S0 Output
pins.
0 0 0 0 I0 The “Configurable-Logic-Blocks” has two, Four-input-
0 0 0 1 I1 function-generators (F1, F2, F3, F4 and G1, G2, G3, G4)
and 3rd H-function-generator contains 3-inputs. Either (0,
0 0 1 0 I2
1, or 2) are the inputs and it will be the output of F & G.
0 0 1 1 I3 Every “CLBs” has 2-independent storage components,
which are used for storage of output function-generators.
0 1 0 0 I4
The 13-input-CLB and 4-output-CLB provide access to the
0 1 0 1 I5 storage-elements and function-generators. All these i/p and
0 1 1 0 I6 o/p are connected with programmable-interconnected-
resources outside the block. There are 4-independent i/p
0 1 1 1 I7 are available for each function-generators F1...F4 and
1 0 0 0 I8 G1...G4 and F’ & G’ are the outputs. The 3rd function -
generator H has H’ output label.
1 0 0 1 I9
1 0 1 0 I10
1 0 1 1 I11
1 1 0 0 I12
1 1 0 1 I13
1 1 1 0 I14
1 1 1 1 I15

3.6. RFT CLB for FPGA

The Reversible fault tolerant CLB of FPGA designed by
using Verilog and simulated by Modelsim. In this system
taken RFT- four- input - LUT from I/O block. And {S0,
S1, S2, S3} are the selector for selection of bits from the 3.7. Application of the Proposed FPGA to Design an n-
I/O-block. Used four-RFT_LUT, RFT-(2x1)-mux, and bit Adder Circuit
RFT-Flip-flops which generates the (Q1),(0 mux) and Q or We implemented a full adder circuit using the DSCH
(Q+) out-put results. Figure 10 shows the proposed RFT simulation tool and our implemented RFT CLB design, as
CLB of FPGA. seen in Figure 10, where Block 1 evaluates the sum (A ⊕
B ⊕ C) of three input bits (A, B, and C) and Block 2
evaluates the carry (AB + AC + BC). While our design has
complete adder logic, we have evaluated the delay and
power usage. This method is scalable and hence
generalizable to n-bit adders.

Fig. 10. “Reversible FT” CLB of FPGA Fig. 11. Design of a Full Adder
The proposed programmable-gate contains two-
configurable components: (CLBs and IOBs). 4. Results and Discussions
“Configurable-Logic-Blocks”: for designing This section simulates and analyses the performance of the

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proposed RFT MSB gate, MSH gate, and reversible fault
tolerant components of the LUT Logic Block.
The proposed components' simulations (RFT Master slave
FF, LUT, Multiplexer and D-Latchbased FPGA) are shown
in Figures 12 – 15.

Fig. 15. Simulation of the proposed RFT FPGA

In Figure 12, CLK denotes clock input, D denotes data
input, Q denotes the D-non-complementary Latch's output,
and Q+ denotes the negation of Q. Figure 12 illustrates that
Fig. 12. Simulation of the proposed RFT D-Latch when CLK=1, D becomes Q. Latch keeps previous state
when CLK=0.
Following is the simulation result of the FT MS-Flip-Flop,
where CLK represents the same as D-Latch notations. W
often stands for write. When W=1, Q fluctuates based on
CLK, much like D-Latch Q did previously.
According to the fusion of two selected bits (S1 and S0),
the output designated by Omux may be given to any of the
four inputs (C, D, E, and F), proving the accuracy of the
architecture depicted in Figure 14.
4.1. Performance Metrics
We use four indicators to evaluate reversible FPGA
Fig. 13. Simulation of the proposed RFT 4x1 Multiplexer performance. These measures are described briefly below:

• Gates: A circuit uses reversible gates. The total

number of gates will be obtained by adding together
all the gates. This is a reversible circuit metric. A
circuit with fewer essential gates is more efficient.
• Garbage outputs: The unused outputs of a circuit are
counted as garbage. We can get the total trash outputs
by adding up all the garbage outputs. The low
garbage output value shows the design's efficiency.

• Quantum Cost: It is a key performance parameter for

reversible circuits. This is the number of NOT,
Controlled-V +, and CNOT gates necessary to
Fig. 14. Simulation of the proposed RFT Master Slave implement it.
Flip flop • Delay: In reversible circuits, the critical path
reversible gates are replaced with quantum gates, and
the overall critical path delay defines the circuit
latency. Each 1×1 or 2×2 RG has a unit-delay and is
indicated by Δ.
4.2. Performance Analysis
Performance analysis of the different components of the

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LUT Logic Block is given in this section.
Table 5. Fault tolerant (FT) master Slave Flip flop Output comparison

Techniques No. of Gates Unit Delay Quantum Cost Garbage Output Transistors

Existing [3] 7 6 25 9 60
Existing [4] 5 5 21 7 38
Proposed 4 4 10 2 6

Table 6. FT 4x1 Multiplexer Output comparisons

Techniques No. of Gates Unit Delay Quantum Cost Garbage Output Transistors

Existing [3] 9 7 57 11 70
Existing [4] 1 1 12 5 12
Proposed 1 1 5 3 5

Table 7. FT D-latch Output comparison

Techniques No. of Gates Unit Delay Quantum Cost Garbage Output Transistors

Existing [3] 2 2 9 7 19
Existing [4] 1 1 6 4 10
Proposed 1 1 2 1 3

Table 8. 4 i/p LUT-FPGA Output comparison

Techniques No. of Gates Unit Delay Quantum Cost Garbage Output Transistors
Existing [3] 39 39 243 50 342
Existing [4] 5 5 60 19 60
Proposed 5 5 56 5 37

Table 9. Comparative analysis of CLB

Techniques No. of Gates Unit Delay Quantum Cost Garbage Output Transistors

Existing [3] 44 44 208 57 424

Existing [4] 18 18 170 57 192
Proposed 12 15 156 32 112

Tables 5–9 show that the suggested architecture performs 4.2.1. Garbage Outputs Comparison
better than existing designs in terms of gate count,
Figure 16 compares the proposed FPGA to existing FPGAs
transistor count, garbage output, latency, and quantum
in terms of garbage outputs. The above-mentioned (i), (ii),
cost.
and (iii) design techniques are presented in Figure 16(a)–
The FPGA structure is fixed by two variables n and m. For (c). Figure 16 indicates that the suggested approach
each of these ways, the overall results are displayed in outperforms existing efforts in all scenarios. In the final
comparison to the findings for the three approaches (i) two scenarios, existing designs rise exponentially, but the
Changing m without changing n (ii) Changing n while system design increases linearly with the number of inputs.
maintaining m. (iii) Changing m and n.

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 (a)
(a)

(b)
(b)

(c)
Fig. 16. Comparison of proposed with existing method on
the garbage outputs (a) Changing m without changing n (b) (c)
Changing n while maintaining m. (c) Changing m and n Fig. 17. Comparison of proposed with existing method on
4.2.2. Constant Inputs Comparison constant inputs (a) Changing m without changing n (b)
Changing n while maintaining m. (c) Changing m and n
Quantum circuits with multiple constant bits and reversible
4.2.3. Delay Comparison
gates are unmanageable. Constant input is therefore
regarded a substantial overhead that must be reduced. A logic circuit's delay is equal to the delay of the crucial
Figure 17(a)–(c) compares the proposed FPGA to existing circuit. However, finding all essential paths is an NP-
FPGAs in terms of necessary constant inputs for design complete task, especially for large circuits, or for large n or
methods I (ii), and (iii). The slope (growing rate) of all the m in the case of FPGAs. Thus, researchers utilised to
edges in Figure 17 is about equal, but the recommended choose the route that was most likely to include critical
design has the greatest performance. paths. The proposed circuit's delay is analyzed in terms of
the most likely critical pathways. Figure 18 compares the
implemented work to the existing work in terms of circuit
delay. According to Figure 18(a)-(c), the suggested design
outperforms the existing designs under all feasible
conditions.

International Journal of Intelligent Systems and Applications in Engineering IJISAE, 2024, 12(16s), 217–226 | 224
 Multiplexer 1.57 17
LUT-FPGA 1.23 14

All of the RFT mentioned above are implemented in a

90nm (Spartan -3 FPGA) device for the purpose of
analyzing the parameters listed in Table 9.

5. Conclusion
The reversible fault tolerant Configurable logic block
(a) (CLB) based FPGA are developed. The reversible CLB are
important building components of FPGA. Here we have
validated the functioning of RFT CLB which comprises 3
– input, 4 – input LUT, 4:1 Multiplexer, D – Latch and
Master slave Flip – flop. Our RFT CLB and its
components are improved in terms of Garbage outputs,
number of gates, Quantum cost and Number of transistors
with comparison to conventional approaches. The
described design employing the proposed reversible gate
provides reduced complexity of hardware and consumption
of power.
Acknowledgements
(b)
The authors would like to express their gratitude to B.G.S
Institute of Technology, Adichunchanagiri University,
B.G. Nagara, Mandya for all of their assistance and
encouragement in carrying out this research and publishing
this paper.
Author contributions
Ravi L.S is the principal author responsible for the study's
conception and design, overseeing experimental
procedures, conducting data analysis, and composing the
manuscript. He adeptly executed data acquisition and
(c) analysis, generated graphical representations, and made
Fig. 18. Comparison of proposed with existing method on substantial contributions to manuscript development. He
the critical path delay (a) Changing m without changing n was actively engaged in study design, offering invaluable
(b) Changing n while maintaining m. (c) Changing m and n insights during data interpretation, and precisely revising
the manuscript. Dr. Naveen K.B served as the Research
4.3. Additional Experiments supervisor, providing critical assessment of the manuscript.
To examine power consumption and delay, a comparison is Conflicts of interest
done between a RFT a LUT-FPGA, a RFT Multiplexer, a
RFT Master-Slave Flip-Flop and RFT D-Latch. According The authors declare no conflict of interest.
to the following table, the most recent technique
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