COA Course File 2023-24
COA Course File 2023-24
of
(BCS-302)
Session 2023-24
Submitted By:
Vision of Institute
Be known globally for value-added Education Innovation Research at the intersection of
disciplines in service of humankind.
Mission of Institute
Place a multidisciplinary engineering education ecosystem that transforms learners into
future innovators, entrepreneurs, and professional leaders.
Create an ambiance of interdisciplinary research, innovation, and creativity to address
regional and global challenges for benefit of human life and the environment.
Provide the environment for enhancing knowledge, and inculcating critical & Design
thinking, life skills through quality learning Systems.
Collaborate with globally renowned academic & research institutions and Corporate for
improving Productivity and economics.
CSE Department Vision and Mission
PEO4: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
Programme Outcomes
Progra Statement
m
Outcom
e
PO2 Problem analysis: Identify, formulate, review research literature, and analyze
complex computer engineering problems reaching substantiated conclusions
using first principles of mathematics, natural sciences, and engineering sciences.
PO5 Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to
complex engineering activities with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent relevant to the professional engineering practices.
PO8 Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norm of the engineering practices.
PO12 Life-long learning: Recognize the need for, and have the preparation and ability
to engage in independent and life learning in the broadest context of technological
change.
Programme Specific Outcomes (PSOs)
After completing their graduation, students of Computer Science and Engineering will be able
to do:
Programme
Specific
Statement
Outcomes
(PSO)
Comprehend the core subjects of CSE and apply them to resolve domain-
PSO1 specific tribulations.
Year: - Second
Semester: - 3rd
Section: - A&B
Course Description
This course covers the details about architecture & organization of a computer system in detail.
The main objective of this course is to introduce the major concept related to memory, I/O,
ALU, CU & Addressing modes etc. and how these concepts are organized in a computer
system.
Course Outcomes
At the end of course, the student will be able to understand:
CO1 Study of the basic structure and operation of a digital computer system
Analysis of the design of arithmetic & logic unit and understanding of the
CO2 fixed point and floating-point
arithmetic operations.
Course Code CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 2 1 - - - - - - - - - 1 2 -
BCS302 CO2 2 1 1 - - - - - - - - 1 2 -
CO3 2 1 1 - - - - - - - - 1 2 -
CO4 2 1 1 - - - - - - - - 1 2 -
CO5 2 1 1 - - - - - - - - 1 2 -
- - - -
Mapping Strength BCS302 2.0 1.0 1.0 - - - 1.0 2.0 -
CO-PO JUSTIFICATION
CO No PO CL Justification
2 Moderately matching as students will understand the fundamentals
PO1 of Computer Organization and apply the same to explain the
operation of computers.
1 Slightly matching as students can identifies the functionalities and
PO2 computing resources of computer systems.
CO1 1 Slightly matching as students can identify the deficiencies and
PO12 demonstrate the need of updating in the computer organization so
that operation of computers.
2 Moderately matching as students will understand the computer
PSO1 organization and operation of computers.
2 Moderately matching as students will understand the fundamentals
PO1 of arithmetic and logic unit and apply the same in designing the
arithmetic unit and logical unit.
1 Slightly matching as students able to identify the algorithms and
PO2 apply the same in designing arithmetic unit.
BCS302 BCS302
Tuesday
_2B _2A
BCS302 BCS302
Thursday
_2B _2A
BCS302 BCS302
Friday
_2A _2B
List of Students
B.Tech. (CSE) 2nd Year (A), ODD Sem, 2023-24
Course
Faculty
BCS302 Mr. Mohd Imran Ansari
Code Name
DATE
LECTUR DATE
DESCRIPTION *PEDAGOGY REMARK
E NO. (SCHEDULED)
(EXECUTED)
UNIT-I: (Introduction)
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4 Micro-operations, execution of a complete WHITE BOARD/PPT 09/10/2023
instruction.
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UNIT-IV: (Memory)
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UNIT-V: (Input/Output)
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Department of CSE
B.Tech. 2nd Year, III Sem
Session 2023-24 (Odd Semester)
Assignment-1
3 What are the different types of addressing modes? Explain each with an 2 1 K2
example.
4 Design and explain common bus system for four registers using 2 1 K2
Multiplexers.
Note: Use a Separate copy to write their answer. Avoid copying assignments
Department of CSE
B.Tech. 2nd Year, III Sem
Session 2023-24 (Odd Semester)
Assignment-2
3 Explain in detail the principal of carry-look ahead adder and design 4-bit 4 1 K4
CLA adder.
Note: Use a Separate copy to write their answer. Avoid copying assignments
Department of CSE
B.Tech. 2nd Year, III Sem
Session 2023-24 (Odd Semester)
Assignment-3
Note: Use a Separate copy to write their answer. Avoid copying assignments
Department of CSE
B.Tech. 2nd Year, III Sem
Session 2023-24 (Odd Semester)
Assignment-4
Device Type
a. Magnetic tape i. Input device
Random access Auxiliary Storage Device
b. ii.
memory (RAM) (Auxiliary Storage Device)
Internal storage (internal
c. Laser printer iii.
storage)
d. Light pen iv. Output device
2. A form of computer data storage that stores data and machine code and can be searched and changed
in any order:
1. Remote memory
2. Random access memory
3. Read only memory
4. Flash memory
1. ROM
2. RAM
3. CD
4. Hard Disk
5. ________ a high-speed device used in CPU 3. Static RAM
1. Virtual memory
2. Flash memory
3. Main memory
4. Cache memory
1. RAM
2. ROM
3. CPU
4. CD ROM
1. DDR
2. DRAM
3. SRAM
4. PRAM
1. Hard Disk
2. DVD ROMs
Department of CSE
B.Tech. 2nd Year, III Sem
Session 2023-24 (Odd Semester)
Assignment-5
8. If an exception is raised and the succeeding instructions are executed completely, then the processor is
said to have ______
a) Generation word
b) Exception handling
c) Imprecise exceptions
d) None of the mentioned
Note: Use a Separate copy to write their answer. Avoid copying assignments
1st CLASS TEST, SESSION 2023- 2024 (ODD SEM.)
COURSE- B.Tech.
DEPTT. – Computer Science & Engineering
YEAR: - 2nd YEAR (3rd SEM)
SUBJECT NAME: - Computer Organization and Architecture (BCS302)
TIME: 2 Hour MAX MARKS: 30
Note: Answer all questions. Draw neat sketch, wherever necessary. Suitably assume missing data, if any.
SECTION A
Question 1: Attempt all parts in brief. [1X5=5]
SECTION B
Question 2: Attempt any 05 out of the following. [3X5=15]
Draw a diagram of a Bus system in which it uses 3 state buffers and a decoder instead of
a. 3
the multiplexers. [CO1], K2
b. Represent (−25.15)10 in IEEE-754 single precision and double precision format. 3 [CO2], K3
c. Show the multiplication process using Booth’s Algorithm for (-7) X (+3). 3 [CO2], K4
d. What is system bus? Explain different types of bus lines for communication. 3 [CO1], K2
Write down the full forms of the following term:
e. 3
I. RAM II. ROM III. CPU [CO1], K1
Explain Half-Adder with the help of its circuit diagram.
f. 3
[CO2], K2
g. What is mean by bus arbitration? List different types of bus arbitration. 3 [CO1], K1
SECTION C
Question 3: Attempt any 02 out of the following. [5X2=10]
Write a program to evaluate arithmetic expression:
X = (A+B) * (C-D)
a. 5
E. Using a general register CPU with three address instructions.
F. Using a general register CPU with two address instructions. [CO1], K5
Draw the flow chart of Restoring division algorithm for binary numbers.
b. 5 [CO2], K4
c. Explain functional units of computer system in detail with proper block diagram. 5 [CO1], K2
Bloom’s Taxonomy:
K1 K2 K3 K4 K5 K6
Remember Understand Apply Analyze Evaluate Create
d. List various types of ROM memory available in the computer system. 1 [CO4], K1
SECTION B
Question 2: Attempt any 05 out of the following. [3X5=15]
f. Differentiate between RISC and CISC. 3 [CO3], K3
g. Explain linear and non-linear pipeline with suitable diagram. 3 [CO3], K2
h. Justify the concept of Pipelining using a suitable diagram in a computer system. 3 [CO3], K5
i. What is Belady’s anomaly? Justify with proper example. 3 [CO4], K4
j. List the difference between static RAM and dynamic RAM. 3 [CO4], K3
f. Explain the cache performance measures. 3 [CO4], KL4
A computer uses RAM chips of 1024*1 capacity.
g. I. How many chips are needed to provide a memory capacity of 16 KB? 3
II. What is the size of Decoder is required to implement above memory? [CO4], K6
SECTION C
Question 3: Attempt any 02 out of the following. [5X2=10]
Discuss the Memory Hierarchy in computer system with regard to Speed, Size and Cost,
a. 5 [CO4], K4
also draw the proper diagram.
Write a program to evaluate arithmetic expression:
X = ((A-B+C) * (A^B))/(C^D*E)
b. 5
G. Using a general register CPU with three address instructions.
H. Using a general register CPU with two address instructions. [CO3], K5
Calculate the number of page faults using optimal page replacement algorithm for the
c. reference string: 1,5,4,3,2,5,1,2,4,3,6,4. If the number of frames in the memory is 3 and 5
4 illustrating each step. [CO4], K5
Bloom’s Taxonomy:
K1 K2 K3 K4 K5 K6
Remember Understand Apply Analyze Evaluate Create
a. Give the detailed description of General Register Organization with sketch. 7 [CO1], K1, K2
b. Design a 4-bit Carry-Look ahead Adder and explain its operation with an example. 7 [CO2], K3
Section C
Q3. Attempt any one part of the following: [7X1=7]
a. Draw a diagram of bus system in which it uses 3 state buffers and a decoder instead 7 [CO1], K2,
of the multiplexers. K4
b. Explain functional units of computer system in detail. 7 [CO1], K1,
K2
Q4. Attempt any one part of the following: [7X1=7]
a. Multiply (-7*3) and (15*-6) using Booth algorithm. 7 [CO2], K3
b. Explain IEEE Standard for floating point representation. With the help of suitable example. 7 [CO2], K3
b. What are interrupts? How many types of Interrupts are there? List the sequence of 7 [CO5],
K2,K4
steps following an interrupt request.
Bloom’s Taxonomy:
K1 K2 K3 K4 K5 K6
Remember Understand Apply Analyze Evaluate Create
Question Bank
9 Define locality of reference. Also explain Spatial & Temporal locality of reference.
11 Describe the working of micro program sequencer with a suitable diagram and tables.
12 Discuss the memory hierarchy in computer system with regard to speed, size and cost.
13 Draw a flowchart for instruction cycle with neat diagram and explain.
14 List the differences between hardwired and micro programmed control in tabular format. Write
the sequence of control steps for the following instruction for single bus architecture.
R1 <- R2 * (R3)
i) How many chips are needed & how should their address lines be
connected to provide a memory capacity of 1024*8?
ii) How many chips are needed to provide a memory capacity of 16KB?
i ) Calculate the number of page faults using optimal page replacement algorithm
for the reference string: 1,5,4,3,2,5,1,2,4,3,6,4 if the number of frames in the memory is 3 and 4
illustrating each step.
ii)Calculate the page fault for a given string with the help of LRU & FIFO page replacement
algorithm, Size of frames 4 and string 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
17 There is an instruction pipeline with four stages. The stage delays for each stage are 5 nsec,
6 nsec, 11 nsec, and 8 nsec. Determine the approximate speedup of the pipeline in the steady
state under ideal conditions as compared to the corresponding non-pipelined implementation?
19 Differentiate between hardwired and micro programmed control unit. Explain each component
of hardwired of hardwired control unit organization.
i) Give the block diagram of DMA controller. Why are the read and write control
lines in a DMA controller bidirectional?
21 Differentiate between hardwired and micro programmed control unit. Explain each
component of hardwired control unit organization
By using (i) Two address instructions (ii) One address instructions (iii) Zero address
Impact observed
The students found peer tutoring to be very helpful, and as a result, they felt more
comfortable with the Unit-1 topics.
Impact observed
They completed technical training courses.
Direct Assessment
(80%) Indirect
Overall
S.No CO Internal External Assessment
Attainment
Assessment assessment (20%)
(20%) (80%)
1 CO1 1 1 3 1.4
2 CO2 1 1 3 1.4
3 CO3 1 1 3 1.4
4 CO4 2 1 3 1.56
5 CO5 1 1 3 1.4
Assignment
Course Exit Survey
Lecture Notes