How to Design a Finite State Machine?

Step-by-Step Guide

Finite State Machines (FSMs) are essential components in digital circuit design, enabling the
creation of sequential logic systems. In this guide, we will explore the process of designing a Finite
State Machine by taking the example of a sequence detector. Specifically, we will focus on the
steps involved and the different types of sequence detectors. Let's dive in!

Steps for Designing the Finite State Machine.

Step-1: Define the Purpose and Input/Outputs
To design an FSM, start by defining the purpose of the machine in simple terms or as a block
diagram. Understand how the machine operates and determine its inputs and outputs. Ensure
that the machine can be realized using a finite number of memory elements.

Step-2: Draw the State Diagram

Once you have a clear understanding of the machine's purpose and inputs/outputs, proceed to
draw a state diagram. The state diagram represents the various states of the machine and the
transitions between them. Each state is represented by a circle, and the transitions are
represented by arrows.

Step-3: Create the State Table

From the state diagram, create a state table. The state table lists all the states, inputs, and
outputs of the machine. It serves as a reference for designing the logic circuitry later in the
process.

Step-4: Check the redundant States

Review the state diagram and state table to identify any redundant states. Redundant states
are states that do not contribute to the overall functionality of the machine. If any redundant
states are found, remove them from the state diagram and update the state table accordingly.
Step-5: Select the type of Flip-Flop

Choose the type of flip-flop (D, JK, or SR) that will be used in the circuit. The selection depends
on the specific requirements of the design. Each flip-flop has its own excitation table, which
provides the necessary inputs for the flip-flop to transition to the desired state.

Step 6: Derive the Boolean Functions

Determine the Boolean functions for the flip-flops and outputs based on the state variables and
inputs. Simplify the Boolean expressions using techniques such as Karnaugh maps or Boolean
algebra. These Boolean functions will be used to design the logic circuitry.

Step 7: Design the Logic Circuit

With the derived Boolean functions, design the logic circuit for the FSM. Use logic gates (AND,
OR, NOT) and flip-flops to implement the desired functionality. Connect the inputs, outputs, and
flip-flop inputs according to the state table and Boolean expressions.

Let’s understand the Finite State Design procedure through an example of the Sequence
Detector.

What is Sequence Detector? Overlapping and Non-Overlapping Sequence

Detector

These digital circuits detect specific bit sequences in received incoming bits. There are two types
of sequence detectors: overlapping and non-overlapping.

In an overlapping sequence detector, the last few bits of a sequence can also be the first few bits
of the next sequence. On the other hand, a non-overlapping sequence detector resets after
detecting a sequence and starts searching for a new sequence.

For example, if the following input bit-stream is applied to 1001 overlapping sequence detector,
then this is how its output will look like.
 Fig. The output of the overlapping sequence detector

Input - 100100100100111011

Output- 000100100100100000

As, you can see, the output of the detector goes high 4 times. But if the same input bit-stream
is applied to the non-overlapping sequence detector then it will go high for only two time. And
this is how its output will look like.

Input - 100100100100111011

Output- 000100000100000000

To design these sequence detectors, we follow similar steps as with any Finite State Machine.
We start by drawing the state transition diagram, which represents the different states and
transitions based on inputs. From the diagram, a state table can be derived, providing a
structured overview of the states, inputs, and outputs.
Next, the type of flip-flop is selected, and the required excitations for each flip-flop are
determined. Boolean expressions for the inputs of the flip-flops and the output are derived from
the state table and simplified if possible. Based on these Boolean expressions, the final logic
circuit for the sequence detector can be drawn. The circuit includes the flip-flops, inputs, and
outputs, enabling the detection of the specified bit sequence.

Design of 1001 Overlapping Sequence Detector (Mealy Machine)

Step-1: Find the Input/Outputs of the machine and determine the required
number of states.

The detector will have 1-input and output and it will have total 4 different states. The four
different states are mentioned below in the table.

In general, in the Mealy Sequence Detectors, the number of states in the sequence detector is
same as the number of bits in the sequence.

Step-2: Draw a State Transition Diagram

The state transition diagram of the 1001 sequence detector (overlapping ) is shown below.
 Fig. State Transition Diagram of 1001 Mealy Sequence Detector (Overlapping)

Step-3: Draw a State Table

For the above state transition diagram, the state transition table is shown below.

Step-4: State Reduction and State Assignment

In the above state table, there is no redundant states. And here, we are going to use the
following state assignment.

A – 00, B – 01, C - 10, D – 11

With this state assignment, the modified state table is represented below. Here, the inputs are
represented in the different column. And the variables for the states are assigned as Q1 and Q0.
The Q1 and Q0 represents the preset state, while Q1+ and Q0+ represents the next state.
 Fig. The modified State Table of Overlapping Sequence Detector (1001)

Step-5: Select the type of Flip-Flop and Draw the Excitation Table

For our design, let’s use D flip-Flops. Since, we require two bits for state representation, we
need two D flip-flops. For the D flip-flops, the output is same as the input. Therefore, the input
to the D flip-flops, is same as the required next state.

The excitation table is shown below.

Step-6: Derive the Boolean Functions

From the excitation table, determine the Boolean functions for the flip-flops and outputs based
on the state variables and inputs. Simplify the Boolean expressions using techniques such as
Karnaugh maps or Boolean algebra. These Boolean functions will be used to design the logic
circuitry.

As shown above, the expression of D1, in terms of X, Q1 and Q0 is determined.

Similarly, the expression of D0 in terms of X, Q1 and Q0 is evaluated. And the Boolean

expression is simplified using the K-map.
And similarly, the expression of the output Y is determined.

Step 7: Design the Logic Circuit

Based on the derived Boolean expression, the logic circuit of 1001 overlapping sequence
detector is shown below.

Similarly, by following the same design steps, let’s design the 1001 non-overlapping sequence
detector.
Design of 1001 Non-overlapping Sequence Detector (Mealy Machine)

The design of non-overlapping sequence detector is similar to the overlapping sequence

detector. The only difference is that, once the sequence is detected, the detector gets reset and
goes to the starting state. And it starts searching for the new sequence.

Step-1 & 2: Find the inputs/ Outputs and the required number of states of the
machine, and draw a State Diagram

The state transition diagram of both overlapping and non-overlapping sequence detector is
shown side by side. In the overlapping sequence detector, once the sequence is detected, then
detector goes to B state. (To utilize the last received 1 for the new sequence), while in the non-
overlapping detector, it goes to the starting state A.

Step - 3: Draw a State Table

Based on the state diagram of the non-overlapping sequence detector, the state table is shown
below.
 Fig. State Table of 1001 Non-overlapping Sequence Detector

Step-4: State Reduction and State Assignment

In the above state table, there is no redundant states. And here, we are going to use the
following state assignment.

A – 00, B – 01, C - 10, D – 11

With this state assignment, the modified state table is represented below. Here, the inputs are
represented in the different column. And the variables for the states are assigned as Q1 and Q0.
The Q1 and Q0 represents the preset state, while Q1+ and Q0+ represents the next state.

Fig. Modified State Table of 1001 Non-Overlapping Sequence Detector

Step-5: Select the type of Flip-Flop and Draw the Excitation Table

For our design, let’s use D flip-Flops. Since, we require two bits for state representation, we
need two D flip-flops. For the D flip-flops, the output is same as the input. Therefore, the input
to the D flip-flops, is same as the required next state.

The excitation table is shown below.

Fig. The excitation table of 1001 Non-Overlapping Sequence Detector

Step-6: Derive the Boolean Functions

From the excitation table, determine the Boolean functions for the flip-flops and outputs based
on the state variables and inputs. Simplify the Boolean expressions using techniques such as
Karnaugh maps or Boolean algebra. These Boolean functions will be used to design the logic
circuitry.

From the excitation table, the Boolean expression of D1, D0 and output Y is derived in terms of
the present states Q1, Q0 and the input X. The derived Boolean expressions are simplified using
the K-map.
Boolean expression of D1, in terms of X, Q1 and Q0 is shown below.

Similarly, the Boolean expression of D0, in terms of X, Q1 and Q0 is shown below.

And likewise, the Boolean expression of output Y, in terms of X, Q1 and Q0 is derived. The
output Y is 1, when both Q1, Q0 and X inputs are 1.
Step 7: Design the Logic Circuit
Based on the derived Boolean expression, the logic circuit of 1001 non-overlapping sequence
detector is shown below.
In conclusion, designing a Finite State Machine, such as a sequence detector, involves a
systematic approach that includes defining the purpose, creating a state diagram, deriving a state
table, selecting flip-flops, finding excitations, and drawing the logic circuit. By following these
steps, one can successfully design FSMs for a wide range of applications in digital circuit design.