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HDL and FPGA Ch05 HVT 2024 RTL Combinational Circuits

The document discusses HDL design of combinational circuits at the register transfer level using Verilog. It covers Verilog operators, always blocks, if and case statements, and provides examples of combinational circuit designs including decoders, adders, and barrel shifters.

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Vy Tung
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53 views44 pages

HDL and FPGA Ch05 HVT 2024 RTL Combinational Circuits

The document discusses HDL design of combinational circuits at the register transfer level using Verilog. It covers Verilog operators, always blocks, if and case statements, and provides examples of combinational circuit designs including decoders, adders, and barrel shifters.

Uploaded by

Vy Tung
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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HDL & FPGA

Lecture 5. Register Transfer Level


Combinational Circuit
Huỳnh Việt Thắng
Faculty of Electronics & Telecommunication Engineering
Danang University of Science and Technology
[email protected]

Jun 2023
Introduction
• We examine HDL design of intermediate-size components: adder,
comparator, multiplexer, etc.
• We discuss more sophisticated Verilog operators, the always
block, and routing constructs, and then demonstrate the RTL
combinational circuit design
Contents
• Verilog Operators
• Always Block for a combinational circuit
• If Statement
• Case Statement
• Routing Structure of Conditional Control
Constructs
• General Coding Guidelines for an Always Block
• Parameter and Constant
• Design Examples
Verilog Operators
Verilog Operators
Notes on Verilog operators
Notes on Verilog operators
Notes on Verilog operators
Notes on Verilog operators
Notes on Verilog operators
Procedural statements
• For system modeling, Verilog contains procedural statements, which are
executed in sequence. These statements are encapsulated inside an always
block or initial block.
• The initial block is executed once when the simulation is started. It can
be used in simulation (testbench)
• Only the always block can be synthesized. Abstract procedural statement
→ known as behavioral description
• An always block can be thought of as a black box whose behavior is
described by the internal procedural statements.
• Procedural statements include a rich variety of constructs but many of
them don't have clear hardware counterparts. A poorly coded always
block frequently leads to unnecessarily complex implementation or
cannot be synthesized at all.
Procedural statements
• Three types of statements are discussed in this
section:
– Blocking procedural assignment
– If statement
– Case statement
always block
Blocking & Non-Blocking Assignments
Variable data types
Example 1
• 1-bit comparator
Example 2
Incorrect description
if statement
Example 3. Priority Encoder
Example 4. Binary Decoder
case statement
A case statement is a multiway
decision statement that compares the
[case-expr] expression with a number
of [item] expressions. The execution
jumps to the branch whose [item]
matches the current value of [case-
expr].

If there are multiple matched [item]


expressions, execution jumps to the
branch of the first match. The last item
can be an optional default keyword. It
covers all the unspecified values of the
[case-expr] expression.

The begin and end delimiters can be


omitted if there is only one procedural
statement in a branch.
Example 5. Binary decoder with case statement
Example 6. Priority Encoder with case statement
The casez and casex statements
Routing structure of conditional control constructs
• We examine several conditional control language constructs, including
the ? : operator and the if and case statements.
• In the C language, these constructs are executed sequentially.

• There is no "sequential" control in a combinational circuit. These


constructs are realized by routing networks. All expressions are
concurrently evaluated, and the routing network routes the
desired result to the output.

• Two types of routing structures: priority routing network and


multiplexing network, which are inferred by an if-else type
statement and a parallel case statement, respectively.
Priority routing network
• An if-else statement implies a priority routing network.

The conditional operator (?:) is like a simplified if-else statement and infers similar priority routing networks.
The number of cascading stages increases proportionally to the number of if-else clauses. A large number
of if-else clauses will lead to a long cascading chain and introduce a large propagation delay.
Multiplexing network
Coding guidelines for always block
• Verilog is for both modeling and synthesis.
• While writing code for synthesis, we need to be aware
of how the various language constructs are mapped to
hardware.
• This is especially true for an always block since variables
and procedural statements can be used within the block.
• We should remember that the purpose of the code is to
infer hardware rather than describing a sequential
algorithm in C.
• Failing to do so frequently leads to unsynthesizable
codes, unnecessarily complex implementation, or
discrepancy between simulation and synthesis.
• In this section, we review some common errors and
suggest a collection of coding guidelines.
Common errors in combinational circuit codes
1. Variable assigned in multiple always blocks
2. Incomplete sensitivity list
3. Incomplete branch and incomplete output
assignment
Variable assigned in multiple always blocks
Incomplete sensitivity list

In Verilog-2001, a special notation, @*, is introduced to implicitly include all the


relevant input signals and thus eliminates this problem.
lncomplete branch and incomplete output assignment
• We should observe the following rules while developing
code for combinational circuit:
– Include all the branches of an if or case statement.
– Assign a value to every output signal in every branch.

The above segment violates both rules!


Fix the errors
Error with case statement
The 2’b01 value is not covered by any branch.
If s assumes this combination, y will keep its
previous value and an unintended latch is
inferred.
To fix the error, we must ensure that y is
assigned a value all the time.
Guidelines for always block
Constant
Parameter
Parameter (cont.)
Parameter (cont.)
Design examples
• Hexadecimal digit to seven-segment LED decoder
• Sign-magnitude adder
• Barrel shifter
• Simplified floating-point adder

[Read section 3.9, page 67]

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