CHAPTER TWO

BASIC ARCHITECTURE OF THE 8088 AND 8086

MICROPROCESSORS

1/27/2024 1
Learning Objectives
After completing this chapter, the learners should be able to:
✓Internal architecture of the 8086/8088 microprocessors.
✓Pointer and index register
✓Status and flag register
✓Memory address space and data organization
✓Data types
✓Segment registers and memory segmentation
✓The Stack

1/27/2024 2
Introduction to 8086 Microprocessor

❖The 8086 Microprocessor is an enhanced version of the 8085 Microprocessor, it

was developed to overcome the drawbacks of the 8085 Microprocessor in 1976.

❖It is a 16-bit-based Microprocessor that has 20 address lines and 16 data lines.

❖The 8086 Microprocessor supports both operation modes.

❖The maximum operation mode is useful for systems which have multiple
processors and the minimum operation mode is useful for the systems which have
a single processor.

1/27/2024 3
 Features of 8086 Microprocessor
The most important features of 8086 microprocessors are as follows -
➢ The 8086 microprocessor is a 16-bit microprocessor. What this means is that the ALU and the
internal registers work with 16 bit of binary data at a time.

➢ It has 16 bits of the data bus. Because of this, the 8086 can read or write either 16 bit or 8 bit
of data at a time.

➢ The 8086 microprocessor has 20 bits of address lines that can access 220 address locations.

➢ Each memory location is a byte-addressable memory location.

➢ So the maximum value of address that can be addressed by 8086 is 2^20 = 1MB. So 8086 can
address the locations ranging between 00000 H to FFFFF H.

➢ This 1MB memory is divided into 16 logical segments, each with a memory of 64KB.

1/27/2024 4
Features of 8086 Microprocessor
➢The instruction queue of the 8086 microprocessor is of 6 bytes of length.
Therefore, the 8086 microprocessor can pre-fetch up to 6 instructions from the
memory and queue them in order to speed up the instruction execution.

➢The 8086 microprocessor can perform only fixed-point arithmetic instructions. It

means that the floating-point operations cannot be performed by it.

➢This is a drawback of the 8086 which was later eliminated in the further series of
Intel processors.

1/27/2024 5
 Internal architecture of the 8086 microprocessors.

1/27/2024 6
 Components of 8086 Microprocessor
The following are the components of an 8086 microprocessor:
The 8086 microprocessor consists of two main blocks:
➢ Bus Interface Unit (BIU)
➢ Execution Unit (EU)
The Bus Interface Unit (BIU) consists of the following components:
➢ Instruction Queue
➢ Segment Registers
➢ Instruction Pointer (IP)
The Execution Unit (EU) consists the following:
➢ Arithmetic Logic Unit (ALU)
➢ Control Unit
➢ General Purpose registers
➢ Index registers and pointers (except IP)
➢ Flags
1/27/2024 7
1/27/2024 8
 8086 HAS PIPELINING ARCHITECTURE
✓While the EU is decoding an instruction or executing an instruction, which does
not require use of the buses, the BIU fetches up to six instruction bytes

✓The BIU stores these pre-fetched bytes in a first-in-first-out register set called a
queue.

✓ When the EU is ready for its next instruction from the queue in the BIU. This is
much faster than sending out an address to the system memory and waiting for
memory to send back the next instruction byte or bytes.

✓Fetching the next instruction while the current instruction executes is called
pipelining.

1/27/2024 9
1/27/2024 10
1/27/2024 11
 6 Byte Pre-fetch Queue
✓It is a 6-byte queue (FIFO).
✓The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that
can have in 8086 is 6 bytes.
✓Hence to cover up all operands and data fields of maximum size instruction in 8086
Microprocessor there is a Pre-Fetch queue is 6 Bytes.
✓The pre-Fetch queue is connected with the control unit which is responsible for
decoding op-code and operands and telling the execution unit what to do with the help
of timing and control signals.
✓The pre-Fetch queue is responsible for pipelining and because of that 8086
microprocessor is called fetch, decode, execute type microprocessor.
1/27/2024 12
1/27/2024 13
✓The execution unit of the 8086 tells the BIU where to fetch instructions or data from,
decodes instructions, and executes instructions.
✓ The EU contains control circuitry, which directs internal operations.
✓ A decoder in the EU translates instructions fetched from memory into a series of
actions, which the EU carries out.
✓The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract, AND, OR,
XOR, increment, decrement, complement or shift binary numbers.
• The main functions of EU are:
• Steps
✓ EU extracts instructions from top of queue in BIU
✓ Decode the instructions
✓ Generates operands if necessary
✓ Passes operands to BIU & requests it to perform read or write bus cycles to memory
or I/O
✓ Perform the operation specified by the instruction on operands
1/27/2024 14
1/27/2024 15
General Data Registers
1. AX: This is the accumulator.
✓It is generally used for arithmetical and logical instructions but in 8086
microprocessor it is not mandatory to have an accumulator as the destination
operand.
✓It is of 16 bits and is divided into two 8-bit registers AH and AL to also perform 8-
bit instructions.
2. BX: This is the base register.
✓It is of 16 bits and is divided into two 8-bit registers BH and BL to also perform 8-
bit instructions.
✓It is used to store the value of the offset.

1/27/2024 16
3. CX: This is the counter register.

✓It is of 16 bits and is divided into two 8-bit registers CH and CL to

also perform 8-bit instructions.

✓It is used in looping and rotation.

4. DX: This is the data register.

✓ It is of 16 bits and is divided into two 8-bit registers DH and DL to

also perform 8-bit instructions.

✓It is used in the multiplication and input/output port addressing.

1/27/2024 17
Segment Registers
❖In order to increase execution speed and fetching speed, 8086
segments the memory.

❖The 8086 architecture uses the concept of segmented memory.

❖8086 able to address a memory capacity of 1megabyte and it is

byte organized.

❖Its 20-bit address bus can address 1MB of memory.

❖This 1MB memory is divided into 16 logical segments, each with a

memory of 64KB.
1/27/2024 18
 Segment Registers
There are 4 segment registers. They are:

❖ Code Segment Register(CS)

❖ Data Segment Register(DS)

❖ Extra Segment Register(ES)

❖ Stack Segment Register(SS)

1/27/2024 19
8086 works only with four 64KB segments within the whole 1MB
memory.
❖Code segment register (CS): is used for addressing memory location
in the code segment of the memory, where the executable program is
stored.
❖Data segment register (DS): points to the data segment of the
memory where the data is stored.
❖Extra Segment Register (ES) : also refers to a segment in the
memory which is another data segment in the memory.
❖Stack Segment Register (SS): is used for addressing stack segment
of the memory. The stack segment is that segment of memory which is
used to store stack data.
1/27/2024 20
❖ While addressing any location in the memory, the physical address is
calculated from two parts:

❖The first is segment address, the segment registers contain 16-bit segment
base addresses, related to different segment.

❖The second part is the offset value in that segment.

1/27/2024 21
 Pointers and Index Registers:
❖The index and pointer registers are given below:
✓Instruction pointer (IP)
✓BP—Base pointer
✓ SP—Stack pointer
✓ SI—Source index
✓ DI—Destination index
❖The pointer registers contain offset within the particular segments.
o The pointer register IP contains offset within the code segment.

o The pointer register BP contains offset within the data segment.

o The pointer register SP contains offset within the stack segment.

1/27/2024 22
❖The index registers are used as general purpose registers as well as
for offset storage in case of indexed, base indexed and relative base
indexed addressing modes.
✓ The register SI is used to store the offset of source data in data
segment.
✓The register DI is used to store the offset of destination in data or
extra segment.

❖The index registers are particularly useful for string manipulation.

1/27/2024 23
1/27/2024 24
 Instruction Pointer (IP)
✓It is a 16-bit register. It holds offset of the next instructions in
the Code Segment. IP is incremented after every instruction byte is
fetched.
✓IP gets a new value whenever a branch instruction occurs.
✓The address of the next instruction is calculated by using the formula
CS x 10H + IP.
Example:
CS = 4321H
IP = 1000H
then CS x 10H = 43210H + offset = 44210H
Here Offset = Instruction Pointer(IP)

1/27/2024 25
1/27/2024 26
Example
• The value of Code Segment (CS) Register is 4042H and the value of offset is
0580H.
Calculate the effective address of the memory location pointed by the CS
register.
Answer
• The offset of the CS Register is the IP register.
• Therefore, the effective address of the memory location pointed by the CS
register is calculated as follows:
• Effective address= Base address of CS register X 10H + Address of IP
= 4042H X 10H + 0580H

= (40420 + 0580)H

= 41000H
1/27/2024 27
• Calculate the effective address for the following register:
SS: 3860H, SP: 1735H

• SP is the offset for Stack Register (SS).

Therefore, the effective address for SS

(SS X 10H) + SP = 3640H X 10H + 1735H
= 36400H + 1735H
= 38135H

1/27/2024 28
 8086 flag register and its functions
✓ The 8086 flag register contents indicate
the results of computation in the ALU.
✓ It also contains some flag bits to control
the CPU operations.
✓ A 16 bit flag register is used in 8086. It is
divided into two parts . Condition code or
status flags and Machine control flags.
✓ The conditional code flag register is the
lower byte of the 16-bit flag register.
✓ The condition code flag register is identical
to 8085 flag register, with an additional
overflow flag.
✓ The control flag register is the higher byte
of the flag register. It contains three flags
namely direction flag (D), interrupt flag (I)
and trap flag (T).
1/27/2024 29
The description of each flag bit is as follows:
▪ CF- Carry Flag: This flag is set, when there is a carry out of
MSB in case of addition or a borrow in case of subtraction.
▪ Example addition of two numbers 35H and F2H

1/27/2024 30
Auxiliary Carry Flag (AF) is one of the six status flags in the 8086 microprocessor.
❑ This flag is used in BCD (Binary-coded Decimal) operations.
❑ The status of this flag is updated for every arithmetic or logical operation performed by ALU.
❑ This flag is set to one if there is a CARRY from the lower nibble or BORROW for the lower nibble in binary
representation.
❑ Else it is set to zero.
❑ Note : Auxiliary Carry Flag is to set to one when there is a carry from the units place in hexadecimal
representation. Same as the lower nibble in binary representation. Addition of 39H and 5AH

1/27/2024 31
 ▪ SF- Sign Flag: This flag is set, when the result of any computation is
negative. For signed computations the sign flag equals the MSB of the result.
▪ ZF- Zero Flag: This flag is set, if the result of the computation or comparison
performed by the previous instruction is zero.
▪ PF- Parity Flag: This flag is set to 1, if the result contains even number of 1’s.
▪ OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of
a signed operation is large enough to accommodate in a destination register.

1/27/2024 32
1/27/2024 33
▪ TF- Tarp Flag: If this flag is set, the processor enters the single step
execution mode. The processor executes the current instruction and the
control is transferred to the Trap interrupt service routine.
▪ IF- Interrupt Flag: If this flag is set, the mask able interrupts are recognized
by the CPU, otherwise they are ignored.
▪ D- Direction Flag: This is used by string manipulation instructions.
▪ If this flag bit is ‘0’, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode. Otherwise, the
string is processed from the highest address towards the lowest address, i.e.,
auto decrementing mode.
1/27/2024 34
The 8086 microprocessor uses three different buses to transfer data and
instructions between the microprocessor and other components in a computer
system.
These buses are:
1.Address Bus: The address bus is used to send the memory address of the
instruction or data being read or written. The address bus is 16 bits wide, allowing
the 8086 to address up to 64 kilobytes of memory.
2.Data Bus: The data bus is used to transfer data between the microprocessor and
memory. The data bus is 16 bits wide, allowing the 8086 to transfer 16-bit data
words at a time.
3.Control Bus: The control bus is used to transfer control signals between the
microprocessor and other components in the computer system.
The control bus is used to send signals such as read, write, and interrupt requests,
and to transfer status information between the microprocessor and other
components.
1/27/2024 35
1/27/2024 36
The description of the pins of 8086 is as follows:
❑AD0-AD15 (Address Data Bus): Bidirectional address/data lines.
These are low order address bus. They are multiplexed with data.
❑When these lines are used to transmit memory address, the symbol A
is used instead of AD, for example, A0- A15.
❑A16 - A19 (Output): High order address lines. These are multiplexed
with status signals.
❑A16/S3, A17/S4: A16 and A17 are multiplexed with segment
identifier signals S3 and S4.
❑A18/S5: A18 is multiplexed with interrupt status S5.
❑A19/S6: A19 is multiplexed with status signal S6.

1/27/2024 37
The description of the pins of 8086 is as follows:
❑BHE/S7 (Output): Bus High Enable/Status. It enables the data onto the most
significant half of data bus, D8-D15. 8-bit device connected to upper half of the data
bus use BHE signal. It is multiplexed with status signal S7.
❑RD (Read): For read operation. It is an output signal.
❑Ready (Input): The addressed memory or I/O sends acknowledgment through this
pin. When HIGH, it denotes that the peripheral is ready to transfer data.
❑RESET (Input): System reset. The signal is active HIGH.
❑CLK (input): Clock 5, 8 or 10 MHz.
❑INTR: Interrupt Request.
❑NMI (Input): Non-maskable interrupt request.
❑TEST (Input): Wait for test control. When LOW the microprocessor continues
execution otherwise waits.
❑VCC: Power supply +5V dc.
❑GND: Ground.
1/27/2024 38
• HOLD
• This is a control signal sent by the connected external peripheral
device to acquire the microprocessor buses.
• What this means is that is an external device like the input and output
devices are connected to the 8086 microprocessor and they require
the control over the buses, then a HOLD signal is sent by that device
at this pin.
• HLDA
• After the control of buses is transferred to the external peripheral
device, then an acknowledgment signal is sent for the same through
this pin.
• WR'
• This signal is used for writing purpose.

1/27/2024 39
✓M / IO'
✓This pin tells whether the operation is performed in the memory or
through the IO devices. If this pin is 1, then the operations are performed
in memory, else in the IO devices.
✓DT / R'
✓This signal tells whether the data is transferred or received. The
microprocessor transfers the data when the pin is at 1, and at 0, it receives
data.
✓DEN'
✓DEN stands for Data Enable. This pin is used to activate a chip in case of
multiple chips. It is an active low signal.
✓ALE
✓This pin is used to Latch address from multiplexed bus to temporary
storage in the 8086 microprocessor. If this pin is set to high, then the AD0
to AD15 pins will carry address, else they will carry data in them.
✓INTA
✓INTA stands for interrupt acknowledgment. If an interrupt request is
received at INTR, then the acknowledgment for it is sent through this pin.
1/27/2024 40
Operating Modes of 8086
• There are two operating modes of operation for Intel 8086, namely
the minimum mode and the maximum mode.
• When only one 8086 CPU is to be used in a microprocessor system,
the 8086 is used in the Minimum mode of operation.
• In a multiprocessor system 8086 operates in the Maximum mode.

1/27/2024 41
Maximum Mode:
✓The Maximum Mode of the 8086 microprocessor is supposed for use
in structures where the processor is the significant element and has full
control over the device bus.

✓ In this mode, the microprocessor acts because of the bus controller

and interacts without delay with other gadgets together with memory,
I/O ports, and co-processors.

1/27/2024 42
1/27/2024 43
Minimum Mode:
➢The Minimum Mode of the 8086 microprocessor is designed for
systems wherein the processor shares the gadget bus with different
devices and does not act as the bus controller.

➢This mode is commonly utilized in single-processor systems or while

the device calls for fewer assets and a much less complex
configuration.

1/27/2024 44
1/27/2024 45
Memory Segmentation:
✓ The memory in an 8086 based system is organized as segmented memory.
✓ The CPU 8086 is able to access 1MB of physical memory. The complete 1MB
of memory can be divided into 16
✓ segments, each of 64KB size and is addressed by one of the segment register.
✓ The 16-bit contents of the segment register actually point to the starting location
of a particular segment.
✓ The address of the segments may be assigned as 0000H to F000h respectively.
✓ To address a specific memory location within a segment, we need an offset
address.
✓ The offset address values are from 0000H to FFFFH so that the physical
addresses range from 00000H to FFFFFH.
1/27/2024 46
1/27/2024 47
1/27/2024 48