UNIT-III SEQUENTIAL MOS LOGIC CIRCUITS

Behavior of Bistable Elements:

Two identical cross coupled inverter circuits are shown in Figure. Here, the output
voltage of inverter (1) is equal to the input voltage of inverter (2), i.e., Vo1. = Vi2, and the
output voltage of inverter (2) is equal to the input voltage of inverter (1), i.e., Vo2 = Vi1.

The two voltage transfer characteristics intersect at three points. Two of these
operating points are stable, as indicated in Figure. If the circuit is initially operating at one of
these two stable points, it will preserve this state unless it is forced externally to change its
operating point. Note that the gain of each inverter circuit, i.e., the slope of the respective
voltage transfer curves, is smaller than unity at the two stable operating points. Thus, in order
to change the state by moving the operating point from one stable point to the other, a
sufficiently large external voltage perturbation must be applied so that the voltage gain of the
inverter loop becomes larger than unity.
On the other hand, the voltage gains of both inverters are larger than unity at the third
operating point. Consequently, even if the circuit is biased at this point initially, a small
voltage perturbation at the input of any of the inverters will be amplified, causing the
operating point to move to one of the stable operating points. This leads to the conclusion that
the third operating point is unstable. The circuit has two stable operating points, hence, it is
called bistable.
The bistable behavior of the cross-coupled inverter circuit can also be visualized
qualitatively by examining the total potential energy level at each of the three possible
operating points as shown in Figure. It is seen that the potential energy is at its minimum at
two of the three operating points, since the voltage gains of both inverters are equal to zero.
By contrast, the energy attains a maximum at the operating point at which the voltage gains
of both inverters are maximum. Thus, the circuit has two stable operating points
corresponding to the two energy minima, and one unstable operating point corresponding to
the potential energy maximum.
Analysis of Bistable Circuit:
Consider the bistable circuit shown in Figure, which is initially operating at Vo1 = Vo2 = Vth,
i.e., at the unstable operating point. For analysis, assume that the input (gate) capacitance Cg
of each inverter is much larger than its output (drain) capacitance Cd, i.e., Cg>> Cd.

The small-signal drain current supplied by each inverter (1 and 2) can be expressed, in terms
of the small-signal gate voltage of that inverter, as follows. The drain current of each inverter
is also equal to the gate current of the other inverter.
SR Latch Circuit:
The bistable element consisting of two cross-coupled inverters has two stable
operating modes, or states. The circuit preserves its state (either one of the two possible
modes) as long as the power supply voltage is provided; hence, the circuit can perform a
simple memory function of holding its state. However, the simple two-inverter circuit
examined above has no provision for allowing its state to be changed externally from one
stable operating mode to the other. To allow such a change of state, we must add simple
switches to the bistable element, which can be used to force or trigger the circuit from one
operating point to the other. Figure shows the circuit structure of the simple CMOS SR latch,
which has two such triggering inputs, S (set) and R (reset). In the literature, the SR latch is
also called an SR flip-flop, since two stable states can be switched back and forth. The circuit
consists of two CMOS NOR2 gates. One of the input terminals of each NOR gate is used to
cross-couple to the output of the other NOR gate, while the second input enables triggering of
the circuit.

The SR latch circuit has two complementary outputs, Q and Q’. By definition, the
latch is said to be in its set state when Q is equal to logic "1" and Q’ is equal to logic "0".
Conversely, the latch is in its reset state when the output Q is equal to logic "0" and Q’ is
equal to "1". When both input signals are equal to logic "0," it will preserve (hold) either one
of its two stable operating points (states) as determined by the previous inputs.
If the set input (S) is equal to logic "1" and the reset input is equal to logic "0," then
the output node Q will be forced to logic "1" while the output node Q’ is forced to logic "0."
This means that the SR latch will be set, regardless of its previous state. Similarly, if S is
equal to "0" and R is equal to "1" then the output node Q will be forced to "0" while Q’ is
forced to "1". Thus, with this input combination, the latch is reset, regardless of its previously
held state. Finally, consider the case in which both of the inputs S and R are equal to logic "1"
In this case, both output nodes will be forced to logic "0" which conflicts with the
complementarity of Q and Q’. Therefore, this input combination is not permitted during
normal operation and is considered to be a not allowed condition.
 The operation of the CMOS SR latch circuit shown in Figure can be examined in
more detail by considering the operating modes of the four nMOS transistors, MI, M2, M3,
and M4. If the set input (S) is equal to VOH and the reset input (R) is equal to VOL, both of the
parallel-connected transistors Ml and M2 will be on. Consequently, the voltage on node Q’
will assume a logic-low level of VOL = 0. At the same time, both M3 and M4 are turned off,
which results in a logic-high voltage VOH at node Q. If the reset input (R) is equal to VOH and
the set input (S) is equal to VOL, the situation will be reversed (Ml and M2 turned off and M3
and M4 turned on). When both of the input voltages are equal to VOL on the other hand, there
are two possibilities. Depending on the previous state of the SR latch, either M2 or M3 will
be on, while both of the trigger transistors MI and M4 are off. This will generate a logic-low
level of VOL = O at one of the output nodes, while the complementary output node is at VOH.

For the transient analysis of the SR latch circuit, consider an event which results in a
state change, i.e., either an initially reset latch being set by applying a set signal, or an
initially set latch being reset by applying the reset signal. In either case, we note that both of
the output nodes undergo simultaneous voltage transitions. While one output is rising from its
logic-low level to logic-high, the other output node is falling from its initial logic-high level
to logic-low.
To calculate the switching times for both output nodes, we first have to find the total
parasitic capacitance associated with each node. The total lumped capacitance at each output
node can be approximated as follows:

Assuming that the latch is initially reset and that a set operation is being performed by
applying S = "1" and R = "0" the rise time associated with node Q can now be estimated as
follows.
NOR Based SR Latch Using NMOS Logic:
The NOR-based SR latch can also be implemented by using two cross-coupled
depletion-load nMOS NOR2 gates, as shown in Figure. From the logic point of view, the operation
principle of the depletion-load nMOS NOR-based SR latch is identical to that of the CMOS SR latch.
In terms of power dissipation and noise margins, however, the CMOS circuit implementation offers a
better alternative, since both of the CMOS NOR2 gates dissipate virtually no static power for
preserving a state, and since the output voltages can exhibit a full swing between 0 and VDD.

NAND Based SR Latch:

In NAND-based SR latch circuit in order to hold (preserve) a state, both of the

external trigger inputs must be equal to logic "1". The operating point or the state of the
circuit can be changed only by pulling the set input to logic zero or by pulling the reset input
to zero. We can observe that if S is equal to "0" and R is equal to "1" the output Q attains a
logic "1" value and the complementary output Q’ becomes logic "0". Thus, in order to set the
NAND SR latch, a logic "0" must be applied to the set (S) input. Similarly, in order to reset
the latch, a logic "0" must be applied to the reset (R) input.
NAND Based SR Latch Using NMOS Logic:

Clocked Latch and Flip-Flop Circuits:

Clocked NOR Based SR Latch:

To facilitate synchronous operation, the circuit response can be controlled simply by

adding a gating clock signal to the circuit, so that the outputs will respond to the input levels
only during the active period of a clock pulse.

The gate-level schematic of a clocked NOR-based SR latch is shown in Figure. It can

be seen that if the clock (CK) is equal to logic "0" the input signals have no influence upon
the circuit response. The outputs of the two AND gates will remain at logic "0," which forces
the SR latch to hold its current state regardless of the S and R input signals. When the clock
input goes to logic "1" the logic levels applied to the S and R inputs are permitted to reach the
SR latch, and possibly change its state. Note that as in the non-clocked SR latch, the input
combination S = R = "1" is not allowed in the clocked SR latch. With both inputs S and R at
logic "1" the occurrence of a clock pulse causes both outputs to go momentarily to zero.
When the clock pulse is removed, i.e., when it becomes "0," the state of the latch is
indeterminate.

Figure shows a CMOS implementation of the clocked NOR-based SR latch circuit,

using two simple AOI gates the AOI-based implementation of the circuit results in a very
small transistor count, compared with the alternative circuit realization consisting of two
AND2 and two NOR2 gates.
Clocked NAND Based SR Latch:

The NAND-based SR latch can also be implemented with gating clock input, as
shown in Figure. Both input signals S and R as well as the clock signal CK are active low in
this case. This means that changes in the input signal levels will be ignored when the clock is
equal to logic " 1," and that inputs will influence the outputs only when the clock is active,
i.e., CK = "0." For the circuit implementation of this clocked NAND-based SR latch, use a
simple OAI structure, which is essentially analogous to the AOI-based realization of the
clocked NOR SR latch circuit.

A different implementation of the clocked NAND-based SR latch is shown in Figure.

Here, both input signals and the CK signal are active high, i.e., the latch output Q will be set
when CK = "1", S = "1" and R = "O" Similarly, the latch will be reset when CK = "1", S =
"O" and R = "1" The latch preserves its state as long as the clock signal is inactive, i.e., when
CK = "O".
Clocked NAND Based JK Latch:
Figure shows an all-NAND implementation of the JK latch with active high inputs,
and the corresponding block diagram representation. The JK latch is commonly called a JK
flip-flop.

The J and K inputs in this circuit correspond to the set and reset inputs of the basic SR
latch. When the clock is active, the latch can be set with the input combination (J = "1" K =
"0"), and it can be reset with the input combination (J = "0" K = "1"). If both inputs are equal
to logic "0," the latch preserves its current state. If, on the other hand, both inputs are equal to
"1" during the active clock phase, the latch simply switches its state due to feedback. In other
words, the JK latch does not have a not-allowed input combination. As in the other clocked
latch circuits, the JK latch will hold its current state when the clock is inactive (CK = "0").
The operation of the clocked JK latch is summarized in the truth table shown below.

Clocked NOR Based JK Latch:

NAND Based Master Slave JK Flip Flop:
Two cascaded stages are activated with opposite clock phases. This configuration is
called the master-slave flip-flop.

The input latch in Figure, called the "master," is activated when the clock pulse is
high. During this phase, the inputs J and K allow data to be entered into the flip-flop, and the
first-stage outputs are set according to the primary inputs. When the clock pulse goes to zero,
the master latch becomes inactive and the second-stage latch, called the "slave" becomes
active. The output levels of the flip-flop circuit are determined during this second phase,
based on the master-stage outputs set in the previous phase. Since the master and the slave
stages are effectively decoupled from each other with the opposite clocking scheme, the
circuit is never transparent, i.e., a change occurring in the primary inputs is never reflected
directly to the outputs. This very important property clearly separates the master-slave flip-
flop from all of the latch circuits Because the master and the slave stages are decoupled from
each other, the circuit allows for toggling when J = K = "1," but it eliminates the possibility
of uncontrolled oscillations since only one stage is active at any given time.
NOR Based Master Slave JK Flip Flop:

CMOS D-Latch and Edge Triggered Flip Flop:

The gate-level representation of the D-latch is simply obtained by modifying the

clocked NOR-based SR latch circuit. Here, the circuit has a single input D, which is directly
connected to the S input of the latch. The input variable D is also inverted and connected to
the R input of the latch. It can be seen from the gate-level schematic that the output Q
assumes the value of the input D when the clock is active, i.e., for CK = "1" When the clock
signal goes to zero, the output will simply preserve its state. Thus, the CK input acts as an
enable signal which allows data to be accepted into the D-latch.

CMOS D-Latch (Type1):

Consider the circuit diagram given in Figure, which shows a basic two-inverter loop
and two CMOS transmission gate (TG) switches.
 The TG at the input is activated by the CK signal, whereas the TG in the inverter loop
is activated by the inverse of the CK signal, CK. Thus, the input signal is accepted (latched)
into the circuit when the clock is high, and this information is preserved as the state of the
inverter loop when the clock is low. The operation of the CMOS D-latch circuit can be better
visualized by replacing the CMOS transmission gates with simple switches, as shown in
Figure. A timing diagram in this figure shows the time intervals during which the input and
the output signals should be valid (unshaded).

The valid D input must be stable for a short time before (setup time, tsetup) and after
(hold time, t hold) the negative clock transition, during which the input switch opens and the
loop switch closes. Once the inverter loop is completed by closing the loop switch, the output
will preserve its valid level.

CMOS D-Latch (Type2):

Figure shows a different version of the CMOS D-latch. The circuit contains two
tristate inverters, driven by the clock signal and its inverse. The first tri-state inverter acts as
the input switch, accepting the input signal when the clock is high. At this time, the second
tristate inverter is at its high-impedance state, and the output Q is following the input signal.
When the clock goes low, the input buffer becomes inactive, and the second tristate inverter
completes the two-inverter loop, which preserves its state until the next clock pulse.

CMOS Master Slave D Flip Flop:

Consider the two-stage master-slave flip-flop circuit shown in Figure which is
constructed by simply cascading two, D-latch circuits. The first stage (master) is driven by
the clock signal, while the second stage (slave) is driven by the inverted clock signal. Thus,
the master stage is positive level-sensitive, while the slave stage is negative level-sensitive.
When the clock is, high, the master stage follows the D input while the slave stage holds the
previous value. When the clock changes from logic "1" to logic "0" the master latch ceases to
sample the input and stores the D value at the time of the clock transition. At the same time,
the slave latch becomes transparent, passing the stored master value Qm to the output of the
slave stage, Qs. The input cannot affect the output because the master stage is disconnected
from the D input. When the clock changes again from logic "0" to "1" the slave latch locks in
the master latch output and the master stage starts sampling the input again. Thus, this circuit
is a negative edge-triggered D flip-flop by virtue of the fact that it samples the input at the
falling edge of the clock pulse.

NAND3 Based Positive Edge Triggered D Flip Flop:

Another implementation of edge-triggered D flip-flop is shown in Figure, which
consists of six NAND3 gates. This D flip-flop is positive edge-triggered as shown in
waveforms. Initially, all the signal values except for S are 0, i.e., (S, R, CK, D) = (1, 0, 0, 0),
and Q = 0. In the second phase, both D and R switch to 1, i.e., (S, R, CK, D) = (1, 0, 1, 1), but
no change in Q occurs and the Q value remains at 0. However, in the third phase, if CK goes
to high, i.e., (S, R, CK, D) = (1, 1, 1, 1), the output of gate2 switches to 0, which in turn sets
the output of the last stage SR latch to 1. Thus, the output of this D flip-flop switches to 1 at
the positive-going edge of the clock signal, CK. However, in the ninth phase of the
waveform, the Q output is not affected by the negative-going edge of CK, nor by other signal
changes.