Datasheet

RA6M2 Group R01DS0357EJ0120

Rev.1.20
Datasheet Dec 23, 2022

Leading performance 120-MHz Arm® Cortex®-M4 core, up to 1-MB code flash memory, 384-KB SRAM, Capacitive
Touch Sensing Unit, Ethernet MAC Controller, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and
advanced analog.

Features
■ Arm Cortex-M4 Core with Floating Point Unit (FPU) ■ System and Power Management
 Armv7E-M architecture with DSP instruction set  Low power modes
 Maximum operating frequency: 120 MHz  Realtime Clock (RTC) with calendar and VBATT support
 Support for 4-GB address space  Event Link Controller (ELC)
 On-chip debugging system: JTAG, SWD, and ETM  DMA Controller (DMAC) × 8
 Boundary scan and Arm Memory Protection Unit (Arm MPU)  Data Transfer Controller (DTC)
 Key Interrupt Function (KINT)
■ Memory
 Power-on reset
 Up to 1-MB code flash memory (40 MHz zero wait states)
 Low Voltage Detection (LVD) with voltage settings
 32-KB data flash memory (125,000 erase/write cycles)
 Up to 384-KB SRAM ■ Security and Encryption
 Flash Cache (FCACHE)  AES128/192/256
 Memory Protection Units (MPU)  3DES/ARC4
 Memory Mirror Function (MMF)  SHA1/SHA224/SHA256/MD5
 128-bit unique ID  GHASH
 RSA/DSA/ECC
■ Connectivity
 True Random Number Generator (TRNG)
 Ethernet MAC Controller (ETHERC)
 Ethernet DMA Controller (EDMAC) ■ Human Machine Interface (HMI)
 USB 2.0 Full-Speed (USBFS) module  Capacitive Touch Sensing Unit (CTSU)
- On-chip transceiver  Parallel Data Capture Unit (PDC)
 Serial Communications Interface (SCI) with FIFO × 10
■ Multiple Clock Sources
 Serial Peripheral Interface (SPI) × 2
 Main clock oscillator (MOSC) (8 to 24 MHz)
 I2C bus interface (IIC) × 3
 Sub-clock oscillator (SOSC) (32.768 kHz)
 Controller Area Network (CAN) × 2
 High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
 Serial Sound Interface Enhanced (SSIE)
 Middle-speed on-chip oscillator (MOCO) (8 MHz)
 SD/MMC Host Interface (SDHI) × 2
 Low-speed on-chip oscillator (LOCO) (32.768 kHz)
 Quad Serial Peripheral Interface (QSPI)
 IWDT-dedicated on-chip oscillator (15 kHz)
 IrDA interface
 Clock trim function for HOCO/MOCO/LOCO
 Sampling Rate Converter (SRC)
 Clock out support
 External address space
- 8-bit or 16-bit bus space is selectable per area ■ General-Purpose I/O Ports
- SDRAM support  Up to 110 input/output pins
- Up to 1 CMOS input
■ Analog
- Up to 109 CMOS input/output
 12-bit A/D Converter (ADC12) with 3 sample-and-hold circuits
- Up to 21 input/output 5 V tolerant
each × 2
- Up to 18 high current (20 mA)
 12-bit D/A Converter (DAC12) × 2
 High-Speed Analog Comparator (ACMPHS) × 6 ■ Operating Voltage
 Temperature Sensor (TSN)  VCC: 2.7 to 3.6 V
■ Timers ■ Operating Temperature and Packages
 General PWM Timer 32-bit Enhanced High Resolution  Ta = -40°C to +105°C
(GPT32EH) × 4 - 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch)
 General PWM Timer 32-bit Enhanced (GPT32E) × 4 - 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
 General PWM Timer 32-bit (GPT32) × 6 - 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
 Low Power Asynchronous General-Purpose Timer (AGT) × 2
 Watchdog Timer (WDT)
■ Safety
 Error Correction Code (ECC) in SRAM
 SRAM parity error check
 Flash area protection
 ADC self-diagnosis function
 Clock Frequency Accuracy Measurement Circuit (CAC)
 Cyclic Redundancy Check (CRC) calculator
 Data Operation Circuit (DOC)
 Port Output Enable for GPT (POEG)
 Independent Watchdog Timer (IWDT)
 GPIO readback level detection
 Register write protection
 Main oscillator stop detection
 Illegal memory access

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1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 120 MHz with the
following features:
 Up to 1-MB code flash memory
 384-KB SRAM
 Capacitive Touch Sensing Unit (CTSU)
 Ethernet MAC Controller (ETHERC), USBFS, SD/MMC Host Interface
 Quad Serial Peripheral Interface (QSPI)
 Security and safety features
 12-bit A/D Converter (ADC12)
 12-bit D/A Converter (DAC12)
 Analog peripherals.

1.1 Function Outline

Table 1.1 Arm core

Feature Functional description
Arm Cortex-M4 core  Maximum operating frequency: up to 120 MHz
 Arm Cortex-M4 core:
- Revision: r0p1-01rel0
- ARMv7E-M architecture profile
- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.
 Arm Memory Protection Unit (Arm MPU):
- Armv7 Protected Memory System Architecture
- 8 protect regions.
 SysTick timer:
- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2 Memory

Feature Functional description
Code flash memory Maximum 1-MB code flash memory. See section 53, Flash Memory in Userʼs Manual.
Data flash memory 32-KB data flash memory. See section 53, Flash Memory in Userʼs Manual.
Memory Mirror Function (MMF) The Memory Mirror Function (MMF) can be configured to mirror the target application image
load address in code flash memory to the application image link address in the 23-bit unused
memory space (memory mirror space addresses). Your application code is developed and
linked to run from this MMF destination address. The application code does not need to know
the load location where it is stored in code flash memory. See section 5, Memory Mirror
Function (MMF) in Userʼs Manual.
Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 7,
Option-Setting Memory in Userʼs Manual.
SRAM On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). The first 32
KB of SRAM0 error correction capability using ECC. Parity check is performed for other areas.
See section 51, SRAM in Userʼs Manual.
Standby SRAM On-chip SRAM that can retain data in Deep Software Standby mode. See section 52, Standby
SRAM in Userʼs Manual.

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Table 1.3 System (1 of 2)

Feature Functional description
Operating modes Two operating modes:
 Single-chip mode
 SCI or USB boot mode.
See section 3, Operating Modes in Userʼs Manual.
Resets 14 resets:
 RES pin reset
 Power-on reset
 Voltage monitor 0 reset
 Voltage monitor 1 reset
 Voltage monitor 2 reset
 Independent watchdog timer reset
 Watchdog timer reset
 Deep Software Standby reset
 SRAM parity error reset
 SRAM ECC error reset
 Bus master MPU error reset
 Bus slave MPU error reset
 Stack pointer error reset
 Software reset.
See section 6, Resets in Userʼs Manual.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and
the detection level can be selected using a software program. See section 8, Low Voltage
Detection (LVD) in Userʼs Manual.
Clocks  Main clock oscillator (MOSC)
 Sub-clock oscillator (SOSC)
 High-speed on-chip oscillator (HOCO)
 Middle-speed on-chip oscillator (MOCO)
 Low-speed on-chip oscillator (LOCO)
 PLL frequency synthesizer
 IWDT-dedicated on-chip oscillator
 Clock out support.
See section 9, Clock Generation Circuit in Userʼs Manual.
Clock Frequency Accuracy The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
Measurement Circuit (CAC) measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated.
See section 11, Clock Frequency Accuracy Measurement Circuit (CAC) in Userʼs Manual.
Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 10, Interrupt
Controller Unit (ICU) in Userʼs Manual.
Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function
(KINT) in Userʼs Manual.
Low power modes Power consumption can be reduced in multiple ways, such as by setting clock dividers,
controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power
control mode in normal operation, and transitioning to low power modes. See section 12, Low
Power Modes in Userʼs Manual.
Battery backup function A battery backup function is provided for partial powering by a battery. The battery powered
area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See
section 13, Battery Backup Function in Userʼs Manual.
Register write protection The register write protection function protects important registers from being overwritten
because of software errors. See section 14, Register Write Protection in Userʼs Manual.
Memory Protection Unit (MPU) Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 16, Memory Protection Unit (MPU) in Userʼs Manual.

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Table 1.3 System (2 of 2)

Feature Functional description
Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow.
A refresh-permitted period can be set to refresh the counter and be used as the condition for
detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in
Userʼs Manual.
Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt or interrupt for a timer underflow. Because
the timer operates with an independent, dedicated clock source, it is particularly useful in
returning the MCU to a known state as a fail-safe mechanism when the system runs out of
control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by
a refresh of the count value in the registers. See section 28, Independent Watchdog Timer
(IWDT) in Userʼs Manual.

Table 1.4 Event link

Feature Functional description
Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 19, Event Link Controller (ELC)
in Userʼs Manual.

Table 1.5 Direct memory access

Feature Functional description
Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 18, Data Transfer Controller (DTC) in Userʼs Manual.
DMA Controller (DMAC) An 8-channel DMAC module is provided for transferring data without the CPU. When a DMA
transfer request is generated, the DMAC transfers data stored at the transfer source address
to the transfer destination address. See section 17, DMA Controller (DMAC) in Userʼs Manual.

Table 1.6 External bus interface

Feature Functional description
External buses  CS area (EXBIU): Connected to the external devices (external memory interface)
 SDRAM area (EXBIU): Connected to the SDRAM (external memory interface)
 QSPI area (EXBIUT2): Connected to the QSPI (external device interface).

Table 1.7 Timers (1 of 2)

Feature Functional description
General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 14 channels. PWM waveforms can be
generated by controlling the up-counter, down-counter, or up- and down-counter. In addition,
PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be
used as a general-purpose timer. See section 23, General PWM Timer (GPT) in Userʼs
Manual.
Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in
Userʼs Manual.
Low Power Asynchronous General- The Low Power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
Purpose Timer (AGT) for pulse output, external pulse width or period measurement, and counting of external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and can be accessed with the AGT register.
See section 25, Low Power Asynchronous General-Purpose Timer (AGT) in Userʼs Manual.

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Table 1.7 Timers (2 of 2)

Feature Functional description
Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 26, Realtime Clock (RTC) in Userʼs Manual.

Table 1.8 Communication interfaces (1 of 2)

Feature Functional description
Serial Communications Interface The Serial Communications Interface (SCI) is configurable to five asynchronous and
(SCI) synchronous serial interfaces:
 Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
 8-bit clock synchronous interface
 Simple IIC (master-only)
 Simple SPI
 Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 32, Serial Communications Interface (SCI) in Userʼs Manual.
IrDA Interface (IrDA) The IrDA interface sends and receives IrDA data communication waveforms in cooperation
with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 33,
IrDA Interface in Userʼs Manual.
I2C bus interface (IIC) The 3-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C
(Inter-Integrated Circuit) bus interface functions. See section 34, I2C Bus Interface (IIC) in
Userʼs Manual.
Serial Peripheral Interface (SPI) Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-
duplex synchronous serial communications with multiple processors and peripheral devices.
See section 36, Serial Peripheral Interface (SPI) in Userʼs Manual.
Serial Sound Interface Enhanced The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
(SSIE) digital audio devices for transmitting I2S (Inter-Integrated Sound) 2ch, 4ch, 6ch, 8ch, Word
Select (WS) Continue/Monaural/TDM audio data over a serial bus. The SSIE supports an
audio clock frequency of up to 50 MHz, and can be operated as a slave or master receiver,
transmitter, or transceiver to suit various applications. The SSIE includes 32-stage FIFO
buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception
and transmission. See section 39, Serial Sound Interface Enhanced (SSIE) in Userʼs Manual.
Quad Serial Peripheral Interface The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial
(QSPI) ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM)
that has an SPI-compatible interface. See section 37, Quad Serial Peripheral Interface (QSPI)
in Userʼs Manual.
Controller Area Network (CAN) The Controller Area Network (CAN) module provides functionality to receive and transmit data
module using a message-based protocol between multiple slaves and masters in electromagnetically-
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 35, Controller Area Network (CAN) Module in Userʼs Manual.
USB 2.0 Full-Speed (USBFS) module The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller.
The module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9
can be assigned any endpoint number based on the peripheral devices used for
communication or based on your system. See section 31, USB 2.0 Full-Speed Module
(USBFS) in Userʼs Manual.

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Table 1.8 Communication interfaces (2 of 2)

Feature Functional description
Ethernet MAC (ETHERC) One-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3
Media Access Control (MAC) layer protocol. An ETHERC channel provides one channel of the
MAC layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows
transmission and reception of frames compliant with the Ethernet and IEEE802.3 standards.
The ETHERC is connected to the Ethernet DMA Controller (EDMAC) so data can be
transferred without using the CPU.
See section 29, Ethernet MAC Controller (ETHERC) in Userʼs Manual.
SD/MMC Host Interface (SDHI) The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit
buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with
the SD Host/Ancillary Product License Agreement (SD HALA).
The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51
(JEDEC Standard JESD 84-B451) device access. This interface also provides backward
compatibility and supports high-speed SDR transfer modes. See section 41, SD/MMC Host
Interface (SDHI) in Userʼs Manual.

Table 1.9 Analog

Feature Functional description
12-bit A/D Converter (ADC12) Two units of successive approximation 12-bit A/D Converter (ADC12) are provided. Analog
input channels are selectable up to 13 in unit 0 and up to 9 in unit 1. Each 2 analog inputs of
unit 0 and 1 are assigned to same port (AN005/AN105, AN006/AN106), up to 20 ports are
available as analog input. The temperature sensor output and an internal reference voltage are
selectable for conversion of each unit 0 and 1. The A/D conversion accuracy is selectable from
12-bit, 10-bit, and 8-bit conversion, making it possible to optimize the tradeoff between speed
and resolution in generating a digital value. See section 45, 12-Bit A/D Converter (ADC12) in
Userʼs Manual.
12-bit D/A Converter (DAC12) The12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section
46, 12-Bit D/A Converter (DAC12) in Userʼs Manual.
Temperature sensor (TSN) The on-chip temperature sensor can determine and monitor the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC12 for conversion and can also be used by the end
application. See section 47, Temperature Sensor (TSN) in Userʼs Manual.
High-Speed Analog Comparator The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference
(ACMPHS) voltage and provides a digital output based on the conversion result.
Both the test and reference voltages can be provided to the comparator from internal sources
such as the DAC12 output and internal reference voltage, and an external source.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 48, High-
Speed Analog Comparator (ACMPHS) in Userʼs Manual.

Table 1.10 Human machine interfaces

Feature Functional description
Capacitive Touch Sensing Unit The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
(CTSU) touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do
not come into direct contact with the electrodes. See section 49, Capacitive Touch Sensing
Unit (CTSU) in Userʼs Manual.

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Table 1.11 Graphics

Feature Functional description
Parallel Data Capture (PDC) unit One Parallel Data Capture (PDC) unit is provided to communicate with external I/O devices,
including image sensors, and to transfer parallel data such as an image output from the
external I/O device through the DTC or DMAC to the on-chip SRAM and external address
spaces (the CS and SDRAM areas). See section 42, Parallel Data Capture Unit (PDC) in
Userʼs Manual.

Table 1.12 Data processing

Feature Functional description
Cyclic Redundancy Check (CRC) The CRC calculator generates CRC codes to detect errors in the data. The bit order of CRC
calculator calculation results can be switched for LSB-first or MSB-first communication. Additionally,
various CRC-generating polynomials are available. The snoop function allows monitoring
reads from and writes to specific addresses. This function is useful in applications that require
CRC code to be generated automatically in certain events, such as monitoring writes to the
serial transmit buffer and reads from the serial receive buffer. See section 38, Cyclic
Redundancy Check (CRC) Calculator in Userʼs Manual.
Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 50,
Data Operation Circuit (DOC) in Userʼs Manual.
Sampling Rate Converter (SRC) The Sampling Rate Converter (SRC) converts the sampling rate of data produced by various
audio decoders, such as the WMA, MP3, and AAC. Both 16-bit stereo and monaural data are
supported.
See section 40, Sampling Rate Converter (SRC) in Userʼs Manual.

Table 1.13 Security

Feature Functional description
Secure Crypto Engine 7 (SCE7)  Security algorithms:
- Symmetric algorithms: AES, 3DES, and ARC4
- Asymmetric algorithms: RSA, DSA, and ECC.
 Other support features:
- TRNG (True Random Number Generator)
- Hash-value generation: SHA1, SHA224, SHA256, GHASH, and MD5
- 128-bit unique ID.
See section 44, Secure Cryptographic Engine (SCE7) in Userʼs Manual.

Table 1.14 I/O ports

Feature Functional description
Programmable I/O ports  I/O ports for the 145-pin LGA, 144-pin LQFP
- I/O pins: 109
- Input pins: 1
- Pull-up resistors: 110
- N-ch open-drain outputs: 109
- 5-V tolerance: 21
 I/O ports for the 100-pin LQFP
- I/O pins: 75
- Input pins: 1
- Pull-up resistors: 76
- N-ch open-drain outputs: 75
- 5-V tolerance: 14

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1.2 Block Diagram

Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the
features.

Memory Bus Arm Cortex-M4 System

1 MB code flash DSP FPU POR/LVD Clocks

External

CSC MOSC/SOSC
32 KB data flash
MPU Reset
SDRAM (H/M/L) OCO
384 KB SRAM
NVIC
8 KB Standby Mode control PLL
MPU
SRAM
System timer
Power control CAC

DMA Test and DBG interface

ICU Battery backup
DTC

Register write
DMAC × 8 KINT
protection

Timers Communication interfaces Human machine interfaces

SCI × 10 Graphics
QSPI ETHERC CTSU
GPT32EH x 4 IrDA × 1
GPT32E x 4 PDC
GPT32 x 6
IIC × 3 SDHI × 2

SPI × 2 CAN × 2
AGT × 2

SSIE USBFS
RTC

WDT/IWDT

Event link Data processing Analog

ELC CRC SRC ADC12 × 2 TSN

Security DOC DAC12 ACMPHS × 6

SCE7

Figure 1.1 Block diagram

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1.3 Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.15 shows a
list of products.

R7FA6M2AF3C FB #A A 0

Production identification code

Terminal material (Pb-free)

A: Sn (Tin) only
C: Others

Packing
A: Tray
B: Tray (Full carton)
H: Tape and reel

Package type
FB: LQFP 144 pins
FP: LQFP 100 pins
LK: LGA 145 pins

Quality Grade

Operating temperature
2: -40°C to 85°C
° °
3: -40 C to 105 C

Code flash memory size

D: 512 KB
F: 1 MB
Feature set

Group name

Series name

RA family

Flash memory
Renesas microcontroller

Note: Check the order screen for each product on the Renesas website for valid symbols after the #.

Figure 1.2 Part numbering scheme

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Table 1.15 Product list

Code Data Operating
Product part number Package flash flash SRAM temperature
R7FA6M2AF2CLK PTLG0145KA-A 1 MB 32 KB 384 KB -40 to +85°C
R7FA6M2AF3CLK -40 to +105°C
R7FA6M2AF3CFB PLQP0144KA-B -40 to +105°C
R7FA6M2AF3CFP PLQP0100KB-B -40 to +105°C
R7FA6M2AD2CLK PTLG0145KA-A 512 KB -40 to +85°C
R7FA6M2AD3CLK -40 to +105°C
R7FA6M2AD3CFB PLQP0144KA-B -40 to +105°C
R7FA6M2AD3CFP PLQP0100KB-B -40 to +105°C

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1.4 Function Comparison

Table 1.16 Functional comparison

Part numbers
R7FA6M2AF2CLK/
R7FA6M2AD2CLK/
R7FA6M2AF3CLK/ R7FA6M2AF3CFB/ R7FA6M2AF3CFP/
Function R7FA6M2AD3CLK R7FA6M2AD3CFB R7FA6M2AD3CFP
Pin count 145 144 100
Package LGA LQFP LQFP
Code flash memory 1 MB/512 KB
Data flash memory 32 KB
SRAM 384 KB
Parity 352 KB
ECC 32 KB
Standby SRAM 8 KB
System CPU clock 120 MHz
Backup registers 512 B
ICU Yes
KINT 8
Event link ELC Yes
DMA DTC Yes
DMAC 8
BUS External bus 16-bit bus 8-bit bus
SDRAM Yes No
Timers GPT32EH 4 4 4
GPT32E 4 4 4
GPT32 6 6 5
AGT 2 2 2
RTC Yes
WDT/IWDT Yes
Communication SCI 10
IIC 3 2
SPI 2
SSIE 1
QSPI 1
SDHI 2
CAN 2
USBFS Yes
ETHERC 1
Analog ADC12 Unit0: 13 Unit0: 11
Unit1: 9 Unit1: 8
Shared channel pin: 2*1 Shared channel pin: 2*1
3ch-S/H Unit0: 1 (3ch)
Unit1: 1 (3ch)
DAC12 2
ACMPHS 6
TSN Yes
HMI CTSU 18 12
Graphics PDC Yes
Data processing CRC Yes
DOC Yes
SRC Yes
Security SCE7
I/O ports I/O pins 109 75
Input pins 1 1
Pull-up resistors 110 76
N-ch open-drain outputs 109 75
5-V tolerance 21 14

Note 1. Some input channels of the ADC units are sharing same port pin.

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1.5 Pin Functions

Table 1.17 Pin functions (1 of 5)

Function Signal I/O Description
Power supply VCC Input Power supply pin. This is used as the digital power supply for the respective
modules and internal voltage regulator, and used to monitor the voltage of
the POR/LVD. Connect it to the system power supply. Connect this pin to
VSS by a 0.1-μF capacitor. Place the capacitor close to the pin.
VCL0 - Connect to VSS through a 0.1-μF smoothing capacitor close to each VCL
VCL - pin. Stabilize the internal power supply.
VSS Input Ground pin. Connect to the system power supply (0 V).
VBATT Input Backup power pin
Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the
EXTAL Input EXTAL pin.
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator
XCOUT Output between XCOUT and XCIN.
EBCLK Output Outputs the external bus clock for external devices
SDCLK Output Outputs the SDRAM-dedicated clock
CLKOUT Output Clock output pin
Operating mode MD Input Pin for setting the operating mode. The signal level on this pin must not be
control changed during operation mode transition on release from the reset state.
System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes
low.
CAC CACREF Input Measurement reference clock input pin
Interrupt NMI Input Non-maskable interrupt request pin
IRQ0 to IRQ15 Input Maskable interrupt request pins
KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key
interrupt input pins
On-chip emulator TMS I/O On-chip emulator or boundary scan pins
TDI Input
TCK Input
TDO Output
TCLK Output This pin outputs the clock for synchronization with the trace data
TDATA0 to TDATA3 Output Trace data output
SWDIO I/O Serial wire debug data input/output pin
SWCLK Input Serial wire clock pin
SWO Output Serial wire trace output pin
External bus RD Output Strobe signal indicating that reading from the external bus interface space is
interface in progress, active-low
WR Output Strobe signal indicating that writing to the external bus interface space is in
progress, in 1-write strobe mode, active-low
WR0 to WR1 Output Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in writing to the external bus interface space, in byte
strobe mode, active-low
BC0 to BC1 Output Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in access to the external bus interface space, in 1-write
strobe mode, active-low
ALE Output Address latch signal when address/data multiplexed bus is selected
WAIT Input Input pin for wait request signals in access to the external space, active-low
CS0 to CS7 Output Select signals for CS areas, active-low
A00 to A20 Output Address bus
D00 to D15 I/O Data bus
A00/D00 to A15/D15 I/O Address/data multiplexed bus

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Table 1.17 Pin functions (2 of 5)

Function Signal I/O Description
SDRAM interface CKE Output SDRAM clock enable signal
SDCS Output SDRAM chip select signal, active-low
RAS Output SDRAM low address strobe signal, active-low
CAS Output SDRAM column address strobe signal, active-low
WE Output SDRAM write enable signal, active-low
DQM0 Output SDRAM I/O data mask enable signal for DQ07 to DQ00
DQM1 Output SDRAM I/O data mask enable signal for DQ15 to DQ08
A00 to A15 Output Address bus
DQ00 to DQ15 I/O Data bus
GPT GTETRGA, Input External trigger input pins
GTETRGB,
GTETRGC,
GTETRGD
GTIOC0A to I/O Input capture, output compare, or PWM output pins
GTIOC13A,
GTIOC0B to
GTIOC13B
GTIU Input Hall sensor input pin U
GTIV Input Hall sensor input pin V
GTIW Input Hall sensor input pin W
GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase)
GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase)
AGT AGTEE0, AGTEE1 Input External event input enable signals
AGTIO0, AGTIO1 I/O External event input and pulse output pins
AGTO0, AGTO1 Output Pulse output pins
AGTOA0, AGTOA1 Output Output compare match A output pins
AGTOB0, AGTOB1 Output Output compare match B output pins
RTC RTCOUT Output Output pin for 1-Hz or 64-Hz clock
RTCIC0 to RTCIC2 Input Time capture event input pins
SCI SCK0 to SCK9 I/O Input/output pins for the clock (clock synchronous mode)
RXD0 to RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode)
TXD0 to TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous
mode)
CTS0_RTS0 to I/O Input/output pins for controlling the start of transmission and reception
CTS9_RTS9 (asynchronous mode/clock synchronous mode), active-low
SCL0 to SCL9 I/O Input/output pins for the IIC clock (simple IIC mode)
SDA0 to SDA9 I/O Input/output pins for the IIC data (simple IIC mode)
SCK0 to SCK9 I/O Input/output pins for the clock (simple SPI mode)
MISO0 to MISO9 I/O Input/output pins for slave transmission of data (simple SPI mode)
MOSI0 to MOSI9 I/O Input/output pins for master transmission of data (simple SPI mode)
SS0 to SS9 Input Chip-select input pins (simple SPI mode), active-low
IIC SCL0 to SCL2 I/O Input/output pins for the clock
SDA0 to SDA2 I/O Input/output pins for data
SSIE SSIBCK0 I/O SSIE serial bit clock pins
SSILRCK0/SSIFS0 I/O LR clock/frame synchronization pins
SSITXD0 Output Serial data output pins
SSIRXD0 Input Serial data input pins
SSIDATA0 I/O Serial data input/output pins
AUDIO_CLK Input External clock pin for audio (input oversampling clock)

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RA6M2 Group 1. Overview

Table 1.17 Pin functions (3 of 5)

Function Signal I/O Description
SPI RSPCKA, RSPCKB I/O Clock input/output pin
MOSIA, MOSIB I/O Input or output pins for data output from the master
MISOA, MISOB I/O Input or output pins for data output from the slave
SSLA0, SSLB0 I/O Input or output pin for slave selection
SSLA1 to SSLA3, Output Output pins for slave selection
SSLB1 to SSLB3
QSPI QSPCLK Output QSPI clock output pin
QSSL Output QSPI slave output pin
QIO0 to QIO3 I/O Data0 to Data3
CAN CRX0, CRX1 Input Receive data
CTX0, CTX1 Output Transmit data
USBFS VCC_USB Input Power supply pins
VSS_USB Input Ground pins
USB_DP I/O D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of
the USB bus
USB_DM I/O D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of
the USB bus
USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the USB
bus. The VBUS pin status (connected or disconnected) can be detected
when the USB module is operating as a device controller.
USB_EXICEN Output Low-power control signal for external power supply (OTG) chip
USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA, Input Connect the external overcurrent detection signals to these pins. Connect
USB_OVRCURB the VBUS comparator signals to these pins when the OTG power supply
chip is connected.
USB_ID Input Connect the MicroAB connector ID input signal to this pin during operation in
OTG mode

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Table 1.17 Pin functions (4 of 5)

Function Signal I/O Description
ETHERC REF50CK0 Input 50-MHz reference clock. This pin inputs reference signal for
transmission/reception timing in RMII mode.
RMII0_CRS_DV Input Indicates carrier detection signals and valid receive data on RMII0_RXD1
and RMII0_RXD0 in RMII mode
RMII0_TXD0, Output 2-bit transmit data in RMII mode
RMII0_TXD1
RMII0_RXD0, Input 2-bit receive data in RMII mode
RMII0_RXD1
RMII0_TXD_EN Output Output pin for data transmit enable signal in RMII mode
RMII0_RX_ER Input Indicates an error occurred during reception of data in RMII mode
ET0_CRS Input Carrier detection/data reception enable signal
ET0_RX_DV Input Indicates valid receive data on ET0_ERXD3 to ET0_ERXD0
ET0_EXOUT Output General-purpose external output pin
ET0_LINKSTA Input Input link status from the PHY-LSI
ET0_ETXD0 to Output 4 bits of MII transmit data
ET0_ETXD3
ET0_ERXD0 to Input 4 bits of MII receive data
ET0_ERXD3
ET0_TX_EN Output Transmit enable signal. Functions as signal indicating that transmit data is
ready on ET0_ETXD3 to ET0_ETXD0
ET0_TX_ER Output Transmit error pin. Functions as signal notifying the PHY_LSI of an error
during transmission
ET0_RX_ER Input Receive error pin. Functions as signal to recognize an error during reception
ET0_TX_CLK Input Transmit clock pin. This pin inputs reference signal for output timing from
ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0, and ET0_TX_ER
ET0_RX_CLK Input Receive clock pin. This pin inputs reference signal for input timing to
ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and ET0_RX_ER
ET0_COL Input Input collision detection signal
ET0_WOL Output Receive Magic packets
ET0_MDC Output Output reference clock signal for information transfer through ET0_MDIO
ET0_MDIO I/O Input or output bidirectional signal for exchange of management data with
PHY-LSI
SDHI SD0CLK, SD1CLK Output SD clock output pins
SD0CMD, SD1CMD I/O Command output pin and response input signal pins
SD0DAT0 to I/O SD and MMC data bus pins
SD0DAT7,
SD1DAT0 to
SD1DAT7
SD0CD, SD1CD Input SD card detection pins
SD0WP Input SD write-protect signals
Analog power AVCC0 Input Analog voltage supply pin. This is used as the analog power supply for the
supply respective modules. Supply this pin with the same voltage as the VCC pin.
AVSS0 Input Analog ground pin. This is used as the analog ground for the respective
modules. Supply this pin with the same voltage as the VSS pin.
VREFH0 Input Analog reference voltage supply pin for the ADC12 (unit 0). Connect this pin
to VCC when not using the ADC12 (unit 0) and sample-and-hold circuit for
AN000 to AN002.
VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to VSS when
not using the ADC12 (unit 0) and sample-and-hold circuit for AN000 to
AN002
VREFH Input Analog reference voltage supply pin for the ADC12 (unit 1) and D/A
Converter. Connect this pin to VCC when not using the ADC12 (unit 1),
sample-and-hold circuit for AN100 to AN102, and D/A Converter.
VREFL Input Analog reference ground pin for the ADC12 and D/A Converter. Connect this
pin to VSS when not using the ADC12 (unit 1), sample-and-hold circuit for
AN100 to AN102, and D/A Converter.

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Table 1.17 Pin functions (5 of 5)

Function Signal I/O Description
ADC12 AN000 to AN007, Input Input pins for the analog signals to be processed by the ADC12.
AN016 to AN020 AN005 & AN105 and AN006 & AN106 are assigned to same port pin
AN100 to AN102, Input
AN105 to AN107,
AN116 to AN118
ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion
ADTRG1 Input
DAC12 DA0, DA1 Output Output pins for the analog signals processed by the D/A converter
ACMPHS VCOUT Output Comparator output pin
IVREF0 to IVREF3 Input Reference voltage input pins for comparator
IVCMP0 to IVCMP2 Input Analog voltage input pins for comparator
CTSU TS00 to TS17 Input Capacitive touch detection pins (touch pins)
TSCAP - Secondary power supply pin for the touch driver
I/O ports P000 to P009, I/O General-purpose input/output pins
P014, P015
P100 to P115 I/O General-purpose input/output pins
P200 Input General-purpose input pin
P201 to P214 I/O General-purpose input/output pins
P300 to P313 I/O General-purpose input/output pins
P400 to P415 I/O General-purpose input/output pins
P500 to P506, I/O General-purpose input/output pins
P508, P511, P512
P600 to P605, I/O General-purpose input/output pins
P608 to P614
P700 to P705, I/O General-purpose input/output pins
P708 to P713
P800, P801 I/O General-purpose input/output pins
PDC PIXCLK Input Image transfer clock pin
VSYNC Input Vertical synchronization signal pin
HSYNC Input Horizontal synchronization signal pin
PIXD0 to PIXD7 Input 8-bit image data pins
PCKO Output Output pin for dot clock

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RA6M2 Group 1. Overview

1.6 Pin Assignments

Figure 1.3 to Figure 1.5 show the pin assignments.

R7FA6M2AX2CLK

A B C D E F G H J K L M N

P212
13 P407 P409 P412 P708 P711 VCC XCIN VCL0 P702 P405 P402 P400 13
/EXTAL

P213
12 USB_DM USB_DP P410 P414 P710 VSS XCOUT VBATT P701 P404 P511 VCC 12
/XTAL

VCC_ VSS_
11 P207 P411 P415 P712 P705 P704 P703 P403 P401 P512 VSS 11
USB USB

10 P205 P206 P204 P408 P413 P709 P713 P700 P406 P003 P000 P002 P001 10

9 P203 P313 P202 VSS P004 P006 P009 P008 9

8 P214 P211 P200 VCC P005 AVSS0 VREFL0 VREFH0 8

7 P210 P209 RES P310 P007 AVCC0 VREFL VREFH 7

6 P208 P201/MD P312 P305 P505 P506 P015 P014 6

5 P309 P311 P308 P303 NC P503 P504 VSS VCC 5

4 P307 P306 P304 P109/TDO P114 P608 P604 P600 P105 P500 P502 P501 P508 4

3 VSS VCC P301 P112 P115 P610 P614 P603 P107 P106 P104 VSS VCC 3

P300/TCK
2 P302 P111 VCC P609 P612 VSS P605 P601 VCC P800 P101 P801 2
/SWCLK

P108/TMS
1 P110/TDI P113 VSS P611 P613 VCC VCL P602 VSS P103 P102 P100 1
/SWDIO

A B C D E F G H J K L M N

Figure 1.3 Pin assignment for 145-pin LGA (top view)

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RA6M2 Group 1. Overview

P108/TMS/SWDIO
P109/TDO
P110/TDI
P100
P101
P102
P103
P104
P105
P106
P107

P600
P601
P602
P603
P604
P605

P614
P613
P612
P611
P610
P609
P608

P115
P114
P113
P112
P111
VCC

VCC

VCC
VSS

VSS

VSS
VCL
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P800 109 72 P300/TCK/SWCLK
P801 110 71 P301
VCC 111 70 P302
VSS 112 69 P303
P500 113 68 VCC
P501 114 67 VSS
P502 115 66 P304
P503 116 65 P305
P504 117 64 P306
P505 118 63 P307
P506 119 62 P308
P508 120 61 P309
VCC 121 60 P310
VSS 122 59 P311
P015 123 58 P312
P014 124 57 P200
VREFL 125 56 P201/MD
VREFH 126 R7FA6M2AX3CFB 55 RES
AVCC0 127 54 P208
AVSS0 128 53 P209
VREFL0 129 52 P210
VREFH0 130 51 P211
P009 131 50 P214
P008 132 49 VCC
P007 133 48 VSS
P006 134 47 P313
P005 135 46 P202
P004 136 45 P203
P003 137 44 P204
P002 138 43 P205
P001 139 42 P206
P000 140 41 P207
VSS 141 40 VCC_USB
VCC 142 39 USB_DP
P512 143 38 USB_DM
P511 144 37 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9

XCIN

VCC
P213/XTAL
P400
P401
P402
P403
P404
P405
P406
P700
P701
P702
P703
P704
P705

VCL0

P212/EXTAL
VBATT

XCOUT

P713
P712
P711
P710
P709
P708
P415
P414
P413
P412

P409
P408
P407
VSS

P411
P410

Figure 1.4 Pin assignment for 144-pin LQFP (top view)

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RA6M2 Group 1. Overview

P108/TMS/SWDIO
P109/TDO
P110/TDI
P100
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602

P610
P609
P608
P115
P114
P113
P112
P111
VCC
VSS
VCL
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P500 76 50 P300/TCK/SWCLK
P501 77 49 P301
P502 78 48 P302
P503 79 47 P303
P504 80 46 VCC
P508 81 45 VSS
VCC 82 44 P304
VSS 83 43 P305
P015 84 42 P306
P014 85 41 P307
VREFL 86 40 P200
VREFH 87 39 P201/MD
AVCC0
AVSS0
88
89
R7FA6M2AX3CFP 38
37
RES
P208
VREFL0 90 36 P209
VREFH0 91 35 P210
P008 92 34 P211
P007 93 33 P214
P006 94 32 P205
P005 95 31 P206
P004 96 30 P207
P003 97 29 VCC_USB
P002 98 28 USB_DP
P001 99 27 USB_DM
P000 100 26 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9

VSS
P400
P401
P402
P403
P404
P405
P406

VCL0

P213/XTAL
P212/EXTAL

P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
XCIN

VCC
VBATT

XCOUT

Figure 1.5 Pin assignment for 100-pin LQFP (top view)

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RA6M2 Group 1. Overview

1.7 Pin Lists

Pin number Extbus Timers Communication interfaces Analog HMI

Power, System,

ETHERC (RMII)
Clock, Debug,

ETHERC (MII)
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
LGA145

USBFS,
SDRAM
I/O port

DAC12,
ADC12

CTSU
SDHI
SSIE
CAC

CAN
AGT

PDC
GPT

GPT

RTC

IIC
N13 1 1 - IRQ0 P400 - - AGTIO1 - GTIOC - - SCK4 SCK7 SCL0 - AUDIO ET0_WOL ET0_WOL - ADTRG - - -
6A _A _CLK 1
L11 2 2 - IRQ5- P401 - - - GTETRGA GTIOC - CTX0 CTS4_R TXD7/M SDA0 - - ET0_MDC ET0_MDC - - - - -
DS 6B TS4/SS4 OSI7/SD _A
A7
M13 3 3 CACREF IRQ4- P402 - - AGTIO0/ - - RTCI CRX0 - RXD7/MI - - AUDIO ET0_MDI ET0_MDI - - - - VSYNC
DS AGTIO1 C0 SO7/SC _CLK O O
L7
K11 4 4 - - P403 - - AGTIO0/ - GTIOC RTCI - - CTS7_R - - SSIBC ET0_LINK ET0_LINK SD1DA - - - PIXD7
AGTIO1 3A C1 TS7/SS7 K0_A STA STA T7_B
L12 5 5 - - P404 - - - - GTIOC RTCI - - - - - SSILR ET0_EXO ET0_EXO SD1DA - - - PIXD6
3B C2 CK0/S UT UT T6_B
SIFS0
_A
L13 6 6 - - P405 - - - - GTIOC - - - - - - SSITX ET0_TX_ RMII0_TX SD1DA - - - PIXD5
1A D0_A EN D_EN_B T5_B
J10 7 7 - - P406 - - - - GTIOC - - - - - SSLB3 SSIRX ET0_RX_ RMII0_TX SD1DA - - - PIXD4
1B _C D0_A ER D1_B T4_B
H10 8 - - - P700 - - - - GTIOC - - - - - MISOB - ET0_ETX RMII0_TX SD1DA - - - PIXD3
5A _C D1 D0_B T3_B
K12 9 - - - P701 - - - - GTIOC - - - - - MOSIB - ET0_ETX REF50CK SD1DA - - - PIXD2
5B _C D0 0_B T2_B
K13 10 - - - P702 - - - - GTIOC - - - - - RSPC - ET0_ERX RMII0_RX SD1DA - - - PIXD1
6A KB_C D1 D0_B T1_B
J11 11 - - - P703 - - - - GTIOC - - - - - SSLB0 - ET0_ERX RMII0_RX SD1DA - VCOUT - PIXD0
6B _C D0 D1_B T0_B
H11 12 - - - P704 - - AGTO0 - - - CTX0 - - - SSLB1 - ET0_RX_ RMII0_RX SD1CL - - - HSYNC
_C CLK _ER_B K_B
G11 13 - - - P705 - - AGTIO0 - - - CRX0 - - - SSLB2 - ET0_CRS RMII0_CR SD1CM - - - PIXCLK
_C S_DV_B D_B
J12 14 8 VBATT - - - - - - - - - - - - - - - - - - - - -
J13 15 9 VCL0 - - - - - - - - - - - - - - - - - - - - -
H13 16 10 XCIN - - - - - - - - - - - - - - - - - - - - -
H12 17 11 XCOUT - - - - - - - - - - - - - - - - - - - - -
F12 18 12 VSS - - - - - - - - - - - - - - - - - - - - -
G12 19 13 XTAL IRQ2 P213 - - - GTETRGC GTIOC - - - TXD1/M - - - - - - ADTRG - - -
0A OSI1/SD 1
A1
G13 20 14 EXTAL IRQ3 P212 - - AGTEE1 GTETRGD GTIOC - - - RXD1/MI - - - - - - - - - -
0B SO1/SC
L1
F13 21 15 VCC - - - - - - - - - - - - - - - - - - - - -
G10 22 - - - P713 - - AGTOA0 - GTIOC - - - - - - - - - - - - TS17 -
2A
F11 23 - - - P712 - - AGTOB0 - GTIOC - - - - - - - - - - - - TS16 -
2B
E13 24 - - - P711 - - AGTEE0 - - - - - CTS1_R - - - ET0_TX_ - - - - TS15 -
TS1/SS1 CLK
E12 25 - - - P710 - - - - - - - - SCK1 - - - ET0_TX_ - - - - TS14 -
ER
F10 26 - - IRQ10 P709 - - - - - - - - TXD1/M - - - ET0_ETX - - - - TS13 -
OSI1/SD D2
A1
D13 27 16 CACREF IRQ11 P708 - - - - - - - - RXD1/MI - SSLA3 AUDIO ET0_ETX - - - - TS12 PCKO
SO1/SC _B _CLK D3
L1
E11 28 17 - IRQ8 P415 - - - - GTIOC - USB_ - - - SSLA2 - ET0_TX_ RMII0_TX SD0CD - - TS11 PIXD5
0A VBUS _B EN D_EN_A
EN
D12 29 18 - IRQ9 P414 - - - - GTIOC - - - - - SSLA1 - ET0_RX_ RMII0_TX SD0WP - - TS10 PIXD4
0B _B ER D1_A
E10 30 19 - - P413 - - - GTOUUP - - - CTS0_R - - SSLA0 - ET0_ETX RMII0_TX SD0CL - - TS09 PIXD3
TS0/SS0 _B D1 D0_A K_A
C13 31 20 - - P412 - - AGTEE1 GTOULO - - - SCK0 - - RSPC - ET0_ETX REF50CK SD0CM - - TS08 PIX02
KA_B D0 0_A D_A
D11 32 21 - IRQ4 P411 - - AGTOA1 GTOVUP GTIOC - - TXD0/M CTS3_R - MOSIA - ET0_ERX RMII0_RX SD0DA - - TS07 PIX01
9A OSI0/SD TS3/SS3 _B D1 D0_A T0_A
A0
C12 33 22 - IRQ5 P410 - - AGTOB1 GTOVLO GTIOC - - RXD0/MI SCK3 - MISOA - ET0_ERX RMII0_RX SD0DA - - TS06 PIXD0
9B SO0/SC _B D0 D1_A T1_A
L0
B13 34 23 - IRQ6 P409 - - - GTOWUP GTIOC - USB_ - TXD3/M - - - ET0_RX_ RMII0_RX - - - TS05 HSYNC
10A EXICE OSI3/SD CLK _ER_A
N A3
D10 35 24 - IRQ7 P408 - - - GTOWLO GTIOC - USB_I - RXD3/MI SCL0 - - ET0_CRS RMII0_CR - - - TS04 PIXCLK
10B D SO3/SC _B S_DV_A
L3
A13 36 25 - - P407 - - AGTIO0 - - RTC USB_ CTS4_R - SDA0 SSLB3 - ET0_EXO ET0_EXO - ADTRG - TS03 -
OUT VBUS TS4/SS4 _B _A UT UT 0
B11 37 26 VSS_US - - - - - - - - - - - - - - - - - - - - -
B
A12 38 27 - - - - - - - - - USB_ - - - - - - - - - - - -
DM
B12 39 28 - - - - - - - - - USB_ - - - - - - - - - - - -
DP
A11 40 29 VCC_US - - - - - - - - - - - - - - - - - - - - -
B

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RA6M2 Group 1. Overview

Pin number Extbus Timers Communication interfaces Analog HMI

Power, System,

ETHERC (RMII)
Clock, Debug,

ETHERC (MII)
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
LGA145

USBFS,
SDRAM
I/O port

DAC12,
ADC12

CTSU
SDHI
SSIE
CAC

CAN
AGT

PDC
GPT

GPT

RTC

IIC
C11 41 30 - - P207 A17 - - - - - - - - - SSLB2 - - - - - - TS02 -
_A/QS
SL
B10 42 31 - IRQ0- P206 WAI - - GTIU - - USB_ RXD4/MI - SDA1 SSLB1 SSIDA ET0_LINK ET0_LINK SD0DA - - TS01 -
DS T VBUS SO4/SC _A _A TA0_C STA STA T2_A
EN L4
A10 43 32 CLKOUT IRQ1- P205 A16 - AGTO1 GTIV GTIOC - USB_ TXD4/M CTS9_R SCL1 SSLB0 SSILR ET0_WOL ET0_WOL SD0DA - - TSCA -
DS 4A OVRC OSI4/SD TS9/SS9 _A _A CK0/S T3_A P
URA- A4 SIFS0
DS _C
C10 44 - CACREF - P204 A18 - AGTIO1 GTIW GTIOC - USB_ SCK4 SCK9 SCL0 RSPC SSIBC ET0_RX_ - SD0DA - - TS00 -
4B OVRC _B KB_A K0_C DV T4_A
URB-
DS
A9 45 - - IRQ2- P203 A19 - - - GTIOC - CTX0 CTS2_R TXD9/M - MOSIB - ET0_COL - SD0DA - - TSCA -
DS 5A TS2/SS2 OSI9/SD _A T5_A P
A9
C9 46 - - IRQ3- P202 WR1 - - - GTIOC - CRX0 SCK2 RXD9/MI - MISOB ET0_ERX - SD0DA - - - -
DS /BC1 5B SO9/SC _A D2 T6_A
L9
B9 47 - - - P313 A20 - - - - - - - - - - - ET0_ERX - SD0DA - - - -
D3 T7_A
D9 48 - VSS - - - - - - - - - - - - - - - - - - - - -
D8 49 - VCC - - - - - - - - - - - - - - - - - - - - -
A8 50 33 TCLK - P214 - - - GTIU - - - - - - QSPC - ET0_MDC ET0_MDC SD0CL - - - -
LK K_B
B8 51 34 TDATA0 - P211 CS7 - - GTIV - - - - - - QIO0 - ET0_MDI ET0_MDI SD0CM - - - -
O O D_B
A7 52 35 TDATA1 - P210 CS6 - - GTIW - - - - - - QIO1 - ET0_WOL ET0_WOL SD0CD - - - -
B7 53 36 TDATA2 - P209 CS5 - - GTOVUP - - - - - - QIO2 - ET0_EXO ET0_EXO SD0WP - - - -
UT UT
A6 54 37 TDATA3 - P208 CS4 - - GTOVLO - - - - - - QIO3 - ET0_LINK ET0_LINK SD0DA - - - -
STA STA T0_B
C7 55 38 RES - - - - - - - - - - - - - - - - - - - - -
B6 56 39 MD - P201 - - - - - - - - - - - - - - - - - - -
C8 57 40 - NMI P200 - - - - - - - - - - - - - - - - - - -
C6 58 - - - P312 CS3 CAS AGTOA1 - - - - - CTS3_R - - - - - - - - - -
TS3/SS3
B5 59 - - - P311 CS2 RAS AGTOB1 - - - - - SCK3 - - - - - - - - - -
D7 60 - - - P310 A15 A15 AGTEE1 - - - - - TXD3 - QIO3 - - - - - - - -
A5 61 - - - P309 A14 A14 - - - - - - RXD3 - QIO2 - - - - - - - -
C5 62 - - - P308 A13 A13 - - - - - - - - QIO1 - - - - - - - -
A4 63 41 - - P307 A12 A12 - GTOUUP - - - CTS6 - - QIO0 - - - - - - - -
B4 64 42 - - P306 A11 A11 - GTOULO - - - SCK6 - - QSSL - - - - - - - -
D6 65 43 - IRQ8 P305 A10 A10 - GTOWUP - - - TXD6/M - - QSPC - - - - - - - -
OSI6/SD LK
A6
C4 66 44 - IRQ9 P304 A09 A09 - GTOWLO GTIOC - - RXD6/MI - - - - - - - - - - -
7A SO6/SC
L6
A3 67 45 VSS - - - - - - - - - - - - - - - - - - - - -
B3 68 46 VCC - - - - - - - - - - - - - - - - - - - - -
D5 69 47 - - P303 A08 A08 - - GTIOC - - - - - - - - - - - - - -
7B
A2 70 48 - IRQ5 P302 A07 A07 - GTOUUP GTIOC - - TXD2/M - - SSLB3 - - - - - - - -
4A OSI2/SD _B
A2
C3 71 49 - IRQ6 P301 A06 A06 AGTIO0 GTOULO GTIOC - - RXD2/MI CTS9_R - SSLB2 - - - - - - - -
4B SO2/SC TS9/SS9 _B
L2
B2 72 50 TCK/SW - P300 - - - GTOUUP GTIOC - - - - - SSLB1 - - - - - - - -
CLK 0A_A _B
A1 73 51 TMS/SW - P108 - - - GTOULO GTIOC - - - CTS9_R - SSLB0 - - - - - - - -
DIO 0B_A TS9/SS9 _B
D4 74 52 CLKOUT - P109 - - - GTOVUP GTIOC - CTX1 - TXD9/M - MOSIB - - - - - - - -
/TDO/S 1A_A OSI9/SD _B
WO A9
B1 75 53 TDI IRQ3 P110 - - - GTOVLO GTIOC - CRX1 CTS2_R RXD9/MI - MISOB - - - - - VCOUT - -
1B_A TS2/SS2 SO9/SC _B
L9
C2 76 54 - IRQ4 P111 A05 A05 - - GTIOC - - SCK2 SCK9 - RSPC - - - - - - - -
3A_A KB_B
D3 77 55 - - P112 A04 A04 - - GTIOC - - TXD2/M SCK1 - SSLB0 SSIBC - - - - - - -
3B_A OSI2/SD _B K0_B
A2
C1 78 56 - - P113 A03 A03 - - GTIOC - - RXD2/MI - - - SSILR - - - - - - -
2A SO2/SC CK0/S
L2 SIFS0
_B
E4 79 57 - - P114 A02 A02 - - GTIOC - - - - - - SSIRX - - - - - - -
2B D0_B
E3 80 58 - - P115 A01 A01 - - GTIOC - - - - - - SSITX - - - - - - -
4A D0_B
D2 81 - VCC - - - - - - - - - - - - - - - - - - - - -
D1 82 - VSS - - - - - - - - - - - - - - - - - - - - -
F4 83 59 - - P608 A00/ A00/D - - GTIOC - - - - - - - - - - - - - -
BC0 QM1 4B
E2 84 60 - - P609 CS1 CKE - - GTIOC - CTX1 - - - - - - - - - - - -
5A
F3 85 61 - - P610 CS0 WE - - GTIOC - CRX1 - - - - - - - - - - - -
5B

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RA6M2 Group 1. Overview

Pin number Extbus Timers Communication interfaces Analog HMI

Power, System,

ETHERC (RMII)
Clock, Debug,

ETHERC (MII)
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
LGA145

USBFS,
SDRAM
I/O port

DAC12,
ADC12

CTSU
SDHI
SSIE
CAC

CAN
AGT

PDC
GPT

GPT

RTC

IIC
E1 86 - CLKOUT - P611 - SDCS - - - - - - CTS7_R - - - - - - - - - -
/CACRE TS7/SS7
F
F2 87 - - - P612 D08[ DQ08 - - - - - - SCK7 - - - - - - - - - -
A08/
D08]
F1 88 - - - P613 D09[ DQ09 - - - - - - TXD7 - - - - - - - - - -
A09/
D09]
G3 89 - - - P614 D10[ DQ10 - - - - - - RXD7 - - - - - - - - - -
A10/
D10]
G1 90 62 VCC - - - - - - - - - - - - - - - - - - - - -
G2 91 63 VSS - - - - - - - - - - - - - - - - - - - - -
H1 92 64 VCL - - - - - - - - - - - - - - - - - - - - -
H2 93 - - - P605 D11[ DQ11 - - GTIOC - - - - - - - - - - - - - -
A11/ 8A
D11]
G4 94 - - - P604 D12[ DQ12 - - GTIOC - - - - - - - - - - - - - -
A12/ 8B
D12]
H3 95 - - - P603 D13[ DQ13 - - GTIOC - - - CTS9_R - - - - - - - - - -
A13/ 7A TS9/SS9
D13]
J1 96 65 - - P602 EBC SDCL - - GTIOC - - - TXD9 - - - - - - - - - -
LK K 7B
J2 97 66 - - P601 WR/ DQM0 - - GTIOC - - - RXD9 - - - - - - - - - -
WR0 6A
H4 98 67 CLKOUT - P600 RD - - - GTIOC - - - SCK9 - - - - - - - - - -
/CACRE 6B
F
K2 99 - VCC - - - - - - - - - - - - - - - - - - - - -
K1 100 - VSS - - - - - - - - - - - - - - - - - - - - -
J3 101 68 - KR07 P107 D07[ DQ07 AGTOA0 - GTIOC - - CTS8_R - - - - - - - - - - -
A07/ 8A TS8/SS8
D07]
K3 102 69 - KR06 P106 D06[ DQ06 AGTOB0 - GTIOC - - SCK8 - - SSLA3 - - - - - - - -
A06/ 8B _A
D06]
J4 103 70 - IRQ0/ P105 D05[ DQ05 - GTETRGA GTIOC - - TXD8/M - - SSLA2 - - - - - - - -
KR05 A05/ 1A OSI8/SD _A
D05] A8
L3 104 71 - IRQ1/ P104 D04[ DQ04 - GTETRGB GTIOC - - RXD8/MI - - SSLA1 - - - - - - - -
KR04 A04/ 1B SO8/SC _A
D04] L8
L1 105 72 - KR03 P103 D03[ DQ03 - GTOWUP GTIOC - CTX0 CTS0_R - - SSLA0 - - - - - - - -
A03/ 2A_A TS0/SS0 _A
D03]
M1 106 73 - KR02 P102 D02[ DQ02 AGTO0 GTOWLO GTIOC - CRX0 SCK0 - - RSPC - - - - ADTRG - - -
A02/ 2B_A KA_A 0
D02]
M2 107 74 - IRQ1/ P101 D01[ DQ01 AGTEE0 GTETRGB GTIOC - - TXD0/M CTS1_R SDA1 MOSIA - - - - - - - -
KR01 A01/ 5A OSI0/SD TS1/SS1 _B _A
D01] A0
N1 108 75 - IRQ2/ P100 D00[ DQ00 AGTIO0 GTETRGA GTIOC - - RXD0/MI SCK1 SCL1 MISOA - - - - - - - -
KR00 A00/ 5B SO0/SC _B _A
D00] L0
L2 109 - - - P800 D14[ DQ14 - - - - - - - - - - - - - - - - -
A14/
D14]
N2 110 - - - P801 D15[ DQ15 - - - - - - - - - - - - - - - - -
A15/
D15]
N3 111 - VCC - - - - - - - - - - - - - - - - - - - - -
M3 112 - VSS - - - - - - - - - - - - - - - - - - - - -
K4 113 76 - - P500 - - AGTOA0 GTIU GTIOC - USB_ - - - QSPC - - - SD1CL AN016 IVREF0 - -
11A VBUS LK K_A
EN
M4 114 77 - IRQ11 P501 - - AGTOB0 GTIV GTIOC - USB_ - TXD5/M - QSSL - - - SD1CM AN116 IVREF1 - -
11B OVRC OSI5/SD D_A
URA A5
L4 115 78 - IRQ12 P502 - - - GTIW GTIOC - USB_ - RXD5/MI - QIO0 - - - SD1DA AN017 IVCMP0 - -
12A OVRC SO5/SC T0_A
URB L5
K5 116 79 - - P503 - - - GTETRGC GTIOC - USB_ CTS6_R SCK5 - QIO1 - - - SD1DA AN117 - - -
12B EXICE TS6/SS6 T1_A
N
L5 117 80 - - P504 ALE - - GTETRGD GTIOC - USB_I SCK6 CTS5_R - QIO2 - - - SD1DA AN018 - - -
13A D TS5/SS5 T2_A
K6 118 - - IRQ14 P505 - - - - GTIOC - - RXD6/MI - - QIO3 - - - SD1DA AN118 - - -
13B SO6/SC T3_A
L6
L6 119 - - IRQ15 P506 - - - - - - - TXD6/M - - - - - - SD1CD AN019 - - -
OSI6/SD
A6
N4 120 81 - - P508 - - - - - - - SCK6 SCK5 - - - - - SD1DA AN020 - - -
T3_A
N5 121 82 VCC - - - - - - - - - - - - - - - - - - - - -
M5 122 83 VSS - - - - - - - - - - - - - - - - - - - - -
M6 123 84 - IRQ13 P015 - - - - - - - - - - - - - - - AN006/ DA1/ - -
AN106 IVCMP1
N6 124 85 - - P014 - - - - - - - - - - - - - - - AN005/ DA0/ - -
AN105 IVREF3
M7 125 86 VREFL - - - - - - - - - - - - - - - - - - - - -

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RA6M2 Group 1. Overview

Pin number Extbus Timers Communication interfaces Analog HMI

Power, System,

ETHERC (RMII)
Clock, Debug,

ETHERC (MII)
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
LGA145

USBFS,
SDRAM
I/O port

DAC12,
ADC12

CTSU
SDHI
SSIE
CAC

CAN
AGT

PDC
GPT

GPT

RTC

IIC
N7 126 87 VREFH - - - - - - - - - - - - - - - - - - - - -
L7 127 88 AVCC0 - - - - - - - - - - - - - - - - - - - - -
L8 128 89 AVSS0 - - - - - - - - - - - - - - - - - - - - -
M8 129 90 VREFL0 - - - - - - - - - - - - - - - - - - - - -
N8 130 91 VREFH0 - - - - - - - - - - - - - - - - - - - - -
M9 131 - - IRQ13 P009 - - - - - - - - - - - - - - - AN004 - - -
-DS
N9 132 92 - IRQ12 P008 - - - - - - - - - - - - - - - AN003 - - -
-DS
K7 133 93 - - P007 - - - - - - - - - - - - - - - AN107 - - -
L9 134 94 - IRQ11 P006 - - - - - - - - - - - - - - - AN102 IVCMP2 - -
-DS
K8 135 95 - IRQ10 P005 - - - - - - - - - - - - - - - AN101 IVCMP2 - -
-DS
K9 136 96 - IRQ9- P004 - - - - - - - - - - - - - - - AN100 IVCMP2 - -
DS
K10 137 97 - - P003 - - - - - - - - - - - - - - - AN007 - - -
M10 138 98 - IRQ8- P002 - - - - - - - - - - - - - - - AN002 IVCMP2 - -
DS
N10 139 99 - IRQ7- P001 - - - - - - - - - - - - - - - AN001 IVCMP2 - -
DS
L10 140 100 - IRQ6- P000 - - - - - - - - - - - - - - - AN000 IVCMP2 - -
DS
N11 141 - VSS - - - - - - - - - - - - - - - - - - - - -
N12 142 - VCC - - - - - - - - - - - - - - - - - - - - -
M11 143 - - IRQ14 P512 - - - - GTIOC - CTX1 TXD4/M - SCL2 - - - - - - - - VSYNC
0A OSI4/SD
A4
M12 144 - - IRQ15 P511 - - - - GTIOC - CRX1 RXD4/MI - SDA2 - - - - - - - - PCKO
0B SO4/SC
L4

Note: Some pin names have the added suffix of _A, _B, and _C. When assigning the GPT, IIC, SPI, SSIE, ETHERC (RMII), and
SDHI functionality, select the functional pins with the same suffix.

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RA6M2 Group 2. Electrical Characteristics

2. Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
 VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V
 2.7 ≤ VREFH0/VREFH ≤ AVCC0
 VSS = AVSS0 = VREFL0/VREFL = VSS_USB = 0 V
 Ta = Topr.
Figure 2.1 shows the timing conditions.

For example P100

VOH = VCC × 0.7, VOL = VCC × 0.3

VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30pF

Figure 2.1 Input or output timing measurement conditions

The recommended measurement conditions for the timing specification of each peripheral provided are for the best
peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.

2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings

Parameter Symbol Value Unit
Power supply voltage VCC, VCC_USB *2 -0.3 to +4.0 V
VBATT power supply voltage VBATT -0.3 to +4.0 V
Input voltage (except for 5 V-tolerant ports*1) Vin -0.3 to VCC + 0.3 V
Input voltage (5 V-tolerant ports*1) Vin -0.3 to + VCC + 4.0 (max. 5.8) V
Reference power supply voltage VREFH/VREFH0 -0.3 to AVCC0 + 0.3 V
Analog power supply voltage AVCC0 *2 -0.3 to +4.0 V
Analog input voltage VAN -0.3 to AVCC0 + 0.3 V
Operating temperature*3, *4, *5 Topr -40 to +85 °C
-40 to +105
Storage temperature Tstg -55 to +125 °C

Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.
Note 1. Ports P205, P206, P400, P401, P407 to P415, P511, P512, and P708 to P713 are 5 V tolerant.
Note 2. Connect AVCC0 and VCC_USB to VCC.
Note 3. See section 2.2.1, Tj/Ta Definition.
Note 4. Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
Note 5. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering.

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RA6M2 Group 2. Electrical Characteristics

Table 2.2 Recommended operating conditions

Parameter Symbol Value Min Typ Max Unit
Power supply voltages VCC When USB/SDRAM is not used 2.7 - 3.6 V
When USB/SDRAM is used 3.0 - 3.6 V
VSS - 0 - V
USB power supply voltages VCC_USB - VCC - V
VSS_USB - 0 - V
VBATT power supply voltage VBATT 1.65*2 - 3.6 V
Analog power supply voltages AVCC0*1 - VCC - V
AVSS0 - 0 - V

Note 1. Connect AVCC0 to VCC. When the A/D converter, the D/A converter, or the comparator are not in use, do not leave the
AVCC0, VREFH/VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC,
and the AVSS0 and VREFL/VREFL0 pins to VSS, respectively.
Note 2. Low CL crystal cannot be used below VBATT = 1.8 V.

2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Table 2.3 DC characteristics

Conditions: Products with operating temperature (Ta) -40 to +105°C.

Parameter Symbol Typ Max Unit Test conditions

Permissible junction temperature Tj - 125 °C High-speed mode
Low-speed mode
105*1
Subosc-speed mode

Note: Make sure that Tj = Ta + θja × total power consumption (W),

where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering. If the part number shows the operation temperature to 85°C, then Tj max is 105°C, otherwise, it is 125°C.

2.2.2 I/O VIH, VIL

Table 2.4 I/O VIH, VIL (1 of 2)

Parameter Symbol Min Typ Max Unit
Input voltage Peripheral EXTAL(external clock input), WAIT, SPI (except VIH VCC × 0.8 - - V
(except for function RSPCK)
VIL - - VCC × 0.2
Schmitt trigger pin
input pins) D00 to D15, DQ00 to DQ15 VIH VCC × 0.7 - -
VIL - - VCC × 0.3
ETHERC VIH 2.3 - -
VIL - - VCC × 0.2
IIC (SMBus)*1 VIH 2.1 - -
VIL - - 0.8
IIC (SMBus)*2 VIH 2.1 - VCC + 3.6
(max 5.8)
VIL - - 0.8
Schmitt trigger Peripheral IIC (except for SMBus)*1 VIH VCC × 0.7 - - V
input voltage function
VIL - - VCC × 0.3
pin
ΔVT VCC × 0.05 - -

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RA6M2 Group 2. Electrical Characteristics

Table 2.4 I/O VIH, VIL (2 of 2)

Parameter Symbol Min Typ Max Unit
Schmitt trigger Peripheral IIC (except for SMBus)*2 VIH VCC × 0.7 - VCC + 3.6 V
input voltage function (max 5.8)
pin
VIL - - VCC × 0.3
ΔVT VCC × 0.05 - -
5 V-tolerant ports*3, *7 VIH VCC × 0.8 - VCC + 3.6
(max 5.8)
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
RTCIC0, When using the When VBATT VIH VBATT × 0.8 - VBATT + 0.3
RTCIC1, Battery Backup power supply is
VIL - - VBATT × 0.2
RTCIC2 Function selected
ΔVT VBATT × 0.05 - -
When VCC VIH VCC × 0.8 - Higher
power supply is voltage either
selected VCC + 0.3 V
or
VBATT + 0.3 V
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
When not using the Battery Backup VIH VCC × 0.8 - VCC + 0.3
Function
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
Other input pins*4 VIH VCC × 0.8 - -
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
Ports 5 V-tolerant ports*5, *7 VIH VCC × 0.8 - VCC + 3.6 V
(max 5.8)
VIL - - VCC × 0.2
Other input pins*6 VIH VCC × 0.8 - -
VIL - - VCC × 0.2

Note 1. SCL0_B (P204), SCL1_B, SDA1_B (total 3 pins).

Note 2. SCL0_A, SDA0_A, SCL0_B (P408), SDA0_B, SCL1_A, SDA1_A, SCL2, SDA2 (total 8 pins).
Note 3. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713 (total 22
pins).
Note 4. All input pins except for the peripheral function pins already described in the table.
Note 5. P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713 (total 21 pins).
Note 6. All input pins except for the ports already described in the table.
Note 7. When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur
because 5 V-tolerant ports are electrically controlled so as not to violate the break down voltage.

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2.2.3 I/O IOH, IOL

Table 2.5 I/O IOH, IOL

Parameter Symbol Min Typ Max Unit
Permissible output current Ports P000 to P009, P201 - IOH - - -2.0 mA
(average value per pin)
IOL - - 2.0 mA

Ports P014, P015 - IOH - - -4.0 mA

IOL - - 4.0 mA

Ports P205, P206, P407 to P415, Low drive*1 IOH - - -2.0 mA

P602, P708 to P713 (total 18 pins)
IOL - - 2.0 mA

Middle drive*2 IOH - - -4.0 mA

IOL - - 4.0 mA

High drive*3 IOH - - -20 mA

IOL - - 20 mA

Other output pins*4 Low drive*1 IOH - - -2.0 mA

IOL - - 2.0 mA

Middle drive*2 IOH - - -4.0 mA

IOL - - 4.0 mA

High drive*3 IOH - - -16 mA

IOL - - 16 mA

Permissible output current Ports P000 to P009, P201 - IOH - - -4.0 mA

(max value per pin)
IOL - - 4.0 mA

Ports P014, P015 - IOH - - -8.0 mA

IOL - - 8.0 mA

Ports P205, P206, P407 to P415, Low drive*1 IOH - - -4.0 mA

P602, P708 to P713
(total 18 pins) IOL - - 4.0 mA

Middle drive*2 IOH - - -8.0 mA

IOL - - 8.0 mA

High drive*3 IOH - - -40 mA

IOL - - 40 mA

Other output pins*4 Low drive*1 IOH - - -4.0 mA

IOL - - 4.0 mA

Middle drive*2 IOH - - -8.0 mA

IOL - - 8.0 mA

High drive*3 IOH - - -32 mA

IOL - - 32 mA

Permissible output current Maximum of all output pins ΣIOH (max) - - -80 mA
(maxvalue of total of all pins)
ΣIOL (max) - - 80 mA

Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this
table. The average output current indicates the average value of current measured during 100 μs.
Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected
driving ability is retained in Deep Software Standby mode.
Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected
driving ability is retained in Deep Software Standby mode.
Note 4. Except for P200, which is an input port.

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2.2.4 I/O VOH, VOL, and Other Characteristics

Table 2.6 I/O VOH, VOL, and other characteristics

Parameter Symbol Min Typ Max Unit Test conditions
Output voltage IIC VOL - - 0.4 V IOL = 3.0 mA

VOL - - 0.6 IOL = 6.0 mA

IIC*1 VOL - - 0.4 IOL = 15.0 mA

(ICFER.FMPE = 1)
VOL - 0.4 - IOL = 20.0 mA
(ICFER.FMPE = 1)
ETHERC VOH VCC - 0.5 - - IOH = -1.0 mA

VOL - - 0.4 IOL = 1.0 mA

Ports P205, P206, P407 to P415, VOH VCC - 1.0 - - IOH = -20 mA
P602, P708 to P713 (total of 18 VCC = 3.3 V
pins)*2
VOL - - 1.0 IOL = 20 mA
VCC = 3.3 V
Other output pins VOH VCC - 0.5 - - IOH = -1.0 mA

VOL - - 0.5 IOL = 1.0 mA

Input leakage current RES |Iin| - - 5.0 μA Vin = 0 V

Vin = 5.5 V
Port P200 - - 1.0 Vin = 0 V
Vin = VCC
Three-state leakage 5 V-tolerant ports |ITSI| - - 5.0 μA Vin = 0 V
current (off state) Vin = 5.5 V
Other ports (except for port P200) - - 1.0 Vin = 0 V
Vin = VCC
Input pull-up MOS current Ports P0 to PB Ip -300 - -10 μA VCC = 2.7 to 3.6 V
Vin = 0 V
Input capacitance USB_DP, USB_DM, and ports Cin - - 16 pF Vbias = 0V
P014, P015, P400, P401, P511, Vamp = 20 mV
P512 f = 1 MHz
Ta = 25°C
Other input pins - - 8

Note 1. SCL0_A, SDA0_A (total 2 pins).

Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register.
The selected driving ability is retained in Deep Software Standby mode.

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2.2.5 Operating and Standby Current

Table 2.7 Operating and standby current (1 of 2)

Parameter Symbol Min Typ Max Unit Test conditions
Supply Maximum*2 ICC*3 - - 102*2 mA ICLK = 120 MHz
current*1 PCLKA = 120 MHz*7
CoreMark®*5 - 19 - PCLKB = 60 MHz
Normal mode All peripheral clocks enabled, - 26 - PCLKC = 60 MHz
while (1) code executing from PCLKD = 120 MHz
flash*4 FCLK = 60 MHz
BCLK = 120 MHz
All peripheral clocks disabled, - 12 -
High-speed mode

while (1) code executing from

flash*5, *6
Sleep mode*5, *6 - 10 40
Increase during BGO Data flash P/E - 6 -
operation
Code flash P/E - 8 -
Low-speed mode*5 - 1.3 - ICLK = 1 MHz
Subosc-speed mode*5 - 1.2 - ICLK = 32.768 kHz
Software Standby mode - 1.3 15 Ta ≤ 85°C
- 1.3 24 Ta ≤ 105°C
Power supplied to Standby SRAM and USB resume - 29 67 μA Ta ≤ 85°C
detecting unit
- 29 96 Ta ≤ 105°C
Power not supplied to Power-on reset circuit low - 11.6 32.4 Ta ≤ 85°C
SRAM or USB resume power function disabled
detecting unit - 11.6 40 Ta ≤ 105°C
Deep Software Standby mode

Power-on reset circuit low - 4.9 23.5 Ta ≤ 85°C

power function enabled
- 4.9 31 Ta ≤ 105°C
Increase when the RTC When the low-speed on-chip - 4.4 - -
and AGT are operating oscillator (LOCO) is in use
When a crystal oscillator for - 1.0 - -
low clock loads is in use
When a crystal oscillator for - 1.4 - -
standard clock loads is in use
RTC operating while VCC is off (with When a crystal - 0.9 - VBATT = 1.8 V,
the battery backup function, only the oscillator for low clock VCC = 0 V
RTC and sub-clock oscillator loads is in use
operate) - 1.1 - VBATT = 3.3 V,
VCC = 0 V
When a crystal - 1.0 - VBATT = 1.8 V,
oscillator for standard VCC = 0 V
clock loads is in use
- 1.6 - VBATT = 3.3 V,
VCC = 0 V
Analog During 12-bit A/D conversion AICC - 0.8 1.1 mA -
power
supply During 12-bit A/D conversion with S/H amp - 2.3 3.3 mA -
current ACMPHS (1 unit) - 100 150 µA -
Temperature sensor - 0.1 0.2 mA -
During D/A conversion (per unit) Without AMP output - 0.1 0.2 mA -
With AMP output - 0.6 1.1 mA -
Waiting for A/D, D/A conversion (all units) - 0.9 1.6 mA -
ADC12, DAC12 in standby modes (all units)*8 - 2 8 µA -
Reference During 12-bit A/D conversion (unit 0) AIREFH0 - 70 120 μA -
power
supply Waiting for 12-bit A/D conversion (unit 0) - 0.07 0.5 μA -
current ADC12 in standby modes (unit 0) - 0.07 0.5 µA -
(VREFH0)
Reference During 12-bit A/D conversion (unit 1) AIREFH - 70 120 µA -
power
supply During D/A conversion Without AMP output - 0.1 0.4 mA -
current (per unit)
With AMP ouput - 0.1 0.4 mA -
(VREFH)
Waiting for 12-bit A/D (unit 1), D/A (all units) conversion - 0.07 0.8 µA -
ADC12 unit 1 in standby modes - 0.07 0.8 µA -

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Table 2.7 Operating and standby current (2 of 2)

Parameter Symbol Min Typ Max Unit Test conditions
USB Low speed USB ICCUSBLS - 3.5 6.5 mA VCC_USB
operating
current Full speed USB ICCUSBFS - 4.0 10.0 mA VCC_USB

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOS transistors in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows. (ICLK:PCLKA:PCLKB:PCLKC:PCLKD:BCK:EBCLK = 2:2:1:1:2:1:1)
ICC Max. = 0.61 × f + 29 (maximum operation in High-speed mode)
ICC Typ. = 0.08 × f + 2.6 (normal operation in High-speed mode)
ICC Typ. = 0.1 × f + 1.2 (Low-speed mode)
ICC Max. = 0.09 × f + 29 (Sleep mode).
Note 4. This does not include the BGO operation.
Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 6. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.75 MHz).
Note 7. When using ETHERC, PCLKA frequency is such that PCLKA = ICLK.
Note 8. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-bit A/D Converter 0 Module Stop bit) and
MSTPCRD.MSTPD15 (12-bit A/D Converter 1 Module Stop bit) are in the module-stop state.

100.0

10.0
ICC (mA)

1.0
-40 -20 0 20 40 60 80 100

0.1
Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.2 Temperature dependency in Software Standby mode (reference data)

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1000

100
ICC (uA)

10

1
-40 -20 0 20 40 60 80 100
Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.3 Temperature dependency in Deep Software Standby mode, power supplied to standby SRAM and
USB resume detecting unit (reference data)

100
ICC (uA)

10

1
-40 -20 0 20 40 60 80 100
Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.4 Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB
resume detecting unit, power-on reset circuit low power function disabled (reference data)

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100
ICC (uA)

10

1
-40 -20 0 20 40 60 80 100
Ta (Ԩ)

Average value of the tested middle samples during product evaluation.

Average value of the tested upper-limit samples during product evaluation.

Figure 2.5 Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or USB
resume detecting unit, power-on reset circuit low power function enabled (reference data)

2.2.6 VCC Rise and Fall Gradient and Ripple Frequency

Table 2.8 Rise and fall gradient characteristics

Parameter Symbol Min Typ Max Unit Test conditions
VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.0084 - 20 ms/V -
Voltage monitor 0 reset enabled at startup 0.0084 - - -
SCI/USB boot mode*1 0.0084 - 20 -
VCC falling gradient*2 SfVCC 0.0084 - - ms/V -

Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.
Note 2. This applies when VBATT is used.

Table 2.9 Rise and fall gradient and ripple frequency characteristics
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit
(2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.

Parameter Symbol Min Typ Max Unit Test conditions

Allowable ripple frequency fr (VCC) - - 10 kHz Figure 2.6
Vr (VCC) ≤ VCC × 0.2
- - 1 MHz Figure 2.6
Vr (VCC) ≤ VCC × 0.08
- - 10 MHz Figure 2.6
Vr (VCC) ≤ VCC × 0.06
Allowable voltage change rising dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10%
and falling gradient

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1/fr(VCC)

VCC Vr(VCC)

Figure 2.6 Ripple waveform

2.3 AC Characteristics

2.3.1 Frequency

Table 2.10 Operation frequency value in high-speed mode

Parameter Symbol Min Typ Max Unit
Operation frequency System clock (ICLK*2) f - - 120 MHz
Peripheral module clock (PCLKA)*2 - - 120
Peripheral module clock (PCLKB)*2 - - 60
Peripheral module clock (PCLKC)*2 -*3 - 60
Peripheral module clock (PCLKD)*2 - - 120
Flash interface clock (FCLK)*2 -*1 - 60
External bus clock (BCLK)*2 - - 120
EBCLK pin output - - 60
SDCLK pin output VCC ≥ 3.0 V - - 120

Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.
Note 2. See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,
PCLKD, FCLK, and BCLK frequencies.
Note 3. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

Table 2.11 Operation frequency value in low-speed mode

Parameter Symbol Min Typ Max Unit
Operation frequency System clock (ICLK)*2 f - - 1 MHz
Peripheral module clock (PCLKA)*2 - - 1
Peripheral module clock (PCLKB)*2 - - 1
Peripheral module clock (PCLKC)*2,*3 -*3 - 1
Peripheral module clock (PCLKD)*2 - - 1
Flash interface clock (FCLK)*1, *2 - - 1
External bus clock (BCLK) - - 1
EBCLK pin output - - 1

Note 1. Programming or erasing the flash memory is disabled in low-speed mode.

Note 2. See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,
PCLKD, FCLK, and BCLK frequencies.
Note 3. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

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Table 2.12 Operation frequency value in Subosc-speed mode

Parameter Symbol Min Typ Max Unit
Operation frequency System clock (ICLK)*2 f 29.4 - 36.1 kHz
Peripheral module clock (PCLKA)*2 - - 36.1
Peripheral module clock (PCLKB)*2 - - 36.1
Peripheral module clock (PCLKC)*2,*3 - - 36.1
Peripheral module clock (PCLKD)*2 - - 36.1
Flash interface clock (FCLK)*1, *2 29.4 - 36.1
External bus clock (BCLK)*2 - - 36.1
EBCLK pin output - - 36.1

Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode.

Note 2. See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,
PCLKD, FCLK, and BCLK frequencies.
Note 3. The ADC12 cannot be used.

2.3.2 Clock Timing

Table 2.13 Clock timing except for sub-clock oscillator (1 of 2)

Parameter Symbol Min Typ Max Unit Test conditions
EBCLK pin output cycle time tBcyc 16.6 - - ns Figure 2.7
EBCLK pin output high pulse width tCH 3.3 - - ns
EBCLK pin output low pulse width tCL 3.3 - - ns
EBCLK pin output rise time tCr - - 5.0 ns
EBCLK pin output fall time tCf - - 5.0 ns
SDCLK pin output cycle time tSDcyc 8.33 - - ns
SDCLK pin output high pulse width tCH 1.0 - - ns
SDCLK pin output low pulse width tCL 1.0 - - ns
SDCLK pin output rise time tCr - - 3.0 ns
SDCLK pin output fall time tCf - - 3.0 ns
EXTAL external clock input cycle time tEXcyc 41.66 - - ns Figure 2.8
EXTAL external clock input high pulse width tEXH 15.83 - - ns
EXTAL external clock input low pulse width tEXL 15.83 - - ns
EXTAL external clock rise time tEXr - - 5.0 ns
EXTAL external clock fall time tEXf - - 5.0 ns
Main clock oscillator frequency fMAIN 8 - 24 MHz -
Main clock oscillation stabilization wait time tMAINOSCWT - - -*1 ms Figure 2.9
(crystal) *1
LOCO clock oscillation frequency fLOCO 29.4912 32.768 36.0448 kHz -
LOCO clock oscillation stabilization wait time tLOCOWT - - 60.4 μs Figure 2.10
ILOCO clock oscillation frequency fILOCO 13.5 15 16.5 kHz -
MOCO clock oscillation frequency FMOCO 6.8 8 9.2 MHz -
MOCO clock oscillation stabilization wait time tMOCOWT - - 15.0 μs -

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Table 2.13 Clock timing except for sub-clock oscillator (2 of 2)

Parameter Symbol Min Typ Max Unit Test conditions
HOCO clock oscillator Without FLL fHOCO16 15.78 16 16.22 MHz -20 ≤ Ta ≤ 105°C
oscillation frequency
fHOCO18 17.75 18 18.25
fHOCO20 19.72 20 20.28
fHOCO16 15.71 16 16.29 -40 ≤ Ta ≤ -20°C
fHOCO18 17.68 18 18.32
fHOCO20 19.64 20 20.36
With FLL fHOCO16 15.960 16 16.040 -40 ≤ Ta ≤ 105°C
Sub-clock
fHOCO18 17.955 18 18.045
frequency accuracy
fHOCO20 19.950 20 20.050 is ±50 ppm.
HOCO clock oscillation stabilization wait time*2 tHOCOWT - - 64.7 μs -
FLL stabilization wait time tFLLWT - - 1.8 ms -
PLL clock frequency fPLL 120 - 240 MHz -
PLL clock oscillation stabilization wait time tPLLWT - - 174.9 μs Figure 2.11

Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as
the recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the
recommended value.
After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm
that it is 1, and then start using the main clock oscillator.
Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed
operation.

Table 2.14 Clock timing for the sub-clock oscillator

Parameter Symbol Min Typ Max Unit Test conditions
Sub-clock frequency fSUB - 32.768 - kHz -
Sub-clock oscillation stabilization wait time tSUBOSCWT - - -*1 s Figure 2.12

Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time.
After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after
the sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is
recommended.

tBcyc, tSDcyc
tCH
tCf

EBCLK pin output, SDCLK pin output

tCr
tCL

Figure 2.7 EBCLK and SDCLK output timing

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tEXcyc
tEXH tEXL

EXTAL external clock input VCC × 0.5

tEXr tEXf

Figure 2.8 EXTAL external clock input timing

MOSCCR.MOSTP

Main clock oscillator output

tMAINOSCWT

Main clock

Figure 2.9 Main clock oscillation start timing

LOCOCR.LCSTP

On-chip oscillator output

tLOCOWT

LOCO clock

Figure 2.10 LOCO clock oscillation start timing

PLLCR.PLLSTP

PLL circuit output

tPLLWT

OSCSF.PLLSF

PLL clock

Figure 2.11 PLL clock oscillation start timing

Note: Only operate the PLL after the main clock oscillation has stabilized.

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SOSCCR.SOSTP

Sub-clock oscillator output

tSUBOSCWT
Sub-clock

Figure 2.12 Sub-clock oscillation start timing

2.3.3 Reset Timing

Table 2.15 Reset timing

Test
Parameter Symbol Min Typ Max Unit conditions
RES pulse width Power-on tRESWP 1 - - ms Figure 2.13
Deep Software Standby mode tRESWD 0.6 - - ms Figure 2.14
Software Standby mode, Subosc-speed tRESWS 0.3 - - ms
mode
All other tRESW 200 - - μs
Wait time after RES cancellation tRESWT - 29 32 μs Figure 2.13
Wait time after internal reset cancellation tRESW2 - 320 390 μs -
(IWDT reset, WDT reset, software reset, SRAM parity error
reset, SRAM ECC error reset, bus master MPU error reset, bus
slave MPU error reset, stack pointer error reset)

VCC

RES

tRESWP
Internal reset signal
(low is valid)

tRESWT

Figure 2.13 Power-on reset timing

tRESWD, tRESWS, tRESW

RES

Internal reset signal

(low is valid)

tRESWT

Figure 2.14 Reset input timing

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2.3.4 Wakeup Timing

Table 2.16 Timing of recovery from low power modes

Test
Parameter Symbol Min Typ Max Unit conditions
Recovery time Crystal System clock source is main tSBYMC - 2.4*9 2.8*9 ms Figure 2.15
from Software resonator clock oscillator*2 The division
Standby mode*1 connected ratio of all
System clock source is PLL tSBYPC - 2.7*9 3.2*9 ms
to main oscillators is
with main clock oscillator*3
clock 1.
oscillator
External System clock source is main tSBYEX - 230*9 280*9 μs
clock input clock oscillator*4
to main
System clock source is PLL tSBYPE - 570*9 700*9 μs
clock
with main clock oscillator*5
oscillator
System clock source is sub-clock tSBYSC - 1.2*9 1.3*9 ms
oscillator*8
System clock source is LOCO*8 tSBYLO - 1.2*9 1.4*9 ms
System clock source is HOCO clock tSBYHO - 240*9, *10 300 µs
oscillator*6 *9, *10
System clock source is MOCO clock tSBYMO - 220*9 300*9 µs
oscillator*7
Recovery time from Deep Software Standby mode tDSBY - 0.65 1.0 ms Figure 2.16
Wait time after cancellation of Deep Software Standby mode tDSBYWT 34 - 35 tcyc
Recovery time High-speed mode when system clock tSNZ - 35*9, *10 70 μs Figure 2.17
from Software source is HOCO (20 MHz) *9, *10
Standby mode to
High-speed mode when system clock tSNZ - 11*9 14*9 μs
Snooze mode
source is MOCO (8 MHz)

Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be
determined with the following equation:
Total recovery time = recovery time for an oscillator as the system clock source + the longest oscillation stabilization time of any
oscillators requiring longer stabilization times than the system clock source + 2 LOCO cycles (when LOCO is operating) + 3
SOSC cycles (when Subosc is oscillating and MSTPC0 = 0 (CAC module stop)).
Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For
other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
05h))
Note 3. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h). For other
settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
05h))
Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 01h).
For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 01h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
01h))
Note 5. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 01h). For other
settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 01h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT (MOSCWTCR =
01h))
Note 6. The HOCO frequency is 20 MHz.
Note 7. The MOCO frequency is 8 MHz.
Note 8. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.
Note 9. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time:
STCONR.STCON[1:0] = 00b:16 µs (typical), 34 µs (maximum)
STCONR.STCON[1:0] = 11b:16 µs (typical), 104 µs (maximum).
Note 10. When the SNZCR.RXDREQEN bit is set to 0, 16 μs (typical) or 18 μs (maximum) is added as the HOCO wait time.

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Oscillator
(system clock)
tSBYOSCWT tSBYSEQ
Oscillator
(not the system clock)

ICLK

IRQ
Software Standby mode

tSBYMC, tSBYEX, tSBYPC, tSBYPE,

tSBYPH, tSBYSC, tSBYHO, tSBYLO

When stabilization of the system clock oscillator is slower

Oscillator
(system clock)
tSBYOSCWT tSBYSEQ

Oscillator
(not the system clock)

tSBYOSCWT
ICLK

IRQ

Software Standby mode

tSBYMC, tSBYEX, tSBYPC, tSBYPE,

tSBYPH, tSBYSC, tSBYHO, tSBYLO

When stabilization of an oscillator other than the system clock is slower

Figure 2.15 Software Standby mode cancellation timing

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Oscillator

IRQ

Deep Software Standby

reset
(low is valid)

Internal reset
(low is valid)

Deep Software Standby mode

tDSBY
tDSBYWT

Reset exception handling start

Figure 2.16 Deep Software Standby mode cancellation timing

Oscillator

ICLK(except DTC, SRAM)

ICLK(to DTC, SRAM)*1

PCLK

IRQ

Software Standby mode Snooze mode

tSNZ

Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.17 Recovery timing from Software Standby mode to Snooze mode

2.3.5 NMI and IRQ Noise Filter

Table 2.17 NMI and IRQ noise filter

Parameter Symbol Min Typ Max Unit Test conditions
NMI pulse width tNMIW 200 - - ns NMI digital filter disabled tPcyc × 2 ≤ 200 ns
tPcyc × 2*1 - - tPcyc × 2 > 200 ns
200 - - NMI digital filter enabled tNMICK × 3 ≤ 200 ns
tNMICK × 3.5*2 - - tNMICK × 3 > 200 ns
IRQ pulse width tIRQW 200 - - ns IRQ digital filter disabled tPcyc × 2 ≤ 200 ns
tPcyc × 2*1 - - tPcyc × 2 > 200 ns
200 - - IRQ digital filter enabled tIRQCK × 3 ≤ 200 ns
tIRQCK × 3.5*3 - - tIRQCK × 3 > 200 ns

Note: 200 ns minimum in Software Standby mode.

Note: If the clock source is switched, add 4 clock cycles of the switched source.

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Note 1. tPcyc indicates the PCLKB cycle.

Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock.

NMI

tNMIW

Figure 2.18 NMI interrupt input timing

IRQ

tIRQW

Figure 2.19 IRQ interrupt input timing

2.3.6 Bus Timing

Table 2.18 Bus timing (1 of 2)

Condition 1: When using the CS area controller (CSC).
BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz.
VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF.
EBCLK: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Others: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Condition 2: When using the SDRAM area controller (SDRAMC).

BCLK = SDCLK = 8 to 120 MHz.
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF.
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.
BCLK = SDCLK = 8 to 60 MHz.
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF.
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions
Address delay tAD - 12.5 ns Figure 2.20 to
Figure 2.25
Byte control delay tBCD - 12.5 ns
CS delay tCSD - 12.5 ns
ALE delay time tALED - 12.5 ns
RD delay tRSD - 12.5 ns
Read data setup time tRDS 12.5 - ns
Read data hold time tRDH 0 - ns
WR/WRn delay tWRD - 12.5 ns
Write data delay tWDD - 12.5 ns
Write data hold time tWDH 0 - ns
WAIT setup time tWTS 12.5 - ns Figure 2.26
WAIT hold time tWTH 0 - ns

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Table 2.18 Bus timing (2 of 2)

Condition 1: When using the CS area controller (CSC).
BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz.
VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF.
EBCLK: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Others: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Condition 2: When using the SDRAM area controller (SDRAMC).

BCLK = SDCLK = 8 to 120 MHz.
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF.
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.
BCLK = SDCLK = 8 to 60 MHz.
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF.
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions
Address delay 2 (SDRAM) tAD2 0.8 6.8 ns Figure 2.27 to
Figure 2.30
CS delay 2 (SDRAM) tCSD2 0.8 6.8 ns
DQM delay (SDRAM) tDQMD 0.8 6.8 ns
CKE delay (SDRAM) tCKED 0.8 6.8 ns
Read data setup time 2 (SDRAM) tRDS2 2.9 - ns
Read data hold time 2 (SDRAM) tRDH2 1.5 - ns
Write data delay 2 (SDRAM) tWDD2 - 6.8 ns
Write data hold time 2 (SDRAM) tWDH2 0.8 - ns
WE delay (SDRAM) tWED 0.8 6.8 ns
RAS delay (SDRAM) tRASD 0.8 6.8 ns
CAS delay (SDRAM) tCASD 0.8 6.8 ns

Address cycle Data cycle

Ta1 Ta1 Tan
TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2

EBCLK

tAD
Address bus

tRDS tRDH
tAD tAD
Address bus/
data bus

tALED tALED
Address latch
(ALE)

tRSD tRSD
Data read
(RD)

tCSD
tCSD
Chip select
(CSn)

Figure 2.20 Address/data multiplexed bus read access timing

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Address cycle Data cycle

Ta1 Ta1 Tan
TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2 Tn3

EBCLK

tAD
Address bus

tAD tAD tWDD tWDH

Address bus/
data bus

tALED tALED
Address latch
(ALE)

tWRD tWRD
Data write
(WRm)

tCSD
tCSD
Chip select
(CSn)

Figure 2.21 Address/data multiplexed bus write access timing

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CSRWAIT: 2

RDON:1
CSROFF: 2
CSON: 0

TW1 TW2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD

A20 to A00

1-write strobe mode

tAD tAD

A20 to A01

tBCD tBCD

BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD

CS7 to CS0

tRSD tRSD

RD (read)

tRDS tRDH

D15 to D00 (read)

Figure 2.22 External bus timing for normal read cycle with bus clock synchronized

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CSWWAIT: 2

WRON: 1
WDON: 1*1
CSWOFF: 2

CSON:0 WDOFF: 1*1

TW1 TW2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD

A20 to A00

1-write strobe mode

tAD tAD

A20 to A01

tBCD tBCD

BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD

CS7 to CS0

tWRD tWRD

WR1, WR0, WR (write)

tWDD
tWDH

D15 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.23 External bus timing for normal write cycle with bus clock synchronized

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CSRWAIT:2 CSPRWAIT:2 CSPRWAIT:2 CSPRWAIT:2

RDON:1 RDON:1 RDON:1 RDON:1 CSROFF:2

CSON:0
TW1 TW2 Tend Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD tAD tAD tAD

A20 to A00

1-write strobe mode tAD tAD tAD tAD tAD

A20 to A01

tBCD tBCD
BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode tCSD
tCSD
CS7 to CS0
tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD

RD (Read)

tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH

D15 to D00 (Read)

Figure 2.24 External bus timing for page read cycle with bus clock synchronized

CSWWAIT:2 CSPWWAIT:2 CSPWWAIT:2 CSWOFF:2

WRON:1
WRON:1 WRON:1
WDON:1*1 WDOFF:1*1 WDOFF:1*1 WDOFF:1*1
WDON:1*1 WDON:1*1
CSON:0 TW1 TW2 Tend Tdw1 Tpw1 Tpw2 Tend Tdw1 Tpw1 Tpw2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD tAD tAD

A20 to A00

1-write strobe mode tAD tAD tAD tAD

A20 to A01

tBCD tBCD
BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD
CS7 to CS0

tWRD tWRD tWRD tWRD tWRD tWRD

WR1, WR0, WR (write)

tWDD tWDD tWDD

tWDH tWDH tWDH
D15 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.25 External bus timing for page write cycle with bus clock synchronized

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CSRWAIT:3
CSWWAIT:3

TW1 TW2 TW3 (Tend) Tend Tn1 Tn2

EBCLK

A20 to A00

CS7 to CS0

RD (read)

WR (write)

External wait

tWTS tWTH tWTS tWTH

WAIT

Figure 2.26 External bus timing for external wait control

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SDRAM command ACT RD PRA

SDCLK

tAD2 tAD2 tAD2 tAD2

A15 to A00 Row Column address

address

tAD2 tAD2 tAD2 tAD2

AP*1 PRA
command
tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2

SDCS
tRASD tRASD tRASD tRASD

RAS
tCASD tCASD

CAS
tWED tWED

WE

(High)
CKE

tDQMD

DQMn

tRDS2 tRDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.27 SDRAM single read timing

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SDRAM command ACT WR PRA

SDCLK

tAD2 tAD2 tAD2 tAD2

A15 to A00 Row Column address

address

tAD2 tAD2 tAD2 tAD2

AP*1 PRA
command
tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2

SDCS
tRASD tRASD tRASD tRASD

RAS
tCASD tCASD

CAS
tWED tWED tWED tWED

WE

(High)
CKE

tDQMD

DQMn
tWDD2 tWDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.28 SDRAM single write timing

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MRS
SDRAM command
SDCLK

t AD2 t AD2

A15 to A00

t AD2 t AD2

AP*1

t CSD2 t CSD2

SDCS
t RASD t RASD

RAS
t CASD t CASD

CAS
t WED t WED

WE

(High)

CKE

DQMn

(Hi-Z)

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.29 SDRAM mode register set timing

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SDRAM command Ts (RFA) (RFS) (RFX) (RFA)

SDCLK

t AD2 t AD2

A15 to A00

t AD2 t AD2

AP*1

t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2

SDCS

t RASD t RASD t RASD t RASD t RASD t RASD t RASD

RAS
t CASD t CASD t CASD t CASD t CASD t CASD t CASD

CAS

(High)

WE
t CKED t CKED

CKE

t DQMD t DQMD

DQMn

(Hi-Z)
DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.30 SDRAM self-refresh timing

2.3.7 I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing

Table 2.19 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (1 of 2)
GPT32 Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test
Parameter Symbol Min Max Unit conditions
I/O ports Input data pulse width tPRW 1.5 - tPcyc Figure 2.31
POEG POEG input trigger pulse width tPOEW 3 - tPcyc Figure 2.32

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Table 2.19 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (2 of 2)
GPT32 Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test
Parameter Symbol Min Max Unit conditions
GPT32 Input capture pulse width Single edge tGTICW 1.5 - tPDcyc Figure 2.33
Dual edge 2.5 -
GTIOCxY output skew Middle drive buffer tGTISK *1 - 4 ns Figure 2.34
(x = 0 to 7, Y= A or B)
High drive buffer - 4
GTIOCxY output skew Middle drive buffer - 4
(x = 8 to 13, Y = A or B)
High drive buffer - 4
GTIOCxY output skew Middle drive buffer - 6
(x = 0 to 13, Y = A or B)
High drive buffer - 6
OPS output skew tGTOSK - 5 ns Figure 2.35
GTOUUP, GTOULO, GTOVUP,
GTOVLO, GTOWUP, GTOWLO
GPT(PWM GTIOCxY_Z output skew tHRSK*2 - 2.0 ns Figure 2.36
Delay (x = 0 to 3, Y = A or B, Z = A)
Generation
Circuit)
AGT AGTIO, AGTEE input cycle tACYC*3 100 - ns Figure 2.37
AGTIO, AGTEE input high width, low width tACKWH, 40 - ns
tACKWL
AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 - ns
ADC12 ADC12 trigger input pulse width tTRGW 1.5 - tPcyc Figure 2.38

KINT KRn (n = 00 to 07) pulse width tKR 250 - ns Figure 2.39

Note: tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.

Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not
guaranteed.
Note 2. The load is 30 pF.
Note 3. Constraints on input cycle:
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
When switching the source clock: tPcyc × 6 < tACYC should be satisfied.

Port

tPRW

Figure 2.31 I/O ports input timing

POEG input trigger

tPOEW

Figure 2.32 POEG input trigger timing

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Input capture

tGTICW

Figure 2.33 GPT32 input capture timing

PCLKD

Output delay

GPT32 output

tGTISK

Figure 2.34 GPT32 output delay skew

PCLKD

Output delay

GPT32 output

tGTOSK

Figure 2.35 GPT32 output delay skew for OPS

PCLKD

Output delay

GPT32 output
(PWM delay
generation circuit)

tHRSK

Figure 2.36 GPT32 (PWM Delay Generation Circuit) output delay skew

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tACYC

tACKWL tACKWH

AGTIO, AGTEE
(input)

tACYC2

AGTIO, AGTO,
AGTOA, AGTOB
(output)

Figure 2.37 AGT input/output timing

ADTRG0,
ADTRG1
tTRGW

Figure 2.38 ADC12 trigger input timing

KR00 to KR07

tKR

Figure 2.39 Key interrupt input timing

2.3.8 PWM Delay Generation Circuit Timing

Table 2.20 PWM Delay Generation Circuit timing

Parameter Min Typ Max Unit Test conditions
Operation frequency 80 - 120 MHz -
Resolution - 260 - ps PCLKD = 120 MHz
DNL*1 - ±2.0 - LSB -

Note 1. This value normalizes the differences between lines in 1-LSB resolution.

2.3.9 CAC Timing

Table 2.21 CAC timing

Test
Parameter Symbol Min Typ Max Unit conditions
CAC CACREF input pulse width tPBcyc ≤ tcac*2 tCACREF 4.5 × tcac + 3 × tPBcyc - - ns -
tPBcyc > tcac*2 5 × tcac + 6.5 × tPBcyc - - ns

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Note 1. tPBcyc: PCLKB cycle.

Note 2. tcac: CAC count clock source cycle.

2.3.10 SCI Timing

Table 2.22 SCI timing (1)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SCK0 to SCK9.
For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test
Parameter Symbol Min Max Unit*1 conditions
SCI Input clock cycle Asynchronous tScyc 4 - tPcyc Figure 2.40
Clock 6 -
synchronous
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr - 5 ns
Input clock fall time tSCKf - 5 ns
Output clock cycle Asynchronous tScyc 6 - tPcyc
Clock 4 -
synchronous
Output clock pulse width tSCKW 0.4 0.6 tScyc
Output clock rise time tSCKr - 5 ns
Output clock fall time tSCKf - 5 ns
Transmit data delay Clock tTXD - 25 ns Figure 2.41
synchronous
Receive data setup time Clock tRXS 15 - ns
synchronous
Receive data hold time Clock tRXH 5 - ns
synchronous

Note 1. tPcyc: PCLKA cycle.

tSCKW tSCKr tSCKf

SCKn
(n = 0 to 9)

tScyc

Figure 2.40 SCK clock input/output timing

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SCKn

tTXD

TxDn

tRXS tRXH

RxDn

n = 0 to 9

Figure 2.41 SCI input/output timing in clock synchronous mode

Table 2.23 SCI timing (2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SCK0 to SCK9.
For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Test
Parameter Symbol Min Max Unit conditions
Simple SCK clock cycle output tSPcyc 4 (PCLKA ≤ 60 MHz) 65536 tPcyc Figure 2.42
SPI (master) 8 (PCLKA > 60 MHz)
SCK clock cycle input (slave) - 6 (PCLKA ≤ 60 MHz) 65536
12 (PCLKA > 60 MHz)
SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc
SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc
SCK clock rise and fall time tSPCKr, tSPCKf - 20 ns
Data input setup time tSU 33.3 - ns Figure 2.43 to
Figure 2.46
Data input hold time tH 33.3 - ns
SS input setup time tLEAD 1 - tSPcyc
SS input hold time tLAG 1 - tSPcyc
Data output delay tOD - 33.3 ns
Data output hold time tOH -10 - ns
Data rise and fall time tDr, tDf - 16.6 ns
SS input rise and fall time tSSLr, tSSLf - 16.6 ns
Slave access time tSA - 4 (PCLKA ≤ 60 MHz) tPcyc Figure 2.46
8 (PCLKA > 60 MHz)
Slave output release time tREL - 5 (PCLKA ≤ 60 MHz) tPcyc
10 (PCLKA > 60 MHz)

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tSPCKWH tSPCKr tSPCKf

VOH VOH VOH VOH

SCKn
master select VOL VOL VOL
output
tSPCKWL
tSPcyc

tSPCKWH tSPCKr tSPCKf

VIH VIH VIH VIH

SCKn
slave select input VIL VIL VIL
tSPCKWL
(n = 0 to 9) tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Figure 2.42 SCI simple SPI mode clock timing

SCKn
CKPOL = 0
output

SCKn
CKPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tDr, tDf tOH tOD

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

(n = 0 to 9)

Figure 2.43 SCI simple SPI mode timing for master when CKPH = 1

SCKn
CKPOL = 1
output

SCKn
CKPOL = 0
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

(n = 0 to 9)

Figure 2.44 SCI simple SPI mode timing for master when CKPH = 0

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tTD
SSn
input
tLEAD tLAG

SCKn
CKPOL = 0
input

SCKn
CKPOL = 1
input
tSA tOH tOD tREL

MISOn
MSB OUT DATA LSB OUT MSB IN MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

(n = 0 to 9)

Figure 2.45 SCI simple SPI mode timing for slave when CKPH = 1

tTD

SSn
input
tLEAD tLAG

SCKn
CKPOL = 1
input

SCKn
CKPOL = 0
input
tSA tOH tOD tREL

MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

(n = 0 to 9)

Figure 2.46 SCI simple SPI mode timing for slave when CKPH = 0

Table 2.24 SCI timing (3) (1 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions
Simple IIC SDA input rise time tSr - 1000 ns Figure 2.47
(Standard mode)
SDA input fall time tSf - 300 ns
SDA input spike pulse removal time tSP 0 4 × tIICcyc ns
Data input setup time tSDAS 250 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb*1 - 400 pF

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Table 2.24 SCI timing (3) (2 of 2)

Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit Test conditions
Simple IIC SDA input rise time tSr - 300 ns Figure 2.47
(Fast mode)
SDA input fall time tSf - 300 ns
SDA input spike pulse removal time tSP 0 4 × tIICcyc ns
Data input setup time tSDAS 100 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb*1 - 400 pF

Note: tIICcyc: IIC internal reference clock (IICφ) cycle.

Note 1. Cb indicates the total capacity of the bus line.

VIH
SDAn
VIL

tSr tSf
tSP

SCLn

P*1 S*1 Sr*1 P*1

(n = 0 to 9)
tSDAH tSDAS

Note 1. S, P, and Sr indicate the following: Test conditions:

S: Start condition VIH = VCC × 0.7, VIL = VCC × 0.3
P: Stop condition VOL = 0.6 V, IOL = 6 mA
Sr: Restart condition

Figure 2.47 SCI simple IIC mode timing

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2.3.11 SPI Timing

Table 2.25 SPI timing

Conditions:
For RSPCKA and RSPCKB pins, high drive output is selected with the Port Drive Capability bit in the PmnPFS register.
For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter Symbol Min Max Unit*1 Test conditions*2

SPI RSPCK clock cycle Master tSPcyc 2 (PCLKA  60 MHz) 4096 tPcyc Figure 2.48
4 (PCLKA > 60 MHz) C = 30 pF
Slave 4 4096
RSPCK clock high Master tSPCKWH (tSPcyc - tSPCKr - - ns
pulse width tSPCKf) / 2 - 3
Slave 2 × tPcyc -
RSPCK clock low pulse Master tSPCKWL (tSPcyc - tSPCKr - - ns
width tSPCKf) / 2 - 3
Slave 2 × tPcyc -
RSPCK clock rise and Master tSPCKr, - 5 ns
fall time tSPCKf
Slave - 1 µs
Data input setup time Master tSU 4 - ns Figure 2.49 to
Figure 2.54
Slave 5 -
C = 30 pF
Data input hold time Master tHF 0 - ns
(PCLKA division ratio
set to 1/2)
Master tH tPcyc -
(PCLKA division ratio
set to a value other
than 1/2)
Slave tH 20 -
SSL setup time Master tLEAD N × tSPcyc - 10*3 N× ns
tSPcyc +
100*3
Slave 6 x tPcyc - ns
SSL hold time Master tLAG N × tSPcyc - 10 *4 N× ns
tSPcyc +
100*4
Slave 6 x tPcyc - ns
Data output delay Master tOD - 6.3 ns
Slave - 20
Data output hold time Master tOH 0 - ns
Slave 0 -
Successive Master tTD tSPcyc + 2 × tPcyc 8× ns
transmission delay tSPcyc +
2 × tPcyc
Slave 6 × tPcyc
MOSI and MISO rise Output tDr, tDf - 5 ns
and fall time
Input - 1 μs
SSL rise and fall time Output tSSLr, - 5 ns
tSSLf
Input - 1 μs
Slave access time tSA - 2 x tPcyc ns Figure 2.53 and
+ 28 Figure 2.54
C = 30PF
Slave output release time tREL - 2 x tPcyc
+ 28

Note 1. tPcyc: PCLKA cycle.

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Note 2. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SPI
interface, the AC portion of the electrical characteristics is measured for each group.
Note 3. N is set to an integer from 1 to 8 by the SPCKD register.
Note 4. N is set to an integer from 1 to 8 by the SSLND register.

tSPCKWH tSPCKr tSPCKf

SPI

VOH VOH VOH VOH

RSPCKn
master select output VOL VOL VOL
tSPCKWL
tSPcyc

tSPCKWH tSPCKr tSPCKf

VIH VIH VIH VIH

RSPCKn
slave select input VIL VIL VIL
tSPCKWL
n = A or B tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Figure 2.48 SPI clock timing

SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tDr, tDf tOH tOD

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

n = A or B

Figure 2.49 SPI timing for master when CPHA = 0

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SPI tTD

SSLn0 to
SSLn3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tHF tHF

MISOn MSB IN DATA LSB IN MSB IN

input

tDr, tDf tOH tOD

MOSIn MSB OUT DATA LSB OUT IDLE MSB OUT

output
n = A or B

Figure 2.50 SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2

SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

n = A or B

Figure 2.51 SPI timing for master when CPHA = 1

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SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tHF tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

n = A or B

Figure 2.52 RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2

SPI
tTD
SSLn0
input
tLEAD tLAG

RSPCKn
CPOL = 0
input

RSPCKn
CPOL = 1
input
tSA tOH tOD tREL

MISOn
MSB OUT DATA LSB OUT MSB IN MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

n = A or B

Figure 2.53 SPI timing for slave when CPHA = 0

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RA6M2 Group 2. Electrical Characteristics

SPI
tTD

SSLAn
input
tLEAD tLAG

RSPCKn
CPOL = 0
input

RSPCKn
CPOL = 1
input
tSA tOH tOD tREL

MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output

tSU tH tDr, tDf

MOSIn
input MSB IN DATA LSB IN MSB IN

n = A or B

Figure 2.54 SPI timing for slave when CPHA = 1

2.3.12 QSPI Timing

Table 2.26 QSPI timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit*1 Test conditions
QSPI QSPCK clock cycle tQScyc 2 48 tPcyc Figure 2.55
QSPCK clock high pulse width tQSWH tQScyc × 0.4 - ns
QSPCK clock low pulse width tQSWL tQScyc × 0.4 - ns
Data input setup time tSu 8 - ns Figure 2.56
Data input hold time tIH 0 - ns
QSSL setup time tLEAD (N+0.5) x (N+0.5) x ns
tQscyc - 5 *2 tQscyc +100 *2
QSSL hold time tLAG (N+0.5) x (N+0.5) x ns
tQscyc - 5 *3 tQscyc +100 *3
Data output delay tOD - 4 ns
Data output hold time tOH -3.3 - ns
Successive transmission delay tTD 1 16 tQScyc

Note 1. tPcyc: PCLKA cycle.

Note 2. N is set to 0 or 1 in SFMSLD.
Note 3. N is set to 0 or 1 in SFMSHD.

tQSWH tQSWL

QSPCLK output

tQScyc

Figure 2.55 QSPI clock timing

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tTD

QSSL
output
tLEAD tLAG

QSPCLK
output

tSU tH

QIO0-3
MSB IN DATA LSB IN
input

tOH tOD

QIO0-3
MSB OUT DATA LSB OUT IDLE
output

Figure 2.56 Transmit and receive timing

2.3.13 IIC Timing

Table 2.27 IIC timing (1) (1 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.

Test
Parameter Symbol Min*1 Max Unit conditions*3
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 - ns Figure 2.57
(Standard mode,
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns
SMBus)
ICFER.FMPE = 0 SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns
SCL, SDA input rise time tSr - 1000 ns
SCL, SDA input fall time tSf - 300 ns
SCL, SDA input spike pulse removal tSP 0 1 (4) × tIICcyc ns
time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 300 - ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc - ns
wakeup function is enabled + 300
START condition input hold time tSTAH tIICcyc + 300 - ns
when wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + - ns
when wakeup function is enabled 300
Repeated START condition input tSTAS 1000 - ns
setup time
STOP condition input setup time tSTOS 1000 - ns
Data input setup time tSDAS tIICcyc + 50 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb - 400 pF

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Table 2.27 IIC timing (1) (2 of 2)

(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.

Test
Parameter Symbol Min*1 Max Unit conditions*3
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 600 - ns Figure 2.57
(Fast mode)
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns
SCL, SDA input rise time tSr 20 × (external pullup 300 ns
voltage/5.5V)*2
SCL, SDA input fall time tSf 20 × (external pullup 300 ns
voltage/5.5V)*2
SCL, SDA input spike pulse removal tSP 0 1 (4) × tIICcyc ns
time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 300 - ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc - ns
wakeup function is enabled + 300
START condition input hold time tSTAH tIICcyc + 300 - ns
when wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + - ns
when wakeup function is enabled 300
Repeated START condition input tSTAS 300 - ns
setup time
STOP condition input setup time tSTOS 300 - ns
Data input setup time tSDAS tIICcyc + 50 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb - 400 pF

Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note 2. Only supported for SCL0_A, SDA0_A, SCL2, and SDA2.
Note 3. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC
interface, the AC portion of the electrical characteristics is measured for each group.

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Table 2.28 IIC timing (2)

Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.

Test
Parameter Symbol Min*1,*2 Max Unit conditions
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 240 - ns Figure 2.57
(Fast-mode+)
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 120 - ns
ICFER.FMPE = 1
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 120 - ns
SCL, SDA input rise time tSr - 120 ns
SCL, SDA input fall time tSf - 120 ns
SCL, SDA input spike pulse removal tSP 0 1 (4) × tIICcyc ns
time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 120 - ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc - ns
wakeup function is enabled + 120
Start condition input hold time when tSTAH tIICcyc + 120 - ns
wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + - ns
when wakeup function is enabled 120
Restart condition input setup time tSTAS 120 - ns
Stop condition input setup time tSTOS 120 - ns
Data input setup time tSDAS tIICcyc + 30 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb - 550 pF

Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note 2. Cb indicates the total capacity of the bus line.

VIH
SDA0 to SDA2
VIL

tBUF
tSCLH
tSTAH tSTAS tSP tSTOS

SCL0 to SCL2

P*1 S*1 Sr*1 P*1

tSCLL
tSf tSr tSDAS
tSCL
tSDAH
Test conditions:
Note 1. S, P, and Sr indicate the following:
VIH = VCC × 0.7, VIL = VCC × 0.3
S: Start condition
VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0)
P: Stop condition
VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1)
Sr: Restart condition

Figure 2.57 I2C bus interface input/output timing

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RA6M2 Group 2. Electrical Characteristics

2.3.14 SSIE Timing

Table 2.29 SSIE timing

(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface,
the AC portion of the electrical characteristics is measured for each group.

Target specification
Parameter Symbol Min. Max. Unit Comments
SSIBCK0 Cycle Master tO 80 - ns Figure 2.58
Slave tI 80 - ns
High level/ low level Master tHC/tLC 0.35 - tO
Slave 0.35 - tI
Rising time/falling time Master tRC/tFC - 0.15 tO / tI
Slave - 0.15 tO / tI
SSILRCK0/SSIFS0, Input set up time Master tSR 12 - ns Figure 2.60,
SSITXD0, SSIRXD0, Figure 2.61
Slave 12 - ns
SSIDATA0
Input hold time Master tHR 8 - ns
Slave 15 - ns
Output delay time Master tDTR -10 5 ns
Slave 0 20 ns Figure 2.60,
Figure 2.61
Output delay time from Slave tDTRW - 20 ns Figure 2.62*1
SSILRCK0/SSIFS0
change
GTIOC1A, Cycle tEXcyc 20 - ns Figure 2.59
AUDIO_CLK
High level/ low level tEXL/ 0.4 0.6 tEXcyc
tEXH

Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to
generate transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA0 pin.

tHC tRC tFC

SSIBCK0 tLC

tO , tI

Figure 2.58 SSIE clock input/output timing

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RA6M2 Group 2. Electrical Characteristics

tEXcyc

tEXH tEXL

GTIOC1A,
AUDIO_CLK 1/2 VCC
(input)

tEXf tEXr

Figure 2.59 Clock input timing

SSIBCK0
(Input or Output)

SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)

tSR tHR

SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)

tDTR

Figure 2.60 SSIE data transmit and receive timing when SSICR.BCKP = 0

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SSIBCK0
(Input or Output)

SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)

tSR tHR

SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)

tDTR

Figure 2.61 SSIE data transmit and receive timing when SSICR.BCKP = 1

SSILRCK0/SSIFS0 (input)

SSITXD0,
SSIDATA0 (output)

tDTRW

MSB bit output delay after SSILRCK0/SSIFS0 change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.

Figure 2.62 SSIE data output delay after SSILRCK0/SSIFS0 change

2.3.15 SD/MMC Host Interface Timing

Table 2.30 SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Clock duty ratio is 50%.

Parameter Symbol Min Max Unit Test conditions*1

SDnCLK clock cycle TSDCYC 20 - ns Figure 2.63
SDnCLK clock high pulse width TSDWH 6.5 - ns
SDnCLK clock low pulse width TSDWL 6.5 - ns
SDnCLK clock rise time TSDLH - 3 ns
SDnCLK clock fall time TSDHL - 3 ns
SDnCMD/SDnDATm output data delay TSDODLY -6 5 ns
SDnCMD/SDnDATm input data setup TSDIS 4 - ns
SDnCMD/SDnDATm input data hold TSDIH 2 - ns

Note 1. Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership.

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For the SD/MMC Host interface, the AC portion of the electrical characteristics is measured for each group.

T SDCYC
T SDW L T SD W H
SDnCLK
(output) T SDLH
T SD H L T SD O D LY(m ax) T SDO D LY(m in)
SDnCM D/SDnDATm
(output)
T SDIS T SD IH
SDnCM D/SDnDATm
(input)

n = 0, 1, m = 0 to 7

Figure 2.63 SD/MMC Host Interface signal timing

2.3.16 ETHERC Timing

Table 2.31 ETHERC timing

Conditions: ETHERC (RMII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:
ET0_MDC, ET0_MDIO.
For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
ETHERC (MII): Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Test
Parameter Symbol Min Max Unit conditions*3
ETHERC REF50CK0 cycle time Tck 20 - ns Figure 2.64 to
(RMII) Figure 2.67
REF50CK0 frequency, typical 50 MHz - - 50 + 100 ppm MHz
REF50CK0 duty - 35 65 %
REF50CK0 rise/fall time Tckr/ckf 0.5 3.5 ns
RMII_xxxx*1 output delay Tco 2.5 12.0 ns
RMII_xxxx*2 setup time Tsu 3 - ns
RMII_xxxx*2 hold time Thd 1 - ns
RMII_xxxx*1, *2 rise/fall time Tr/Tf 0.5 4 ns
ET0_WOL output delay tWOLd 1 23.5 ns Figure 2.68
ETHERC ET0_TX_CLK cycle time tTcyc 40 - ns -
(MII)
ET0_TX_EN output delay tTENd 1 20 ns Figure 2.69
ET0_ETXD0 to ET_ETXD3 output delay tMTDd 1 20 ns
ET0_CRS setup time tCRSs 10 - ns
ET0_CRS hold time tCRSh 10 - ns
ET0_COL setup time tCOLs 10 - ns Figure 2.70
ET0_COL hold time tCOLh 10 - ns
ET0_RX_CLK cycle time tTRcyc 40 - ns -
ET0_RX_DV setup time tRDVs 10 - ns Figure 2.71
ET0_RX_DV hold time tRDVh 10 - ns
ET0_ERXD0 to ET_ERXD3 setup time tMRDs 10 - ns
ET0_ERXD0 to ET_ERXD3 hold time tMRDh 10 - ns
ET0_RX_ER setup time tRERs 10 - ns Figure 2.72
ET0_RX_ER hold time tRESh 10 - ns
ET0_WOL output delay tWOLd 1 23.5 ns Figure 2.73

Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0.

Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER.

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Note 3. The following pins must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group
membership. For the ETHERC (RMII) Host interface, the AC portion of the electrical characteristics is measured for each
group.
REF50CK0_A, REF50CK0_B, RMII0_xxxx_A, RMII0_xxxx_B.

Tck

90% Tckr
REF50CK0 50%
Tckf
10%

Tco Tsu Thd

Tr Tf
90%
*1 Change Change
RMII_xxxx 50% Change in
in signal Signal Signal in signal
signal level
level level
10%

Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0, RMII_CRS_DV, RMII_RXD1, RMII_RXD0,

RMII_RX_ER

Figure 2.64 REF50CK0 and RMII signal timing

TCK

REF50CK0

TCO

RMII_TXD_EN

TCO

RMII_TXD1,
Preamble SFD DATA CRC
RMII_TXD0

Figure 2.65 RMII transmission timing

REF50CK0

Tsu Thd

RMII_CRS_DV
Thd
Tsu

RMII_RXD1,
Preamble DATA CRC
RMII_RXD0

SFD
RMII_RX_ER
L

Figure 2.66 RMII reception timing in normal operation

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REF50CK0

RMII_CRS_DV

RMII_RXD1,
Preamble SFD DATA xxxx
RMII_RXD0
Thd
Tsu

RMII_RX_ER

Figure 2.67 RMII reception timing when an error occurs

REF50CK0

tWOLd

ET0_WOL

Figure 2.68 WOL output timing for RMII

ET0_TX_CLK
tTENd

ET0_TX_EN
tMTDd

ET0_ETXD[3:0] Preamble SFD DATA CRC

ET0_TX_ER
tCRSs tCRSh

ET0_CRS

ET0_COL

Figure 2.69 MII transmission timing in normal operation

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ET0_TX_CLK

ET0_TX_EN

ET0_ETXD[3:0] Preamble JAM

ET0_TX_ER

ET0_CRS tCOLs tCOLh

ET0_COL

Figure 2.70 MII transmission timing when a conflict occurs

ET0_RX_CLK

tRDVs tRDVh

ET0_RX_DV
tMRDh
tMRDs

ET0_ERXD[3:0] Preamble SFD DATA CRC

ET0_RX_ER

Figure 2.71 MII reception timing in normal operation

ET0_RX_CLK

ET0_RX_DV

Preamble SFD DATA xxxx

ET0_ERXD[3:0]
tRERh
tRERs

ET0_RX_ER

Figure 2.72 MII reception timing when an error occurs

ET0_RX_CLK

tWOLd

ET0_WOL

Figure 2.73 WOL output timing for MII

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RA6M2 Group 2. Electrical Characteristics

2.3.17 PDC Timing

Table 2.32 PDC timing

Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

Test
Parameter Symbol Min Max Unit conditions
PDC PIXCLK input cycle time tPIXcyc 37 - ns Figure 2.74
PIXCLK input high pulse width tPIXH 10 - ns
PIXCLK input low pulse width tPIXL 10 - ns
PIXCLK rise time tPIXr - 5 ns
PIXCLK fall time tPIXf - 5 ns
PCKO output cycle time tPCKcyc 2 × tPBcyc - ns Figure 2.75
PCKO output high pulse width tPCKH (tPCKcyc - tPCKr - tPCKf)/2 - 3 - ns
PCKO output low pulse width tPCKL (tPCKcyc - tPCKr - tPCKf)/2 - 3 - ns
PCKO rise time tPCKr - 5 ns
PCKO fall time tPCKf - 5 ns
VSYNV/HSYNC input setup time tSYNCS 10 - ns Figure 2.76
VSYNV/HSYNC input hold time tSYNCH 5 - ns
PIXD input setup time tPIXDS 10 - ns
PIXD input hold time tPIXDH 5 - ns

Note 1. tPBcyc: PCLKB cycle.

tPIXcyc

tPIXH tPIXf

PIXCLK input

tPIXr
tPIXL

Figure 2.74 PDC input clock timing

tPCKcyc

tPCKH tPCKf

PCKO pin output

tPCKr
tPCKL

Figure 2.75 PDC output clock timing

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PIXCLK

tSYNCS tSYNCH
VSYNC

tSYNCS tSYNCH

HSYNC

tPIXDS tPIXDH
PIXD7 to PIXD0

Figure 2.76 PDC AC timing

2.4 USB Characteristics

2.4.1 USBFS Timing

Table 2.33 USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, UCLK = 48 MHz

Parameter Symbol Min Typ Max Unit Test conditions

Input Input high voltage VIH 2.0 - - V -
characteristics
Input low voltage VIL - - 0.8 V -
Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM |
Differential common-mode VCM 0.8 - 2.5 V -
range
Output Output high voltage VOH 2.8 - 3.6 V IOH = -200 μA
characteristics
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA
Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.77
Rise time tLR 75 - 300 ns
Fall time tLF 75 - 300 ns
Rise/fall time ratio tLR / tLF 80 - 125 % tLR/ tLF
Pull-up and pull- USB_DP and USB_DM pull- Rpd 14.25 - 24.80 kΩ -
down down resistance in host
characteristics controller mode

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tLR tLF

Figure 2.77 USB_DP and USB_DM output timing in low-speed mode

Observation
point
USB_DP

200 pF to
600 pF 3.6 V
27 
1.5 K
USB_DM

200 pF to
600 pF

Figure 2.78 Test circuit in low-speed mode

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Table 2.34 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, UCLK = 48 MHz

Parameter Symbol Min Typ Max Unit Test conditions

Input Input high voltage VIH 2.0 - - V -
characteristics
Input low voltage VIL - - 0.8 V -
Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM |
Differential common-mode VCM 0.8 - 2.5 V -
range
Output Output high voltage VOH 2.8 - 3.6 V IOH = -200 μA
characteristics
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA
Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.79
Rise time tLR 4 - 20 ns
Fall time tLF 4 - 20 ns
Rise/fall time ratio tLR / tLF 90 - 111.11 % tFR/ tFF
Output resistance ZDRV 28 - 44 Ω USBFS: Rs = 27 Ω included
Pull-up and pull- DM pull-up resistance in Rpu 0.900 - 1.575 kΩ During idle state
down device controller mode
1.425 - 3.090 kΩ During transmission and
characteristics
reception
USB_DP and USB_DM pull- Rpd 14.25 - 24.80 kΩ -
down resistance in host
controller mode

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tFR tFF

Figure 2.79 USB_DP and USB_DM output timing in full-speed mode

Observation
point
USB_DP

50 pF
27 

USB_DM

50 pF

Figure 2.80 Test circuit in full-speed mode

2.5 ADC12 Characteristics

Table 2.35 A/D conversion characteristics for unit 0 (1 of 2)

Conditions: PCLKC = 1 to 60 MHz
Parameter Min Typ Max Unit Test conditions
Frequency 1 - 60 MHz -

Analog input capacitance - - 30 pF -

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Table 2.35 A/D conversion characteristics for unit 0 (2 of 2)

Conditions: PCLKC = 1 to 60 MHz
Parameter Min Typ Max Unit Test conditions
Quantization error - ±0.5 - LSB -

Resolution - - 12 Bits -

Channel-dedicated Conversion time*1 Permissible signal 1.06 - - μs  Sampling of channel-

sample-and-hold (operation at source impedance (0.4 + 0.25)*2 dedicated sample-and-hold
circuits in use*3 PCLKC = 60 MHz) Max. = 1 kΩ circuits in 24 states
(AN000 to AN002)  Sampling in 15 states
Offset error - ±1.5 ±3.5 LSB AN000 to AN002 = 0.25 V

Full-scale error - ±1.5 ±3.5 LSB AN000 to AN002 =

VREFH0- 0.25 V
Absolute accuracy - ±2.5 ±5.5 LSB -

DNL differential nonlinearity error - ±1.0 ±2.0 LSB -

INL integral nonlinearity error - ±1.5 ±3.0 LSB -

Holding characteristics of sample-and hold - - 20 μs -

circuits
Dynamic range 0.25 - VREFH0 V -
- 0.25
Channel-dedicated Conversion time*1 Permissible signal 0.48 (0.267)*2 - - μs Sampling in 16 states
sample-and-hold (operation at source impedance
circuits not in use PCLKC = 60 MHz) Max. = 1 kΩ
(AN000 to AN002)
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

High-precision Conversion time*1 Permissible signal 0.48 (0.267)*2 - - μs Sampling in 16 states

channels (operation at source impedance
(AN003 to AN007) PCLKC = 60 MHz) Max. = 1 kΩ
Max. = 400 Ω 0.40 (0.183)*2 - - μs Sampling in 11 states
VCC = AVCC0 = 3.0 to 3.6 V
3.0 V ≤ VREFH0 ≤ AVCC0
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

Normal-precision Conversion time*1 Permissible signal 0.88 (0.667)*2 - - μs Sampling in 40 states

channels (Operation at source impedance
(AN016 to AN020) PCLKC = 60 MHz) Max. = 1 kΩ
Offset error - ±1.0 ±5.5 LSB -

Full-scale error - ±1.0 ±5.5 LSB -

Absolute accuracy - ±2.0 ±7.5 LSB -

DNL differential nonlinearity error - ±0.5 ±4.5 LSB -

INL integral nonlinearity error - ±1.0 ±5.5 LSB -

Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage
are stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Note 3. When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.37.

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Table 2.36 A/D conversion characteristics for unit 1

Conditions: PCLKC = 1 to 60 MHz
Parameter Min Typ Max Unit Test conditions
Frequency 1 - 60 MHz -

Analog input capacitance - - 30 pF -

Quantization error - ±0.5 - LSB -

Resolution - - 12 Bits -

Channel-dedicated Conversion time*1 Permissible signal 1.06 - - μs  Sampling of channel-

sample-and-hold (operation at source impedance (0.4 + 0.25)*2 dedicated sample-and-hold
circuits in use*3 PCLKC = 60 MHz) Max. = 1 kΩ circuits in 24 states
(AN100 to AN102)  Sampling in 15 states
Offset error - ±1.5 ±3.5 LSB AN100 to AN102 = 0.25 V

Full-scale error - ±1.5 ±3.5 LSB AN100 to AN102 =

VREFH - 0.25 V
Absolute accuracy - ±2.5 ±5.5 LSB -

DNL differential nonlinearity error - ±1.0 ±2.0 LSB -

INL integral nonlinearity error - ±1.5 ±3.0 LSB -

Holding characteristics of sample-and hold - - 20 μs -

circuits
Dynamic range 0.25 - VREFH - V -
0.25
Channel-dedicated Conversion time*1 Permissible signal 0.48 - - μs Sampling in 16 states
sample-and-hold (Operation at source impedance (0.267)*2
circuits not in use PCLKC = 60 MHz) Max. = 1 kΩ
(AN100 to AN102)
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

High-precision Conversion time*1 Permissible signal 0.48 - - μs Sampling in 16 states

channels (Operation at source impedance (0.267)*2
(AN105 to AN107) PCLKC = 60 MHz) Max. = 1 kΩ
Max. = 400 Ω 0.40 - - μs Sampling in 11 states
(0.183)*2 VCC = AVCC0 = 3.0 to 3.6 V
3.0 V ≤ VREFH ≤ AVCC0
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

Normal-precision Conversion time*1 Permissible signal 0.88 - - μs Sampling in 40 states

channels (Operation at source impedance (0.667)*2
(AN116 to AN118) PCLKC = 60 MHz) Max. = 1 kΩ
Offset error - ±1.0 ±5.5 LSB -

Full-scale error - ±1.0 ±5.5 LSB -

Absolute accuracy - ±2.0 ±7.5 LSB -

DNL differential nonlinearity error - ±0.5 ±4.5 LSB -

INL integral nonlinearity error - ±1.0 ±5.5 LSB -

Note: These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage
are stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Note 3. When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.37.

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Table 2.37 A/D conversion characteristics for simultaneous use of channel-dedicated sample-and-hold
circuits in unit0 and unit1
Conditions: PCLKC = 30/60 MHz

Parameter Min Typ Max Test conditions

Channel-dedicated sample-and-hold circuits in use Offset error - ±1.5 ±5.0  PCLKC = 60 MHz
with continious sampling function enabled  Sampling in 15 states
Full-scale error - ±2.5 ±5.0
(AN000 to AN002)
Absolute accuracy - ±4.0 ±8.0
Channel-dedicated sample-and-hold circuits in use Offset error - ±1.5 ±5.0
with continious sampling function enabled
Full-scale error - ±2.5 ±5.0
(AN100 to AN102)
Absolute accuracy - ±4.0 ±8.0
Channel-dedicated sample-and-hold circuits in use Offset error - ±1.5 ±3.5  PCLKC = 30 MHz
with continious sampling function enabled  Sampling in 7 states
Full-scale error - ±1.5 ±3.5
(AN000 to AN002)
Absolute accuracy - ±3.0 ±5.5
Channel-dedicated sample-and-hold circuits in use Offset error - ±1.5 ±3.5
with continious sampling function enabled
Full-scale error - ±1.5 ±3.5
(AN100 to AN102)
Absolute accuracy - ±3.0 ±5.5

Note: When simultaneously using channel-dedicated sample-and-hold circuits in unit0 and unit1, setting the ADSHMSR.SHMD bit to
1 is recommended.

Table 2.38 A/D internal reference voltage characteristics

Parameter Min Typ Max Unit Test conditions
A/D internal reference voltage 1.13 1.18 1.23 V -
Sampling time 4.15 - - μs -

FFFh
Full-scale error

Integral nonlinearity
error (INL)
A/D converter
output code Ideal line of actual A/D
Actual A/D conversion conversion characteristic
characteristic

Ideal A/D conversion

characteristic Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

000h Offset error

0 Analog input voltage VREFH0
(full-scale)

Figure 2.81 Illustration of ADC12 characteristic terms

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RA6M2 Group 2. Electrical Characteristics

Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the
analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D
conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical
A/D conversion characteristics.

Integral nonlinearity error (INL)

Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.

Differential nonlinearity error (DNL)

Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion
characteristics and the width of the actual output code.

Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.

Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

2.6 DAC12 Characteristics

Table 2.39 D/A conversion characteristics

Parameter Min Typ Max Unit Test conditions
Resolution - - 12 Bits -
Without output amplifier
Absolute accuracy - - ±24 LSB Resistive load 2 MΩ
INL - ±2.0 ±8.0 LSB Resistive load 2 MΩ
DNL - ±1.0 ±2.0 LSB -
Output impedance - 8.5 - kΩ -
Conversion time - - 3.0 μs Resistive load 2 MΩ,
Capacitive load 20 pF
Output voltage range 0 - VREFH V -
With output amplifier
INL - ±2.0 ±4.0 LSB -
DNL - ±1.0 ±2.0 LSB -
Conversion time - - 4.0 μs -
Resistive load 5 - - kΩ -
Capacitive load - - 50 pF -
Output voltage range 0.2 - VREFH - 0.2 V -

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2.7 TSN Characteristics

Table 2.40 TSN characteristics

Parameter Symbol Min Typ Max Unit Test conditions
Relative accuracy - - ±1.0 - °C -
Temperature slope - - 4.0 - mV/°C -
Output voltage (at 25°C) - - 1.24 - V -
Temperature sensor start time tSTART - - 30 μs -
Sampling time - 4.15 - - μs -

2.8 OSC Stop Detect Characteristics

Table 2.41 Oscillation stop detection circuit characteristics

Parameter Symbol Min Typ Max Unit Test conditions
Detection time tdr - - 1 ms Figure 2.82

Main clock
tdr
OSTDSR.OSTDF

MOCO clock

ICLK

Figure 2.82 Oscillation stop detection timing

2.9 POR and LVD Characteristics

Table 2.42 Power-on reset circuit and voltage detection circuit characteristics (1 of 2)
Test
Parameter Symbol Min Typ Max Unit conditions
Voltage detection Power-on reset DPSBYCR.DEEPCUT[1:0] = VPOR 2.5 2.6 2.7 V Figure 2.83
level (POR) 00b or 01b
DPSBYCR.DEEPCUT[1:0] = 1.8 2.25 2.7
11b
Voltage detection circuit (LVD0) Vdet0_1 2.84 2.94 3.04 Figure 2.84
Vdet0_2 2.77 2.87 2.97
Vdet0_3 2.70 2.80 2.90
Voltage detection circuit (LVD1) Vdet1_1 2.89 2.99 3.09 Figure 2.85
Vdet1_2 2.82 2.92 3.02
Vdet1_3 2.75 2.85 2.95
Voltage detection circuit (LVD2) Vdet2_1 2.89 2.99 3.09 Figure 2.86
Vdet2_2 2.82 2.92 3.02
Vdet2_3 2.75 2.85 2.95

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Table 2.42 Power-on reset circuit and voltage detection circuit characteristics (2 of 2)
Test
Parameter Symbol Min Typ Max Unit conditions
Internal reset time Power-on reset time tPOR - 4.5 - ms Figure 2.83
LVD0 reset time tLVD0 - 0.51 - Figure 2.84
LVD1 reset time tLVD1 - 0.38 - Figure 2.85
LVD2 reset time tLVD2 - 0.38 - Figure 2.86
Minimum VCC down time*1 tVOFF 200 - - μs Figure 2.83,
Figure 2.84
Response delay tdet - - 200 μs Figure 2.83 to
Figure 2.86
LVD operation stabilization time (after LVD is enabled) td(E-A) - - 10 μs Figure 2.85,
Figure 2.86
Hysteresis width (LVD1 and LVD2) VLVH - 70 - mV

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR,
Vdet1, and Vdet2 for POR and LVD.

tVOFF

VPOR
VCC

Internal reset signal

(active-low)

tdet tPOR tdet tdet tPOR

Figure 2.83 Power-on reset timing

tVOFF

VCC Vdet0

Internal reset signal

(active-low)
tdet tdet tLVD0

Figure 2.84 Voltage detection circuit timing (Vdet0)

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RA6M2 Group 2. Electrical Characteristics

tVOFF

VCC Vdet1 VLVH

LVCMPCR.LVD1E

td(E-A)
LVD1
Comparator output

LVD1CR0.CMPE

LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0

tdet tdet tLVD1

When LVD1CR0.RN = 1

tLVD1

Figure 2.85 Voltage detection circuit timing (Vdet1)

tVOFF

VCC Vdet2 VLVH

LVCMPCR.LVD2E

td(E-A)
LVD2
Comparator output

LVD2CR0.CMPE

LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0

tdet tdet tLVD2

When LVD2CR0.RN = 1

tLVD2

Figure 2.86 Voltage detection circuit timing (Vdet2)

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2.10 VBATT Characteristics

Table 2.43 Battery backup function characteristics

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.65 to 3.6 V*1
Parameter Symbol Min Typ Max Unit Test conditions
Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.70 V Figure 2.87
Lower-limit VBATT voltage for power supply VBATTSW 2.70 - - V
switching caused by VCC voltage drop
VCC-off period for starting power supply switching tVOFFBATT 200 - - μs

Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the
voltage level for switching to battery backup (VDETBATT).
Note 1. Low CL crystal cannot be used below VBATT = 1.8 V.

tVOFFBATT

VDETBATT
VCC

VBATT VBATTSW

Backup power
VCC supply VBATT supply VCC supply
area

Figure 2.87 Battery backup function characteristics

2.11 CTSU Characteristics

Table 2.44 CTSU characteristics

Parameter Symbol Min Typ Max Unit Test conditions
External capacitance connected to TSCAP pin Ctscap 9 10 11 nF -
TS pin capacitive load Cbase - - 50 pF -
Permissible output high current ΣIoH - - -40 mA When the mutual
capacitance method
is applied

2.12 ACMPHS Characteristics

Table 2.45 ACMPHS characteristics

Parameter Symbol Min Typ Max Unit Test conditions
Reference voltage range VREF 0 - AVCC0 V -
Input voltage range VI 0 - AVCC0 V -
Output delay*1 Td - 50 100 ns VI = VREF ± 100 mV
Internal reference voltage Vref 1.13 1.18 1.23 V -

Note 1. This value is the internal propagation delay.

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2.13 Flash Memory Characteristics

2.13.1 Code Flash Memory Characteristics

Table 2.46 Code flash memory characteristics

Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK ≤ 60 MHz

FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz

Test
Parameter Symbol Min Typ Max Min Typ Max Unit conditions
Programming time 128-byte tP128 - 0.75 13.2 - 0.34 6.0 ms
NPEC  100 times
8-KB tP8K - 49 176 - 22 80 ms
32-KB tP32K - 194 704 - 88 320 ms
Programming time 128-byte tP128 - 0.91 15.8 - 0.41 7.2 ms
NPEC > 100 times
8-KB tP8K - 60 212 - 27 96 ms
32-KB tP32K - 234 848 - 106 384 ms
Erasure time 8-KB tE8K - 78 216 - 43 120 ms
NPEC  100 times
32-KB tE32K - 283 864 - 157 480 ms
Erasure time 8-KB tE8K - 94 260 - 52 144 ms
NPEC > 100 times
32-KB tE32K - 341 1040 - 189 576 ms
Reprogramming/erasure cycle*4 NPEC 10000*1 - - 10000*1 - - Times
Suspend delay during programming tSPD - - 264 - - 120 μs
First suspend delay during erasure in tSESD1 - - 216 - - 120 μs
suspend priority mode
Second suspend delay during tSESD2 - - 1.7 - - 1.7 ms
erasure in suspend priority mode
Suspend delay during erasure in tSEED - - 1.7 - - 1.7 ms
erasure priority mode
Forced stop command tFD - - 32 - - 20 μs
Data hold time*2 tDRP 10*2, *3 - - 10*2, *3 - - Years
30*2, *3 - - 30*2, *3 - - Ta = +85°C

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1
to the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),
erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different
addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. Overwriting is prohibited.

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RA6M2 Group 2. Electrical Characteristics

• Suspension during programming

FCU command Program Suspend

tSPD

FSTATR0.FRDY Ready Not Ready Ready

Programming pulse Programming

• Suspension during erasure in suspend priority mode

FCU command Erase Suspend Resume Suspend

tSESD1 tSESD2

FSTATR0.FRDY Ready Not Ready Ready Not Ready

Erasure pulse Erasing Erasing

• Suspension during erasure in erasure priority mode

FCU command Erase Suspend

tSEED

FSTATR0.FRDY Ready Not Ready Ready

Erasure pulse Erasing

• Forced Stop

FACI command Forced Stop

tFD

FSTATR.FRDY Not Ready Ready

Figure 2.88 Suspension and forced stop timing for flash memory programming and erasure

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2.13.2 Data Flash Memory Characteristics

Table 2.47 Data flash memory characteristics

Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK ≤ 60 MHz

FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz

Test
Parameter Symbol Min Typ Max Min Typ Max Unit conditions
Programming time 4-byte tDP4 - 0.36 3.8 - 0.16 1.7 ms
8-byte tDP8 - 0.38 4.0 - 0.17 1.8
16-byte tDP16 - 0.42 4.5 - 0.19 2.0
Erasure time 64-byte tDE64 - 3.1 18 - 1.7 10 ms
128-byte tDE128 - 4.7 27 - 2.6 15
256-byte tDE256 - 8.9 50 - 4.9 28
Blank check time 4-byte tDBC4 - - 84 - - 30 μs
Reprogramming/erasure cycle*1 NDPEC 125000*2 - - 125000*2 - - -
Suspend delay during 4-byte tDSPD - - 264 - - 120 μs
programming
8-byte - - 264 - - 120
16-byte - - 264 - - 120
First suspend delay 64-byte tDSESD1 - - 216 - - 120 μs
during erasure in
128-byte - - 216 - - 120
suspend priority mode
256-byte - - 216 - - 120
Second suspend delay 64-byte tDSESD2 - - 300 - - 300 μs
during erasure in
128-byte - - 390 - - 390
suspend priority mode
256-byte - - 570 - - 570
Suspend delay during 64-byte tDSEED - - 300 - - 300 μs
erasing in erasure
128-byte - - 390 - - 390
priority mode
256-byte - - 570 - - 570
Forced stop command tFD - - 32 - - 20 μs
Data hold time*3 tDRP 10*3,*4 - - 10*3,*4 - - Year
30*3,*4 - - 30*3,*4 - - Ta = +85°C

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),
erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different
addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1
to the minimum value.
Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 4. This result is obtained from reliability testing.

2.14 Boundary Scan

Table 2.48 Boundary scan characteristics (1 of 2)

Test
Parameter Symbol Min Typ Max Unit conditions
TCK clock cycle time tTCKcyc 100 - - ns Figure 2.89
TCK clock high pulse width tTCKH 45 - - ns
TCK clock low pulse width tTCKL 45 - - ns
TCK clock rise time tTCKr - - 5 ns
TCK clock fall time tTCKf - - 5 ns

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RA6M2 Group 2. Electrical Characteristics

Table 2.48 Boundary scan characteristics (2 of 2)

Test
Parameter Symbol Min Typ Max Unit conditions
TMS setup time tTMSS 20 - - ns Figure 2.90
TMS hold time tTMSH 20 - - ns
TDI setup time tTDIS 20 - - ns
TDI hold time tTDIH 20 - - ns
TDO data delay tTDOD - - 40 ns
Boundary scan circuit startup time*1 TBSSTUP tRESWP - - - Figure 2.91
Note 1. Boundary scan does not function until the power-on reset becomes negative.

tTCKcyc
tTCKH

TCK tTCKf

tTCKr
tTCKL

Figure 2.89 Boundary scan TCK timing

TCK

tTMSS tTMSH

TMS

tTDIS tTDIH

TDI

tTDOD

TDO

Figure 2.90 Boundary scan input/output timing

VCC

RES

tBSSTUP Boundary scan

(= tRESWP) execute

Figure 2.91 Boundary scan circuit startup timing

R01DS0357EJ0120 Rev.1.20 Page 89 of 98

Dec 23, 2022
RA6M2 Group 2. Electrical Characteristics

2.15 Joint Test Action Group (JTAG)

Table 2.49 JTAG

Test
Parameter Symbol Min Typ Max Unit conditions
TCK clock cycle time tTCKcyc 40 - - ns Figure 2.89
TCK clock high pulse width tTCKH 15 - - ns
TCK clock low pulse width tTCKL 15 - - ns
TCK clock rise time tTCKr - - 5 ns
TCK clock fall time tTCKf - - 5 ns
TMS setup time tTMSS 8 - - ns Figure 2.90
TMS hold time tTMSH 8 - - ns
TDI setup time tTDIS 8 - - ns
TDI hold time tTDIH 8 - - ns
TDO data delay time tTDOD - - 20 ns

tTCKcyc

tTCKH

TCK tTCKf

tTCKr
tTCKL

Figure 2.92 JTAG TCK timing

TCK

tTMSS tTMSH

TMS

tTDIS tTDIH

TDI

tTDOD

TDO

Figure 2.93 JTAG input/output timing

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Dec 23, 2022
RA6M2 Group 2. Electrical Characteristics

2.16 Serial Wire Debug (SWD)

Table 2.50 SWD

Test
Parameter Symbol Min Typ Max Unit conditions
SWCLK clock cycle time tSWCKcyc 40 - - ns Figure 2.94
SWCLK clock high pulse width tSWCKH 15 - - ns
SWCLK clock low pulse width tSWCKL 15 - - ns
SWCLK clock rise time tSWCKr - - 5 ns
SWCLK clock fall time tSWCKf - - 5 ns
SWDIO setup time tSWDS 8 - - ns Figure 2.95
SWDIO hold time tSWDH 8 - - ns
SWDIO data delay time tSWDD 2 - 28 ns

tSWCKcyc

tSWCKH

SWCLK

tSWCKL

Figure 2.94 SWD SWCLK timing

SWCLK

tSWDS tSWDH

SWDIO
(Input)

tSWDD

SWDIO
(Output)

tSWDD

SWDIO
(Output)

tSWDD

SWDIO
(Output)

Figure 2.95 SWD input/output timing

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Dec 23, 2022
RA6M2 Group 2. Electrical Characteristics

2.17 Embedded Trace Macro Interface (ETM)

Table 2.51 ETM

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Test
Parameter Symbol Min Typ Max Unit conditions
TCLK clock cycle time tTCLKcyc 33.3 - - ns Figure 2.96
TCLK clock high pulse width tTCLKH 13.6 - - ns
TCLK clock low pulse width tTCLKL 13.6 - - ns
TCLK clock rise time tTCLKr - - 3 ns
TCLK clock fall time tTCLKf - - 3 ns
TDATA[3:0] output setup time tTRDS 3.5 - - ns Figure 2.97
TDATA[3:0] output hold time tTRDH 2.5 - - ns

tTCLKcyc

tTCLKH

TCLK tTCLKf

tTCLKr
tTCLKL

Figure 2.96 ETM TCLK timing

TCLK

tTRDS tTRDH tTRDS tTRDH

TDATA[3:0]

Figure 2.97 ETM output timing

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RA6M2 Group Appendix 1. Package Dimensions

Appendix 1.Package Dimensions

For information on the latest version of the package dimensions or mountings, go to “Packages” on the Renesas
Electronics Corporation website.

JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-TFLGA145-7x7-0.50 PTLG0145KA-A 145F0G 0.1g

φb1
φ M S AB
w S B

φb
D φ M S AB
w S A
ZD e
A
A

e
M
L
K
J
H B
E

G
F
E
D
C
B
A

ZE
1 2 3 4 5 6 7 8 9 10 11 12 13 Reference Dimension in Millimeters
x4 y S Symbol
v
Min Nom Max
Index mark D 7.0
S
(Laser mark)
E 7.0
v 0.15
w 0.20
A 1.05
e 0.5
b 0.21 0.25 0.29
b1 0.29 0.34 0.39
x 0.08
y 0.08
ZD 0.5
ZE 0.5

Figure 1.1 145-pin LGA

R01DS0357EJ0120 Rev.1.20 Page 93 of 98

Dec 23, 2022
RA6M2 Group Appendix 1. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFQFP144-20x20-0.50 PLQP0144KA-B — 1.2

HD Unit: mm
*1 D

108 73

109 72

HE
E
144 *2
37

1 36 NOTE 4
NOTE)
Index area
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
NOTE 3
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
F LOCATED WITHIN THE HATCHED AREA.
S 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Reference Dimensions in millimeters

*3 Symbol
e bp Min Nom Max
y S M
D 19.9 20.0 20.1
E 19.9 20.0 20.1
A2  1.4 
HD 21.8 22.0 22.2
HE 21.8 22.0 22.2
A   1.7
0.25
A2

A1 0.05  0.15
A

bp 0.17 0.20 0.27

T

c 0.09  0.20
A1

Lp
T 0q 3.5q 8q
L1 e  0.5 
x   0.08
Detail F
y   0.
Lp 0.45 0.6 0.75
L1  1.0 

© 2016 Renesas Electronics Corporation. All rights reserved.

Figure 1.2 144-pin LQFP

R01DS0357EJ0120 Rev.1.20 Page 94 of 98

Dec 23, 2022
RA6M2 Group Appendix 1. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFQFP100-14x14-0.50 PLQP0100KB-B — 0.6

HD
Unit: mm
*1 D

75 51

76 50

HE
E
*2

100
26

1 25 NOTE 4
Index area NOTE)
NOTE 3 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
F
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
S
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Reference Dimensions in millimeters

y S Symbol
*3 Min Nom Max
e bp
M
D 13.9 14.0 14.1
E 13.9 14.0 14.1
A2  1.4 
HD 15.8 16.0 16.2
HE 15.8 16.0 16.2
0.25

A   1.7
A2
A

A1 0.05  0.15
T

bp 0.15 0.20 0.27

A1

c 0.09  0.20
Lp
T 0q 3.5q 8q
L1
e  0.5 
Detail F
x   0.08
y   0.08
Lp 0.45 0.6 0.75
L1  1.0 

© 2015 Renesas Electronics Corporation. All rights reserved.

Figure 1.3 100-pin LQFP

R01DS0357EJ0120 Rev.1.20 Page 95 of 98

Dec 23, 2022
 Revision History

RA6M2 Group Revision History

Revision History RA6M2 Group Datasheet

Rev. Date Chapter Summary

1.00 Oct 8, 2019 - First Edition issued
1.10 May 14, 2021 - Second Edition issued
1.20 Dec 23, 2022 - Third Edition issued

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All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in
this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and
trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no
part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated,
transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior
written consent from Renesas.
Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.
CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
Magic Packet™ is a trademark of Advanced Micro Devices, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective
holders.

R01DS0357EJ0120 Rev.1.20 Page 96 of 98

Dec 23, 2022
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.

1. Precaution against Electrostatic Discharge (ESD)

A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
Notice
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(Rev.5.0-1 October 2020)

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