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Assignment N0.7 - GDTR Writeup

The document discusses an experiment to display the values of GDTR, LDTR, IDTR, and MSW registers to detect protected mode on an x86/64 CPU. It provides background on real mode and protected mode, describes the registers, and presents an algorithm to read the register values and display them.

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Gaurav Shinde
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58 views4 pages

Assignment N0.7 - GDTR Writeup

The document discusses an experiment to display the values of GDTR, LDTR, IDTR, and MSW registers to detect protected mode on an x86/64 CPU. It provides background on real mode and protected mode, describes the registers, and presents an algorithm to read the register values and display them.

Uploaded by

Gaurav Shinde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Department of Computer Engineering Microprocessor Laboratory (2019 course)

Experiments No:7
Subject:MPL Department :Computer Engg. Class: SE COMP

Title: display the values of GDTR, LDTR, IDTR,TR and MSW Registers

Problem Statement: Write X86/64 ALP to detect protected mode and display the values of
GDTR, LDTR, IDTR,TR and MSW Registers also identify CPU type using CPUID instruction.

Objective:

● To understand assembly language programming instruction


set To understand different assembler directives with example
● To apply instruction set for implementing X86/64 bit assembly language programs

Outcomes: On completion of this practical ,students will be able to


C218.1: Understand and apply various addressing modes and instruction set to implement
assembly language programs

Hardware Requirement: NA
Software Requirement: OS:Ubuntu Assembler: NASM version 2.16.07 Linker: ld

Theory Contents : Real Mode:


Real mode, also called real address mode, is an operating mode of all x86-compatible CPUs.
Real mode is characterized by a 20-bit segmented memory address space (giving exactly 1
MiB of addressable memory) and unlimited direct software access to all addressable memory,
Department of Computer Engineering Microprocessor Laboratory (2019 course)

I/O addresses and peripheral hardware. Real mode provides no support for memory protection,
multitasking, or code privilege levels.
Protected Mode:
In computing, protected mode, also called protected virtual address mode is an operational
mode of x86-compatible central processing units (CPUs). It allows system software to use
features such as virtual memory, paging and safe multi-tasking designed to increase an
operating system's control over application software.
When a processor that supports x86 protected mode is powered on, it begins executing
instructions in real mode, in order to maintain backward compatibility with earlier x86
processors. Protected mode may only be entered after the system software sets up several
descriptor tables and enables the Protection Enable (PE) bit in the control register 0 (CR0).

Control Register :

Global Descriptor Table Register


This register holds the 32-bit base address and 16-bit segment limit for the global descriptor
table (GDT). When a reference is made to data in memory, a segment selector is used to find a
segment descriptor in the GDT or LDT. A segment descriptor contains the base address for a
segment.
Department of Computer Engineering Microprocessor Laboratory (2019 course)

Local Descriptor Table Register


This register holds the 32-bit base address, 16-bit segment limit, and 16-bit segment selector
for the local descriptor table (LDT). The segment which contains the LDT has a segment
descriptor in the GDT. There is no segment descriptor for the GDT. When a reference is made
to data in memory, a segment selector is used to find a segment descriptor in the GDT or LDT.
A segment descriptor contains the base address for a segment
Interrupt Descriptor Table Register
This register holds the 32-bit base address and 16-bit segment limit for the interrupt descriptor
table (IDT). When an interrupt occurs, the interrupt vector is used as an index to get a gate
descriptor from this table. The gate descriptor contains a far pointer used to start up the
interrupt handler.

Algorithm :
1. Start
Department of Computer Engineering Microprocessor Laboratory (2019 course)

2. Display the message using sys_write call


3. Read CR0
4. Checking PE bit, if 1=Protected Mode
5. Load number of digits to display
6. Rotate number left by four bits
7. Convert the number in ASCII
8. Display the number from buffer
9. Exit using sys_exit call

Conclusion: Hence we performed an ALP to program to use GDTR, LDTR and IDTR in
Real Mode
Assignment Question:
1. Explain instruction set of SMSW,SGDT,SLDT, STR?
2. What is GDT and GDTR?
3. What is LDT and LDTR?
4. What is IDT and IDTR?
5. What is selector?
6. Function of Descriptor (GDT ,LDT ,IDT) ?
7. What is mean by Interrupt Handler?
8. Explain Difference between Real Mode & Protected Mode?
9. Explain CR0 in Detail:
10. Explain POST Sequence?
11. Explain Flowchart of Real to Protected Mode Switch?

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