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Testability of VLSI

Lecture 1: Introduction to VLSI Testing

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Why Testing is Important?

1994
Prof. Thomas Nicely reports bug in Pentium
Restoring Division
Logic error not caught until > 1M units shipped
Recall cost $450M (!!!)

1997-2000
All major micro-processor manufacturers adopt
formal verification.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Requirement of Testing

Verification Testing
➢ Verifies correctness of design. ➢ Verifies correctness of manufactured hardware.
➢ Performed by simulation, hardware ➢ Test generation: software process executed
emulation, or formal methods. once during design
➢ Performed prior to manufacturing. ➢ Test application: electrical tests applied to
➢ Responsible for quality of design. hardware on every manufactured device.
➢ No limit on number of test points/test ➢ Responsible for quality of devices.
vectors ➢ Limited on number of test points/test vectors
based on the I/O pins

➢ Manufacturing Defects : IC processing/ packaging (Nano Scale Devices ↑↑ Defects)

➢ PCB assembly and wiring errors
➢ Environment, Temperature, Humidity, Vibration
➢ Power supply fluctuations
➢ Wear and Tear : friction, corrosion

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ASIC Design Flow
Specifications

Not Logic
Verification.
Testing is done for
faults in
fabrication.

GDS-II
Testing
Technology specific
Power, Performance
and Area (PPA) Goal 4

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification
Formal verification
➢ Used in different Pre-fabrication stages in ASIC project
➢ Two Types
1.Formal Equivalence Checking
2.Formal Property Checking

➢ Formal Equivalence Checking

1.RTL vs Pre-Routed Netlist
2.Pre-Routed Netlist vs Post Routed Netlist
3.Netlist Vs ECO-Netlist (functional engineering change order (ECO) for optimization)

Cadence (Conformal LEC) and Synopsys (Formality).

RTL to gate-level netlist conversion is done using our synthesis tool called Genus.
Synthesized netlist can be imported using Cadence Composer

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Equivalence Checking

1.RTL vs Pre-Routed Netlist

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Equivalence Checking

1.Pre-Routed Netlist vs Post Routed Netlist

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Equivalence Checking

F= AC+BC
Binary Decision Making
Assign F = (A&C)|(B & C)
A
0 1
1
B C
1
0 0
1
0

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Two Types of Simulation

➢ Exhaustive
➢ Selective

➢ Formal Property Checking/Model Checking.

Increased Complexity of modern-day chips makes exhaustive simulation impractical
Formal Verification is done at abstract model, Need to have
System Model (Behavior Model using Verilog. VHDL or Software d sing C++)
Specifications (Property)
Verification Method

System Verilog, Cadence Jasper

Tool takes the DUT and Assertion file as inputs

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Property Checking/Model Checking.

rst_n

r0 gnt0

gnt1
r1

ClK

r0 g0

r1 g1

g0 g1

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Property Checking/Model Checking.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Property Checking/Model Checking.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Property Checking/Model Checking.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Formal Verification

➢ Formal Property Checking/Model Checking.

Correctness of design checked by rigorous mathematical procedures
It does not require test benches or stimuli and turnaround time is very less
Boolean equivalence, Binary decision diagram (BDD)
System Verilog, Cadence Jasper
Tool takes the DUT and Assertion file as inputs

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Functional Verification

1.Static Verification

➢ Against some predefined rules

➢ Verify your design at an early stage, without any stimulus
➢ Reduce the verification effort at the RTL level.

2.Functional Simulation

➢ Verifying the functional behavior

➢ Timing delays of the internal logic or interconnects are not considered

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Timing Analysis

Static Timing Analysis

Does Static delay requirements without any input or output vectors

Dynamic Timing Analysis

Verifies functionality by applying input vectors and checking for correct output vectors

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

VLSI Production Flow

DFTT

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1 18

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testing

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Types of Testing
1. Characterization (Verification)
➢ Verify that the design is correct, and the device will meet all specifications.
➢ Functional tests are run, and comprehensive AC and DC measurements are made.
➢ Probing of internal nodes of the chip can be done on all PVT corners
➢ Silicon debug/ Basic DC/AC tests (VOL, VOH, tpd etc post fab is also called
characterization.
2. Production (Testing)
➢ Quality check on produced chips
➢ The vectors may not cover all possible functions and data patterns but must have a
high coverage of modeled faults.
➢ The main driver is cost, since every device must be tested. Test time (and
therefore cost) must be absolutely minimized.
3. Burn-in
➢ Testing, either continuously or periodically, over a long period of time.
➢ Accelerated Life test
4. Incoming Inspection
➢ Inspection on the purchased devices before integrating them into the system. Depending
upon the context, this testing can be either similar to production testing, or more
comprehensive than production testing, or even tuned to the specific systems application
20

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Types of Testing

1. Wafer sort or probe

Wafer Sort is a process where a die is tested electrically while still in wafer form.
Wafer Sort process done with the presence of equipment called wafer prober and Tester.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Types of Testing

2. Parametric Tests
➢ DC parametric tests include shorts test, opens test, maximum current test, leakage test,
output drive current test, and threshold levels test.
➢ AC parametric tests include propagation delay test, setup and hold test, functional
speed test, access time test, refresh and pause time test, and rise and fall time test.

3. Functional Tests.
➢ These consist of the input vectors and the corresponding responses. They check for proper
operation of a verified design by testing the internal chip nodes.
➢ Functional tests cover a very high percentage of modeled (e.g., stuck type) faults in logic
circuits and their generation is the main topic of this course.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Automatic Test Equipment

Advantest Model T6682 ATE

➢ The instrument electronics 0.35 VLSI chips.

➢ 1024 channels, so it can independently control and
observe 1024 chip pins simultaneously.
➢ Test speed is either 250 MHz, 500 MHz, or 1 GHz.
➢ Drive busses between –2.5 V to 6.0 V,
➢ Can drive small amplitude 200 mV signals.
clock/strobe timing accuracy is 870ps

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Automatic Test Equipment

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Shmoo Plot

VCCQ is the I/O supply of the emc interface

https://www.semiconductoronline.com/doc/shmooplot-0001
25

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

Tradeoff : Quality level vs. Cost

1. Fixed Costs (FC): These are the costs of things that are necessary but do not change with
use. Example machinery. Fixed cost per product reduces with increase in product output.

2. Variable Costs (VC): These costs increase with production output. E.g., Labor, raw
material energy etc. Variable cost per product may remain constant reduces with increase in
product output.

3. Total Costs (TC): Sum of FC and VC

4. Average Cost : These are obtained by dividing the total costs by the number of units
produced.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

If aging factor is taken into

account, the average
cost might be as shown by
the rising curve (shown as
real), called a bathtub
curve.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

Production output Q (x) where x is inputs

The average product, or the product per unit of input, is called the technological
efficiency. We maximize this efficiency by setting:

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

Maximizing technological efficiency.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics
Economic Efficiency. Engineers are good at optimizing the technological efficiency, but
often ignore the total cost of the product. Economic efficiency is related to the total cost of
production, which includes both fixed and variable costs

Maximum economic efficiency 30

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

The Law of Diminishing Returns: If one input of production is increased keeping

other inputs constant, then the output may increase, eventually reaching a point
beyond which increasing the input will cause progressively less increase in output.
31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

Increasing Returns to Scale. The case of mass production is worth considering.

Production often increases faster than the increase of inputs, which is called increasing
returns to scale. Some of the reasons are:

(1) Technological factors and

(2) Specialization.

In the long run, however, the law of diminishing returns prevails.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

Benefit-Cost Analysis
Benefits include income from sale of products or services, savings in cost and
time, etc. Costs refer to the costs of labor, machinery, energy, finances, risks, etc.
All items are normally quantified and expressed in the same units (e.g., dollars.)
We then define the benefit-cost ratio as follows:

For buying a car, the benefits could include convenient transportation to work or school and
saving time.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

Testing can be 50 to 60% of their equipment manufacturing cost

Test hardware onto the chip enable at speed testing
“Any attempt to observe a system will perturb the system behavior.”
Techniques such as scan design, BIST, and boundary scan simplify the test problem of
electronic systems.

The Rule of Ten

It is widely accepted in the electronics industry that chips must be tested before they are
assembled onto printed circuit boards (PCBs), which, in turn, must be tested before they are
assembled into systems. This is because experience has shown that the rule of ten holds. If a
chip fault is not caught by chip testing, then finding the fault costs 10 times as much at the
PCB level as at the chip level. Similarly, if a board fault is not caught by PCB testing, then
finding the fault costs 10 times as much at the system level as at the board level.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

Yield The process yield of a manufacturing process is defined as the fraction (or
percentage) of acceptable parts among all parts that are fabricated.

The term wafer yield is sometimes used to refer to the average number of good
chips produced per wafer.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Economics

A good testing procedure can reject all (or most) defective parts. Testing, however, cannot
improve the process yield. There are two ways of improving the process
yield:

(1) Diagnosis and Repair. The parts that are found defective after test are diagnosed for
specific failures which are then repaired. Although the yield is improved, this procedure
increases the cost of manufacturing. The reason is that we first allow the process to make
errors which are then corrected. A more economical procedure is to eliminate the source
errors. (Fault Tolerant Design).

(2) Process Diagnosis and Correction. The defects found in the failed parts are
traced to specific causes, which may be defective material, faulty machines,
incorrect human procedures, etc. Once the cause is eliminated, the yield
improves. Process diagnosis is the preferred method of yield improvement.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Data Analysis

Defects versus faults.

Process variations, such as impurities in wafer material and chemicals, dust particles on
masks or in the projection system, mask misalignment, incorrect temperature control, etc.,
can produce defects on wafers. The term defect generally refers to a physical imperfection
in the processed wafer

The term fault is used to refer to electrical, Boolean, or The term fault is used to refer to
electrical, Boolean, or functional malfunctions functional malfunctions.

In general, a physical defect in a chip can produce multiple faults. Thus, the spatial
distribution of faults on a wafer is also clustered, sometimes even more so than the defects.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Quality

Defect level is measured as Defect per Million (DPM)

< 200 DPM is acceptable for most IC

>1,000 DPM is very bad for most IC

System DPM
Chip DPM X Number of chips in the system

E.g.
If system has 10 Chips and Chip has DPM of 1000 (0.1% IC is defective)
System DPM = 1%
If 1 Million system is manufactured 10,000 will be defective

Defect Level (DL)

 Fraction of bad IC passing the test (test escapes)

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Models to Predict DPM

Brown & Williams (IBM, 1981), Binomial distribution

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
39

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Models to Predict DL
Brown & Williams (IBM, 1981), Binomial distribution

𝑑
𝐹𝐶 = , 𝑤ℎ𝑒𝑟𝑒 𝑑 𝑖𝑠 𝑓𝑎𝑢𝑙𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝑎𝑛𝑑 𝑡 𝑖𝑠 𝑡𝑜𝑡𝑎𝑙 𝑓𝑎𝑢𝑙𝑡𝑠
𝑡

𝑌𝑒𝑖𝑙𝑑 = 𝑃𝑟𝑜𝑏𝑎𝑏𝑖𝑙𝑖𝑡𝑦 𝑡ℎ𝑎𝑡 𝐼𝐶 𝑖𝑠 𝑔𝑜𝑜𝑑 = (1 − 𝑞)𝑡

Where each fault occurrence probability is q (uniform independent)

𝑑
𝑡 1− 𝑡
𝐹𝑟𝑎𝑐𝑡𝑖𝑜𝑛 𝑜𝑓 𝐺𝑜𝑜𝑑 𝐼𝐶 𝑝𝑎𝑠𝑠𝑖𝑛𝑔 𝑡𝑒𝑠𝑡 = (1 − 𝑞)𝑡−𝑑 = (1 − 𝑞) = 𝑌 (1−𝐹𝐶)

𝐹𝑟𝑎𝑐𝑡𝑖𝑜𝑛 𝑜𝑓 𝐵𝑎𝑑 𝐼𝐶 𝑝𝑎𝑠𝑠𝑖𝑛𝑔 𝑡𝑒𝑠𝑡 (𝐷𝐿) = 1 − 𝑌 (1−𝐹𝐶)

In the Williams-Brown model, dies are assumed to have equal faults to model the impact
of actual defects.

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
40

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Models to Predict DL
Agarwal Model, Poisson distribution

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
41

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Yield Estimation

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
42

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI Circuits”,
Michael L. Bushnell and Vishwani D. Agrawal, Kluwer Academic Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

Lab. of Dependable Systems Graduate Institute of Electronics Engineering.
National Taiwan University
https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-
SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 2: Fault Modelling

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Defects, Errors, and Faults
Defect. A defect in an electronic system is the unintended difference between
the implemented hardware and its intended design.
Example : unwanted wire (short to ground)
1. Process Defects – missing contact windows, parasitic transistors, oxide breakdown,
etc.
2. Material Defects – bulk defects (cracks, crystal imperfections), surface impurities,
etc.
3. Package Defects – contact degradation, seal leaks, etc
4. Age Defects – dielectric breakdown, electromigration, etc.
Fault. A representation of a “defect” at the abstracted function level is called a fault
Example: Stuck to Zero Fault
Error. A wrong output signal produced by a defective system is called an error. An
error is an “effect” whose cause is some “defect.
Example: output = 0, when a=b=1 for a AND gate

Failure : Deviation from expected behavior Example: computer crash

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fabrication Faults

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fabrication Faults

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Models
Why Fault Modelling?

1. Defects are hard to handle

How many possible defects in a circuit ? Way too many
Number of faults can be easily calculated in a circuit

2. Fault models makes test automation possible

Automatic test pattern generation (ATPG) generate test patterns
Fault simulation
Evaluate test quality
Automatic diagnosis
Locate defects

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Models

1. Assertion Fault: An assertion expresses a property of a high-level function in the form:

“antecedent consequent,” where antecedent and consequent can be simple predicates like
“line L takes symbolic value v” or conjunctions of simple predicates.

2. Behavioural Faults (Functional or High level): When the behavior of an electronic

system is described in computer-readable form, it is generally written in a programming
language (such as C) or some other hardware description language that resembles a
programming language.

3. Structural Faults: The structure of a circuit may refer to its topology or to physical
geometry. Examples of structural faults are single stuck-at faults and bridging faults.
Focus is on manufacturing defects not functional aspect of DUT.

➢ Please refer to other types of faults in the textbook

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Functional Versus Structural Testing

𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛𝑎𝑙 𝑇𝑒𝑠𝑡 𝑉𝑒𝑐𝑡𝑜𝑡𝑠 2129 = 6.8 ∗ 1038

𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑖𝑚𝑒 𝑤𝑖𝑡ℎ 𝐶𝑙𝑜𝑐𝑘 𝑜𝑓 1 𝐺𝐻𝑧 ≈ 22 𝑦𝑒𝑎𝑟𝑠

𝑀𝑎𝑥 𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 64 ∗ (10 + 17)

𝐴𝑐𝑡𝑎𝑢𝑙 𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑐𝑜𝑢𝑙𝑑 𝑏𝑒 𝑠𝑚𝑢𝑐ℎ 𝑙𝑒𝑠𝑠𝑒𝑟𝑎𝑠 𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑒 𝑠𝑎

𝑓𝑎𝑢𝑙𝑡𝑠 𝑔𝑒𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝑤𝑖𝑡ℎ 𝑠𝑖𝑛𝑔𝑙𝑒 𝑣𝑒𝑐𝑡𝑜𝑟
7

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Common Structural Fault Models

➢ Single stuck-at faults

➢ Transistor open and short faults
➢ Bridging Faults
➢ Delay faults (transition, path)
➢ Analog faults

➢ Please refer to other types of faults in the textbook

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Single Stuck-at faults

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Single Stuck-at faults

How many Fault Sites ? 3

How many Fault ?

Minimum test length for 100% SSF fault coverage ? 3

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Single Stuck-at faults

Properties of single stuck-at fault

⚫ Only one line is faulty
⚫ The faulty line is permanently set to 0 or 1
⚫ The fault can be at an input or output of a gate

XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Single Stuck-at faults
SSF on fanout wires not equivalent to SSF on fanout branches
Faults on stems and faults on branches are counted separately
Example: E is fanout stem; L,F are fanout branches

𝐾 = 𝐴ҧ𝐵𝐶 ҧ 𝐶ҧ + 𝐴𝐵𝐶
ത + 𝐴𝐵 ҧ

𝐾 = 𝐴(ҧ 𝐵𝐶 ҧ
ത + 𝐵 𝐶+𝐵𝐶)
ҧ + 𝐶)
𝐾 = 𝐴(𝐵

𝐾 = 𝐴 + (𝐵 + 𝐶)

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Multiple Stuck-at faults

𝐼𝑓 𝑡ℎ𝑒𝑟𝑒 𝑎𝑟𝑒 𝑁 𝑝𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝑓𝑎𝑢𝑙𝑡 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛𝑠 𝑖𝑛 𝑎 𝑐𝑖𝑟𝑐𝑢𝑖𝑡

𝑇𝑜𝑡𝑎𝑙 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑖𝑒𝑠 𝑖𝑠 3𝑁 𝑎𝑠 𝑎 𝑙𝑖𝑛𝑒 𝑏𝑒 𝑏𝑒 𝑠𝑎0 , 𝑠𝑎1 𝑜𝑟 𝑔𝑜𝑜𝑑
𝑂𝑛𝑒 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑦 𝑜𝑓 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 𝑏𝑒𝑖𝑛𝑔 𝑔𝑜𝑜𝑑
2𝑁 𝑝𝑜𝑠𝑠𝑖𝑏𝑖𝑙𝑖𝑡𝑖𝑒𝑠 of single fault
Possibilities of multiple fault 3𝑁 - 1- 2N

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Multiple Stuck-at faults

Different
Algorithms

Hughes, J.L.A., and E.J. McCluskey, “An Analysis of the Multiple Fault Detection Capabilities of
Single Stuck-at Fault Test Sets,” Proc. of Int’l Test Conf, Philadelphia, PA, Oct. 1984, pp. 52–58.
14

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Multiple Stuck-at faults

1
0(1)

0(1)

SA0

What should be the test vector ? 011

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Multiple Stuck-at faults

SA1

1(0)
1

0(1)

SA0

What should be the test vector ? 011 SA1 is Masking SA0

What should be the test vector ? 010 detects the MSF {c SA0, a SA1}.
16

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Bridging faults

Input to Output Short Input to Input Short Output to Output Short

➢ Improper masking or etching

➢ Loose or excess bare wires
➢ Defective printed circuit boards
➢ Shorting of pins of a chip

Test Vectors for Input and Output Stuck-at Faults cover Input-to-Output Shorts

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Bridging faults
Input to Output Short

1. Can cause oscillations

2. Creates Memory

Test Vectors for Input and Output Stuck-at Faults cover Input-to-Output Shorts

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Bridging faults
Short is Modeled as Low Resistance

Original Wired-OR Wired-AND F-dominant

Fault-free FG Faulty FG Faulty FG Faulty FG
00 00 00 00
01 11 00 00
10 11 00 11
11 11 11 11

If F,G = 0,0 can be detected as F s-a-0

If F,G = 1,1 can be detected as G s-a-1

High Resistance Bridges do not affect the logic value, and hence are undetectable by a
static logic test.
19

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Bridging faults
Different Models Need Different Patterns

Inputs Fault-free Wired Wired A

ABC Output OR AND dominant
000 0 0 0 0
001 1 1 1 1
010 1 0 0 0
011 1 0 0 1
100 0 0 0 0
101 0 0 0 0
110 0 0 0 0
111 0 0 0 0
20

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Bridging faults

[Millman 88] S.D. Millman, McCluskey, “Detecting bridging faults with stuck-at test sets,”
ITC 1988.
21

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Delay faults

Delay Fault

Slow to rise, slow to fall

Slow to rise (STR), slow to fall Transition (STF), faults due to Vt Variation, Doing
Variation, Improper contacts etc
No fault detected at static and low frequency operation but glitches can be there at
high operating frequencies and cause errors in sequential circuits
Delay Faults requires two test vectors 22

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Delay faults
Delay Fault

Can be modelled a RC delay but can be because of poor MOSFET being fabricated
or nay other fab defects .

Delay Faults requires two test vectors

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Delay faults

Path Delay Fault

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Delay faults

How Many Paths ? 5 paths: {AHK, BELHK, BEFJK, CELHK, CEFJK}

How Many set of test vectors ? 10 sets

Test vector to detect STF fault at F ? 001-000

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Delay faults

(101,111) : Non-robust test for path

STR at E

(101,100) : Robust test for path STR

at E

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Delay faults
Robust Testing may note possible always

AND1 Check : B=1 , C= 0 AND2 Check : A=0 , C= 1

AND3 Check : A=0 , Will render Both AND1 and AND 3 to Low
A=1, B=0 will activate AND2 and B=0 will activate AND 14
27

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Experimental Results

[2]/ Video lectures by Professor James Chien-Mo Li

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Models

in0 in1 Ctrl Out Detected SSF

0 1 0 0 In0 (Sa1), Out (Sa1), Cntrl (Sa1)
1 0 0 1 In0 (Sa0), Out (Sa0),
1 0 1 0 In1 (Sa1), Cntrl (Sa0)
1 1 1 1 In1 (Sa0)

Note: only four vectors for 3 inputs

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Transistor faults

OS
Two types of Transistor Faults

➢ Stuck-open -- a single transistor is permanently stuck in the open state

irrespective of its gate voltage. Single Stuck-open detection requires two test
patterns

➢ Stuck-short -- a single transistor is permanently shorted irrespective of its

gate voltage. Detection by quiescent IDD

http://ece-research.unm.edu/jimp/vlsi_test/slides/html/faults2.html
30

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Transistor faults
Stuck-open

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Transistor faults

Two-pattern Tests for Stuck-open Faults

Automation available to optimize Stuck-at and Stuk-open Fault

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Transistor faults
Stuck-on fault

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Transistor faults
SOP  TDF

[2]. Video lectures by Professor James Chien-Mo Li

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Cell Aware Fault Model

3X1 Mux

Hapke, Friedrich & Redemund, Wilfried & Glowatz, Andreas & Rajski, Janusz & Reese, M. & Hustava, Marek
& Keim, Martin & Schlöffel, Jürgen & Fast, Anja. (2014). Cell-Aware Test. Computer-Aided Design of
Integrated Circuits and Systems, IEEE Transactions on. 33. 1396-1409. 10.1109/TCAD.2014.2323216.
36

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Cell Aware Fault Model

3X1 Mux

PPM reduction AMD 32 nm notebook processor.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Cell Aware Fault Model

in0 in1 Ctrl Out Detected SSF

0 1 0 0 In0 (Sa1), Out (Sa1), Cntrl (Sa1)
1 0 0 1 In0 (Sa0), Out (Sa0),
1 0 1 0 In1 (Sa1), Cntrl (Sa0)
1 1 1 1 In1 (Sa0)
0 0 1 0 Bridging w and in0

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

Lab. of Dependable Systems Graduate Institute of Electronics Engineering
National Taiwan University
https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-
SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

3. http://ece-research.unm.edu/jimp/vlsi_test/slides/html/faults2.html

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 3: Fault Collapsing

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Functional Versus Structural Testing

𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛𝑎𝑙 𝑇𝑒𝑠𝑡
𝑇𝑒𝑠𝑡 𝑉𝑒𝑐𝑡𝑜𝑡𝑠 2129 = 6.8 ∗ 1038
𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑖𝑚𝑒 𝑤𝑖𝑡ℎ 𝐶𝑙𝑜𝑐𝑘 𝑜𝑓 1 𝐺𝐻𝑧 ≈ 22 𝑦𝑒𝑎𝑟𝑠

𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 64 ∗ (10 + 17)

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Single Stuck-at faults

How many Fault Sites ? 3

How many Fault ?

Minimum test length for 100% SSF fault coverage ? 3

No requirement to exactly identify which fault. Entire gate is to be discarded 3

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Delay faults

How Many Paths ? 5 paths: {AHK, BELHK, BEFJK, CELHK, CEFJK}

How Many set of test vectors ? 10 sets

Test vector to detect delay fault at F ? 001-000

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Transistor faults

Two-pattern Tests for Stuck-open Faults

Automation available to optimize Stuck-at and Stuk-open Fault

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Detection

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Fault Sensitization
1. Fault Sensitization: We need to choose a test vector that activates the fault site
with complementary signal

X3 =1

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Fault Propagation
2. Fault Propagation: We need to chose a suitable path for propagate the fault to
a primary output.

G4 >> G5>> z

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Fault Justification
3. Fault Justification: We need to work from output to input to assign test vectors
to primary inputs.

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Fault Detectability
A fault f is said to be detectable if there exists a test t that detects f ;
otherwise, f is an undetectable fault

E.g. And 3 S-a-0 is not detectable

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Fault Coverage

Complete detection test set: A set of tests that detect any detectable faults
in a class of faults

The quality of a test set is measured by fault coverage

Fault coverage: Fraction of faults that are detected by a test set

>95% - 99.9% is typically required

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Fault Equivalence
Fault equivalence.

1. Two faults of a Boolean circuit are called equivalent iff they transform the circuit
such that the two faulty circuits have identical output functions.

2. Equivalent faults are also called indistinguishable and have exactly

the same set of tests.
Faults f and g are functionally equivalent (or simply equivalent) if faulty outputs
of them are identical for all test patterns

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Fault Equivalence

Input Output
A B Good A/0 B/0 C/0 A/1 B/1 C/1
0 0 0 0 0 0 1 1 1
0 1 1 1 0 0 1 1 1
1 0 1 0 0 0 1 1 1
1 1 1 1 1 0 1 1 1

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Equivalence

Input Output
A B Good A/0 B/0 C/0 A/1 B/1 C/1
0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 0 1 1
1 0 1 1 1 0 0 0 1
1 1 0 1 1 0 1 1 1

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Equivalence

Input Output
Good in/0 in/1 out/0 out/1
0 1 1 0 0 1
1 0 1 0 0 1

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Fault Equivalence

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Equivalence Fault Collapsing
n+2 instead of 2n+2 faults need to be
considered for an n-input gate

Why Equivalence Fault Collapsing (EFC)?

➢ Reduce number of faults so that
➢ Speed up ATPG
➢ Shorten test set ( 6 to 4 sa faults for 2 i/p gates)

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Equivalence Fault Collapsing
EFC on Fanout-free Circuits
EFC Rules
 (1) both stuck-at one and zero faults for every primary output
 (2) one collapsed fault for each gate input

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Equivalence Fault Collapsing

Fault collapsing reduces 18 s-a faults to 12

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Equivalence Fault Collapsing
Fanout stem faults are NOT always equivalent to fanout branch faults

Example:
 E/0 is equivalent to F/0
 but not equivalent to L/0
 The other faults are NOT equivalent

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Equivalence Fault Collapsing

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Dominance Fault Collapsing
Detecting set of fault f (Tf) = set of all possible test patterns that detect fault f
Fault f dominates fault g if the detecting set of f contains that of g

For F2 Sa1 {00,01,10}

For F1 sa1
01

Fault F2 dominates fault F1

If fault F2 dominates F1, then F2 is removed from the fault list
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Dominance Fault Collapsing

8/6/2023 23

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Dominance Fault Collapsing

g
f

𝒇↔ 𝒈↔𝒉 𝒇→ 𝒈→𝒉

[2] Video lectures by Professor James Chien-Mo Li

8/6/2023 24

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Dominance Fault Collapsing

8/6/2023 25

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Dominance Fault Collapsing

If this is passed
obviously C is
not Sa0

Input Output
A B Good A/0 B/0 C/0 A/1 B/1 C/1
0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 0 1 1
If this is
1 0 1 1 1 0 1 0 1
passed
1 1 0 1 1 0 0 0 1 obviously A
and B are is
not Sa0

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Dominance Fault Collapsing

→ DFC 7 faults

8/6/2023 [2] Video lectures by Professor James Chien-Mo Li 27

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Dominance Fault Collapsing

14 faults → 8 faults after EFC

→ 5 faults after DFC

8/6/2023 28

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Dominance Fault Collapsing
Fanout Stem and Branches

→ DFC 7 faults
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Checkpoint Theorem
Primary inputs and fanout branches of a combinational circuit are called
checkpoints

Checkpoint theorem: “A test set that detects all single (multiple) stuck-at
faults on all checkpoints of a combinational circuit, also detects all single
(multiple) stuck-at faults in that circuit.”

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Checkpoint Theorem

8/6/2023 [2] Video lectures by Professor James Chien-Mo Li 31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Checkpoint Theorem

Chkpt is a Simpler Alternative to EFC/DFC

DFC has issues in sequential circuits and EFC is most preferred technique
for ATPG

8/6/2023 [2] Video lectures by Professor James Chien-Mo Li 32

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Collapse Ratio

8/6/2023 [2] Video lectures by Professor James Chien-Mo Li 33

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Simulation for Design Verification

True-value means that the simulator will compute the response for given input stimuli without
injecting any faults in the design. The input stimuli are also based on the specification.
A frequently used strategy is to exercise all functions with only critical data patterns. This is
because the simulation of the exhaustive set of data patterns can be too expensive
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

True Value Simulation

1. A design can be first simulated at a higher behavior level (such as C).

Netlist not required
Does not contain the detailed timing information.
No electrical behavior
2, Once this design is verified, higher-level blocks are replaced by logic-level netlists.
At this point, a logic simulator is used for verification.
3. The process may be repeated by replacing some or all portions by transistor-level or
circuit-level implementations.

Simulation is used in this way for verifying very large electronic systems.

The weakness of this method is its dependence on the designer’s heuristics used
in generating the input stimuli.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder. How Many Test vectors Required?

The first seven vectors

cover all stuck-at faults.
One may, therefore, use
only the first seven vectors
in the manufacturing test.

Note: This optimization is possible because of same blocks (FA) being used
8/6/2023
and each test vector verifying similar faults in all blocks 36

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder.

Timing analysis of 2 followed by 6 or 3 followed by 7 where carry propagates through the

chain

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Fault simulation for test generation

8/6/2023 38

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 4: Logic Simulation

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Simulation for Design Verification

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Simulation for Design Verification

1. Why learn Design verification now?

2. Many concepts of verification like event driven simulation etc. representation of

unknown as X etc. is used in Fault simulation algorithms also.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

True Value Simulation

1. A design can be first simulated at a higher behavior level (such as C).

Simulation is used in this way for verifying very large electronic systems.

The weakness of this method is its dependence on the designer’s heuristics used
in generating the input stimuli.

8/13/2023 4

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder. How Many Test vectors Required?

The first seven vectors

cover all stuck-at faults.
One may, therefore, use
only the first seven vectors
in the manufacturing test.

Note: This optimization is possible because of same blocks (FA) being used
8/13/2023
and each test vector verifying similar faults in all blocks 5

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder.

Timing analysis of 2 followed by 6 or 3 followed by 7 where carry propagates through the

chain . Only Possible for Modular Structure

8/13/2023 6

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault simulation for test generation

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Circuits for Simulation
1. Function or Behaviour Level

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Circuits for Simulation
2. Logic Level

Gate Level Modelling

module Simple_circuit (input A, input B, input C,

output x, output y);
wire w1;

and g1 (w1,A,B); // and gate instance

not g2 (y,C);
or g3 (x,w1,y);

endmodule
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Circuits for Simulation
3. Switch Level MOS transistors, which are treated as ideal switches

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Circuits for Simulation
4. Circuit Level

This is the lowest level and represents the ultimate in accuracy for the simulation of
electronic systems. The circuit is assumed to be composed of electrical elements such
as resistors, capacitors, inductors, and transistors. Equations relating branch or loop
currents and node voltages are developed and solved by numerical methods

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Circuits for Simulation
5. Timing Level That is, the connectivity of transistors, their sizes and types, and node
capacitances are needed. In addition, technology data specifying the
transistor voltage-current characteristics are also used to compute
charging or discharging currents for the nodes.

Transistor level Modelling

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Why Circuit Level Modeling Is Important

If both control inputs are turned on, If both control inputs are turned on, as,
Results in High Currents the 1 input will dominate.

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Modeling Signal States

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Example -1

Z = ABCD

module Sample (
input A, B, C, D,
output Z,
inout w1, w2, w3 );
and g1(w1,A,B);
and g2 (w2, C,D);
and g3 (Z,w1,w3);
endmodule

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -1

Z = ABCD

initial begin
A = 0;
B = 0;
C = 0;
D = 0;
#10;
A = 1;
B = 1;
C = 1;
D = 1;
#10;
$finish;
end
16

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -1

Z = ABCD

X (in red) stands for Forcing Unknown. 17

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -2

Z = AB+CD

module Sample (
input A, B, C, D,
output Z,
inout w1, w2, w3 );
and g1(w1,A,B);
and g2 (w2, C,D);
or g3 (Z,w1,w3);
endmodule

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -2

Z = AB+CD

initial begin
A = 0;
B = 0;
C = 0;
D = 0;
#10;
A = 1;
B = 1;
C = 1;
D = 1;
#10;
$finish;
end
19

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -2
Z = AB+CD

How is the Simulation tool identifying State X ??

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -3

module mux_2_1(
input sel,
input i0, i1,
output y);
assign y = sel ? i1 : i0;
endmodule

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -4

module tristate_buffer(
input x,
input enable,
output y);
assign y = enable? x : 'bz;
endmodule

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Example -4

module Mux_using_buffer
(input x1,x2,s1,s2,
output y);
tristate_buffer g1 (x1,s1,y);
tristate_buffer g2 (x2,s2,y);
endmodule

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Gates for Z and X inputs

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling XOR/NOR Gate

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Limitation in Simulation

Simulation

Testing

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Design for Testing

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Circuits for Simulation

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Modeling Circuits for Simulation

1. Zero Delay Model

2. Unit Delay Model
3. Multiple Delay Model
Tr and Tf different for each type of gate
4. Min. Max Delay

Digital circuit simulators tend to either ignore

the fine grain variations (transients) between
those meaningful values or model the
transients

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Algorithms for True-Value Simulation

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Compiled-Code Simulation

Normally in an HDL such as VHDL or Verilog

1. Circuit Simplification
2. Circuit Levelized
3. Signals are treated as variables in the code
4. For every input vector, the code is repeatedly executed until all variables
have attained steady values
5. Compiled-code simulators are very effective where two-state (0,1)
simulation suffices
6. Timing are not modeled in a compiled-code simulator

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Compiled-Code Simulation

Circuit Simplification

Video lectures by Professor James Chien-Mo Li

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Compiled-Code Simulation
Levelisation

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Compiled-Code Simulation
Levelisation

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Compiled-Code Simulation
Levelisation
module Full_adder_df (
input a, b, cin, wire q, r, output p, cout, sum);
assign sum = p^cin;
assign p = a^b ;
assign r = a&b ;
assign q = p&cin ;
assign cout = r | q;
endmodule

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Compiled-Code Simulation

Compiled-code simulation: convert gates into codes for

evaluation
 Optimization: simplifies logic
 Levelization: sort gates in order (i.e. topological sort of
graph)
 Code generated: 1.high-level, 2.machine, 3.interpreted
☺ Pros
 Simple to implement
 Can speed-up by parallelism
 see parallel simulation
 Cons
 Only cycle-based accuracy, no timing (zero gate delay)
 Need to evaluate whole circuit even only small portion
changed
 see event-driven simulation

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Event-driven Simulation

 Zero delay
 Nominal delay Event-driven Faster then CC
 Data structure

It is based on the recognition that any signal change (event) must have
a cause, which is also an event. Thus, an event causes new events, which in turn may
cause more events. An event-driven simulator follows the path of events.
Gates whose inputs now have events are called active and are placed in
an activity list. The simulation proceeds by removing a gate from the activity list
and evaluating it to determine whether its output has an event.

An event-driven simulator only does the

necessary amount of work.
For logic
circuits, in which typically very few signals change at a time, this can result in significant
savings of computing effort. However, the biggest advantage of this technique
is in its ability to simulate any arbitrary delays. This is done by a procedure known
as event scheduling. 37

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Event-driven Simulation

Suppose the circuit is simulated with two consecutive input vectors,

(0,0,0,0) and (0,0,0,1). Since A, B, and C have not changed, it is not necessary to
simulate gates G1 and G2. Since neither G1 nor G2 have been simulated, it is not
necessary to test X1 or X2 for changes. The simulation of G4 can be bypassed without
testing X1 or X2.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Event-driven Simulation

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Event-driven Simulation
Zero-delay Event-driven Sim

[2]. Video lectures by Professor James Chien-Mo Li 40

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Event-driven Simulation
Nominal delay

[2]. Video lectures by Professor James Chien-Mo Li 41

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Event-driven Simulation

G3 taken
as 1

G2 taken
as 1
G2 taken
as 0

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 5: Fault Simulation

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Simulation

Netlist

Fault Statistics
Collapsed fault list Fault Simulator
A0, A1, B0…

Automatic Test pattern generation

Text Vectors

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Fault Simulation

Steps Involved in Automatic Test pattern generation

1. Fault Sensitization : Driving a node with a stuck at fault with

complementary signal by appropriately selecting the input vector.

2. Fault Propagation : Affect of the fault needs to be propagated to one

of the primary outputs.

3. Line Justification : Determination of the values at primary inputs so that fault

sensitization and propagation are successful.

SPJ is a lengthy process needs to be done for fault separately, but we can get 100% fault
coverage of detectable faults.

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Fault Simulation
Random Test Pattern Generation
100

70
% Fault Coverage

0
0 20 40 60 80 100 120 140 160 180 200

Number of Random Test vectors

RTP is a very fast process, detects multiple faults in each run, but we may not get 100%
fault coverage of detectable faults.
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Algorithms for Fault Simulation

Serial Fault Simulation

The block C( ) is the fault-free circuit and blocks C(f1) through C(fn) are copies of the same
circuit with faults f1 through fn . The same vectors are applied to all blocks and the outputs
of the faulty circuits are compared in the comparators shown as Comp. Event Driven can
save time as one circuit to other not much change
When fault fn is detected for the first time by vector 35, the simulation of block C(fn) is
suspended beyond that vector. This procedure, known as fault dropping, considerably speeds
up the fault simulation process .
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Algorithms for Fault Simulation

Serial Fault Simulation

Fault dropping considerably speeds up the fault simulation process . Max time for Algorithm
is M(n+1), M is max total test vectors of each block, n is number of faults. While testing only n
vectors max required, Algorithm finds those n vectors. Could be less than n as multiple faults
can be detected by a same vector.
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Inserting Faults

MZ M0
Fault Free 1 0
S-a-1 X 1
S-a-0 0 0

𝒁′ = 𝒁&𝑴𝒁 |𝑴𝟎

Each faut site to be modeled as above and in test bench values of MZ and M0 are be set
for different runs

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Serial Fault Simulation

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Serial Fault Simulation

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Serial Fault Simulation

Advantages:
Easy to implement
Ability to handle a wide range of fault models (stuck-at, delay, Br, …)
Very fast combinational simulation

Disadvantages:
Many simulation runs required
CPU time prohibitive for VLSI circuits

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Parallel Fault Simulation
The idea of parallel fault simulation is to use the bit-parallelism of logical operations in a digital
computer. For a 32-bit machine word, an integer consists of a 32-bit binary vector. A logical
AND or OR operation involving two words performs simultaneous AND or OR operations on all
respective pairs of bits.

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Parallel Fault Simulation
N W2 s-a-0 W4 s-a-1 W1 s-a-0

1 1 1 1
1 W5 1 0 1 0
s-a-0 s-a-0
1
W1 1 0 1 0
1 1 1 0 1 0 1 0 W6
O2
s-a-1
W4 0 0 1 0
1 1 1 0 0 0 1 1

Max Number of Simulations Required

= Mn/(w-1) w is CPU word size,
We can assume the parallel process is faster than serial by approx. w times.

https://www.youtube.com/watch?v=eLUhlph4VCQ
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Parallel Fault Simulation

Advantages:
A large number of faults are detected by each pattern when simulating the
beginning of test sequence.

„ isadvantages:
D
Only applicable to the unit or zero delay models
Faults cannot be dropped unless all (w-1) faults are detected

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Deductive Fault Simulation

All signal values in each faulty circuit are deduced from the fault-free
circuit values and the circuit structure. Since the circuit structure is the same
for all faulty circuits, all deductions are carried out simultaneously. Thus, a
deductive fault simulator processes all faults in a single pass of true-value
simulation augmented with the deductive procedures. This gives the deductive
simulators a tremendous speed, but only when the modeling conditions can be
satisfied.

https://www.youtube.com/watch?v=zTLI2i69tKQ
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Deductive Fault Simulation

Lc=[a1, c1] Ld=[a1, c1, d1]

La=[a1]
a d 0/1
0

1 c 0/1
e 0/1
b
Lb=[b0] Le=[a1, c1, e1]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1

https://www.youtube.com/watch?v=zTLI2i69tKQ
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Deductive Fault Simulation

Lc=[b1, c1] Ld=[b1, c1, d1]

La=[a0]
a d 0/1
1

0 c 0/1
e 0/1
b
Lb=[b1] Le=[b1, c1, e1]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1

https://www.youtube.com/watch?v=zTLI2i69tKQ
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Deductive Fault Simulation
Lc=[La.Lb,c1] Ld=[La.Lb, c1, d1]
La=[a1]
a d 0/1
0

0 c 0/1
e 0/1
b
Lb=[b1] Le=[La.Lb ,c1, e1]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1
AND 0 0 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Deductive Fault Simulation
Lc=[a0, b0,c0] Ld=[a0, b0, c0, d0]
La=[a0]
a d 1/0
1

1 c 1/0
e 1/0
b
Lb=[b0] Le=[a0, bo, co, d0]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1
AND 0 0 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 1 1 (𝐿𝑎 ∪ 𝐿𝑏) ∪ 𝑐0

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Deductive Fault Simulation
Lc=[a0, b0,c0] Ld=[a0, b0, c0, d0]
La=[a0]
a d 1/0
1

1 c 1/0
e 1/0
b
Lb=[b0] Le=[a0, bo, co, d0]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 a1, c1
AND 1 0 0 b1, c1
AND 0 0 0 c1
AND 1 1 1 a0, b0, c0

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Deductive Fault Simulation
La=[a1]
a
0 Lc=[a1, b1,c1]

0 c 0/1
b
Lb=[a1]

La=[a1] La=[a1, c0]

0 a c 1/0
1 c 0/1
La=[a0] La=[a0, c1]

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Deductive Fault Simulation

Lb=[a1, b0]
La=[a1] Lc=[b0, c1]
0
b 1/0
c 0/1
La=[a1]
0

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Deductive Fault Simulation

Lb=[a0, b1]
La=[a0] Lc=[ao,b1, c1]
1
b 0/1
c 0/1
La=[a0]
1

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Deductive Fault Simulation

Single Vector Simulation will give what are the faults which can
be detected and what should be the correct expected result.
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Deductive Fault Simulation

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Deductive Fault Simulation

Advantages:
Very efficient
Simulate all faults in one pass

Disadvantages:
Not easy to handle unknowns
Only for zero-delay timing model Potential
memory management problem

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Concurrent Fault Simulation
It can handle various types of circuit models, faults, signal states, and timing models. It
basically extends the event-driven simulation method to the simulation of faults in the
most efficient way and faster. Data from previous simulation is retained.

✓ ✓ ✓ ✓

Also gives information of Faults not detected.

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Concurrent Fault Simulation

Simulate only differential parts of whole circuit

Event-driven simulation with fault-free and faulty circuits simulated altogether
Concurrent fault list for each gate
Consist of a set of bad gates
Fault index & associated gate I/O values
Initially only contains local faults
Fault propagate from previous stage

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Concurrent Fault Simulation

Good event
Events that happen in good circuit
Affect both good gates and bad gates
Bad event
Events that occur in the faulty circuit of corresponding fault
Affect only bad gates
Diverge
Addition of new bad gates
Converge
Removal of bad gates whose I/O signals are the same as corresponding good gates

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Concurrent Fault Simulation

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Concurrent Fault Simulation

Not Computed
data from previous
simulation retained

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Concurrent Fault Simulation

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Concurrent Fault Simulation

Advantages
Efficient
Faults can be simulated in any modeling style or detail supported in true-
value simulation (offers most flexibility.)
Faster than other methods

Disadvantages
Potential memory problem
Size of the concurrent fault list changes at run time

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Comparison of Fault Simulation Techniques

Speed
Serial fault simulation: slowest
Parallel fault simulation: O(n3), n: num of gates
Deductive fault simulation: O(n2)
Concurrent fault is faster than deductive fault simulation
Memory usage
Serial fault simulation, parallel fault simulation: no problem
Deductive fault simulation: dynamic allocate memory and hard to predict size
Concurrent fault simulation: more severe than deductive fault simulation

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Roth's TEST-DETECT Algorithm
The circuit is simulated for a vector in the true-value mode. This determines the states of all
lines. Next, faults are analyzed one at a time to determine which faults are detected by the
presently simulated vector. The analysis is based on Roth’s D-calculus that allows a composite
representation of a signal in the fault-free and faulty circuits.

In Roth’s D-calculus D = (1,0) and D’=(0,1). D algebra will be covered in subsequent classes.

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References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 6A: Testability Measures

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Simulation

Netlist

Collapsed Fault Fault Statistics

Fault Simulator
list
A0, A1, B0…

Automatic Test pattern generation

Text Vectors

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TESTABILITY MEASURES

We need an algorithm to find which are difficult fouls to detect using random sequence of
Test vectors to apply Sensitization , Propagation and Justification
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Setting Difficulty levels
CC-Combinational Controllability
Lower Value Indicates greater difficulty 1 1
How difficult to detect sa0 ∗4
32
1
𝐶𝐶1 =
8
1 1
𝐶𝐶1 = ∗
8 4

1
𝐶𝐶1 =
4

3
𝐶𝐶0 =
4
1 How difficult to
𝐶𝐶1 = 1
detect sa1 32 ∗ 4
3
4

Inefficient Algorithm
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

TESTABILITY MEASURES
SCOAP Controllability and Observability
Sandia Controllability/Observability Analysis Program.

SCOAP consists of six numerical measures for each signal (l) in the circuit:
1. Combinational 0-controllability, CC0(l)
2. Combinational 1-controllability, CC1(l)
3. Combinational observability, CO(l)
4. Sequential 0-controllability, SC0(l)
5. Sequential 1-controllability, SC1(l)
6. Sequential observability, SO(l)

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Combinational SCOAP Measures

1. Set the difficulty of controlling each primary input (PI) to 0 (called CC0) to the
value 1 and the difficulty of controlling each PI to 1 (called CC1) to the value 1.

2. We progress through the circuit in a forward pass, in level order.

For each logic gate that we traverse, we add 1 to the controllability. This accounts
for the logic depth.

(i) If a logic gate output is produced by setting only one input to

a controlling value, then:

(ii) If a logic gate output can only be produced by setting all inputs to a
non-controlling value, then:

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Combinational SCOAP Measures
SCOAP controllability calculation

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Combinational SCOAP Measures

3. After all controllabilities are established, we compute observabilities in a reverse pass

starting from primary outputs (POs) and moving backwards to the PIs. We first set the
output observability difficulty (called CO) to 0, making no distinction between logic 0 and 1
in observabilities.
4. For a logic gate with an input signal that needs to be observed, the difficulty of observing
that input equals the observability of the output plus the difficulty of setting all other inputs
to non-controlling values, plus 1 to account for the logic depth.

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Combinational SCOAP Measures
SCOAP observability calculation

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Combinational SCOAP Measures
(CC0, CC1)

(1, 1)
(2, 3)

(1, 1) (1, 1)

(3, 6)

(1, 1) (2, 2)

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Combinational SCOAP Measures
To get a 0 to check sa1 at X give (0,0
or 0,1 or 1,0) and both inputs
If 0 required at O
together should not be sa1
Additional condition is O
should not be sa1 and if
(CC0, CC1) setting Y to 0 is easier,
(1, 1) then other path can be
(2, 3) used

(1, 1) (1, 1) X

Y
(3, 6)

(1, 1) (2, 2)

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Combinational SCOAP Measures
To get a 1 to check sa0 at X1
detect give (11) and also both
should not be sa0
(CC0, CC1)
(1, 1)
(2, 3)

(1, 1) (1, 1) X

Y
(3, 6)

(1, 1) (2, 2)

To get a 1 to detect sa0

ensure 1 at X, Y and no
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Combinational SCOAP Measures

To get a 0 to check sa1 difficulty level 2. To

observe at O need to make Y as 1.

(CC0, CC1)
(1, 1)
(2, 3)

(1, 1) (1, 1) X

Y
(3, 6)

(1, 1) (2, 2)

Difficulty level in making Y as 1 is not

same as difficulty level making X as 1
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Combinational SCOAP Measures
To check sa1
here difficulty
level 2+3

(CC0, CC1)
(1, 1) 5
(2, 3) 0+2+1=3

(1, 1) (1, 1) 5 X

Y
(3, 6) 0

(1, 1) 5 (2, 2)
0+3+1=4
To check sa1 here
difficulty level 2+4
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Combinational SCOAP Measures

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References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 6B:
Introduction to Automatic Test Pattern
Generation

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testing
Thermal Imaging.
Powering up the chip and application of few test pattern and using high resolution IR camera
to capture hot and cold areas of chip.

https://www.infratec.eu/thermography/thermography-on-the-trail-of-the-fault/

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ATPG
Random Test Pattern &
Sensitization , Propagation and Justification

Netlist

Fault list Faults for

SCOAP
A0, A1, RTP & SPJ
B0…

ATPG

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ATPG
Functional Versus Structural Testing

𝐹𝑢𝑛𝑐𝑡𝑖𝑜𝑛𝑎𝑙 𝑇𝑒𝑠𝑡 𝑉𝑒𝑐𝑡𝑜𝑡𝑠 2129 = 6.8 ∗ 1038

𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑡𝑖𝑚𝑒 𝑤𝑖𝑡ℎ 𝐶𝑙𝑜𝑐𝑘 𝑜𝑓 1 𝐺𝐻𝑧 ≈ 22 𝑦𝑒𝑎𝑟𝑠

𝑀𝑎𝑥 𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 64 ∗ (10 + 17)

𝐴𝑐𝑡𝑎𝑢𝑙 𝑆𝑡𝑟𝑢𝑐𝑡𝑢𝑟𝑎𝑙 𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑐𝑜𝑢𝑙𝑑 𝑏𝑒 𝑠𝑚𝑢𝑐ℎ 𝑙𝑒𝑠𝑠𝑒𝑟𝑎𝑠 𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑒 𝑠 − 𝑎

𝑓𝑎𝑢𝑙𝑡𝑠 𝑔𝑒𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝑤𝑖𝑡ℎ 𝑠𝑖𝑛𝑔𝑙𝑒 𝑣𝑒𝑐𝑡𝑜𝑟
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ATPG
Logic design of a 32-bit ripple-carry adder.

The first seven vectors cover all stuck-at faults. One may, therefore, use only the
first seven vectors in the manufacturing test.
Possible only for Modular Structures.

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Types of ATPG Algorithm
1. Exhaustive.
In this approach, for an n-input circuit, we generate all input patterns.

The circuit is partitioned into cones of logic, each with 15 or fewer inputs. We can then
perform exhaustive test-pattern generation for each cone.

However, those faults that require multiple cones to be activated in a synergistic way
during testing may not be tested.

Vast changes in compute time, depending on the order in which circuit PIs are
expanded in the BDD
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Types of ATPG Algorithm
2. Random – Used With Algorithmic Methods

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Types of ATPG Algorithm
3. Deterministic ATPG
Symbolic – Boolean Difference

𝐹 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐴
𝐹 = 𝐴ҧ 𝐵𝐶 + 𝐴 𝐵 + 𝐶 + 𝐵𝐶 𝑆ℎ𝑎𝑛𝑜𝑛
𝐹 = 𝐴ҧ 𝐵𝐶 + 𝐴 𝐵 + 𝐶

𝐹𝑔 = 𝐵𝐶⨁ 𝐵 + 𝐶 =1
𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟(𝑏, 𝑐) = 1,0 , 0,1 S-a-0 at A
𝛿𝐹 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐴
𝐵𝑜𝑜𝑙𝑒𝑎𝑛 𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑐𝑒, 𝑜𝑟 𝐵𝑜𝑜𝑙𝑒𝑎𝑛 𝑝𝑎𝑟𝑡𝑖𝑎𝑙 𝑑𝑒𝑟𝑖𝑣𝑎𝑡𝑖𝑣𝑒 =
𝛿𝐴 𝛿𝐴
𝛿𝐹 (𝐴𝐵+𝐶𝐴)
= 𝐵𝐶 = 𝐵𝐶 𝐵 + 𝐶 = (𝐵ത + 𝐶)ҧ 𝐵 + 𝐶 = 𝐵𝐶
ത + 𝐵 𝐶ҧ
𝛿𝐴 𝛿𝐴

𝑊𝑒 𝑐𝑎𝑛 𝑔𝑒𝑡 𝑡ℎ𝑒 𝑡𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 𝑏𝑦 𝑚𝑒𝑟𝑒 𝑏𝑜𝑜𝑙𝑒𝑎𝑛 𝑎𝑙𝑔𝑒𝑏𝑟𝑎

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Types of ATPG Algorithm
3. Deterministic ATPG
Symbolic – Boolean Difference
For few variables

𝐹 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐴
𝐹 = 𝐴ҧ 𝐵𝐶 + 𝐴 𝐵 + 𝐶 + 𝐵𝐶 𝑆ℎ𝑎𝑛𝑜𝑛
𝐹 = 𝐴ҧ 𝐵𝐶 + 𝐴 𝐵 + 𝐶
𝐹𝑔 = 𝐵𝐶⨁ 𝐵 + 𝐶 =1
𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟(𝑏, 𝑐) = 1,0 , 0,1 S-a-0 at A

BC BC BC
00 01 11 10 00 01 11 10 00 01 11 10
0 0 1 1 1 0 0 0 1 0 0 0 1 0 1
A A A
1 0 0 1 0 1 0 1 1 1 1 0 1 0 1
ҧ + 𝐵𝐶 + 𝐶 𝐴ҧ
𝐹 = 𝐴𝐵 𝐹 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐴
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Types of ATPG Algorithm
3. Deterministic ATPG
𝐹 = 𝐴𝐵 + 𝐶
𝐹 = 𝐴ҧ 𝐶 + 𝐴 𝐵 + 𝐶 𝑆ℎ𝑎𝑛𝑜𝑛

𝐹𝑔 = 𝐶⨁ 𝐵 + 𝐶 =1
𝑇𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟(𝑏, 𝑐) = 1,0 S-a-0 at A

𝛿𝐹 𝛿(𝐴𝐵 + 𝐶)
= ҧ
= 𝐶𝐵
𝛿𝐴 𝛿𝐴
BC BC BC
00 01 11 10 00 01 11 10 00 01 11 10
0 0 1 1 1 0 0 1 1 0 0 0 0 0 1
A A A
1 0 1 1 0 1 0 1 1 1 1 0 0 0 1
ҧ +𝐶
𝐹 = 𝐴𝐵 𝐹 = 𝐴𝐵 + 𝐶
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ATPG Algebra
The ATPG algebra is a higher-order Boolean set notation with the purpose of
representing both the “good” and the “failing” circuit (or machine) values simultaneously.
This has the advantage of requiring only one pass of ATPG to determine
signal values for both machines.
Since a test vector requires that a difference be maintained between the two machines, it is
computationally fastest to represent both machines in the algebra, rather than maintaining
them separately.

0 d 0/1

1 c 0/1
e 0/1

0/1 & 1/0 are not Boolean variables

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ATPG Algebra
Roth showed how multiple-path sensitization, required to test certain combinational circuits,
could be done with his five-valued algebra given in Table below.

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ATPG Algebra

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ATPG Algebra
D algebra Single Fault

D D D
𝟎 𝑫 𝑫

0 1 D

ഥ
𝑫 ഥ
𝑫 ഥ
𝑫
𝟎 ഥ
𝑫 ഥ
𝑫

0 1 ഥ
𝑫

X X 𝟎
𝑿
1 0

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D Algebra
Forward implication

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Types of ATPG Algorithm
3. Deterministic ATPG
Sensitization , Propagation and Justification. Many Iterations may be
required. Different Paths and Simultaneous Multiple paths may be required

1. Sensitization: Test Vector D to detect s-a-0 at B

2. Propagation: Select Path B-f-h-k-L
3. Justify: For Path B-f-h-k-L (A=1 , E=1, j=0, i=1(Conflict as i cannot be made 1)
4. Iteration Propagation: Select Path B-g-i-j-k-L
5. Justify (A=0 , E=1,C=1), i= 𝑫, j= , k= L=
In one go Normal and Faulty o/p obtained ABCD (0111) L= 0 Good, L=1 B s-a-0
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Redundancy Definition for Testing Purposes

1 1
1

Combinational ATPG algorithms provide a major side benefit. They can determine when
the circuit has unnecessary, or redundant, hardware.
In combinational circuits untestable faults indicate redundant hardware.
In testing, one can remove redundant hardware and the circuit will still function exactly
the same way as before.
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Static Glitch Example

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Static Glitch Elimination

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Static Glitch Elimination

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Redundancy in Testing

0 1
1

D D

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References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 07:
Automatic Test Pattern Generation for
Combinational Circuits

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ATPG Algorithm

Roth’s D-Algorithm (D-ALG) , established the calculus and algorithms for ATPG using
D-cubes.

The next development was Goel’s PODEM algorithm. He efficiently used path
propagation constraints to limit the ATPG algorithm search space, and introduced the
notion of backtrace.

The third significant development was Fujiwara and Shimono’s FAN algorithm . They
efficiently constrained the backtrace to speed up search, and took advantage of signal
information to limit the search space.

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Prime Implicants
F = AB + ABC + A’C.

BC BC
00 01 11 10 00 01 11 10
0 0 1 1 0 0 0 1 1 0
A A
1 0 0 1 1 1 0 0 1 1

Prime Implicants = AB + BC + A’C. Essential Prime Implicants = AB + A’C.

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D-Calculus and D-Algorithm (Roth)

Definition 1. The singular cover of a logic gate is the minimal set of input signal
assignments needed to represent essential prime implicants in the Karnaugh map of that
logic gate, for both output cases of 0 and 1.

AND NOR NAND

NAND
B B B b c e
0 1 0 1 0 1 1 1 0
0 0 0 0 1 0 0 1 1 0 X 1
A A A
1 0 1 1 0 0 1 1 0 X 0 1

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D-Calculus and D-Algorithm (Roth)

Definition 2. The D-frontier consists of all gates whose output value is currently x but have
one or more error signals (either D’s or D’s) on their inputs. Error propagation consists of
selecting one gate from the D-frontier and assigning values to the unspecified gate inputs so
that the gate output becomes D or D. This procedure is also referred to as the D-drive
operation. If the D-frontier becomes empty during the execution of the algorithm, then no
error can be propagated to a PO. Thus an empty D-frontier shows that backtracking should
occur.

D
sa0

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D-Calculus and D-Algorithm (Roth)

Definition 3. The Unique D-frontier. There is only one gate in the D-frontier and the fault
needs to be propagated through it.

D D
D
X
sa0 0

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D-Calculus and D-Algorithm (Roth)

Definition 4. The J-frontier. To keep track of the currently unsolved line-justification

problems, we use a set called the J-frontier, which consists of all gates whose output value is
known but is not implied by its input values.

D D
D
D
sa0 0

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D-Calculus and D-Algorithm (Roth)

Definition 4. The J-frontier. To keep track of the currently unsolved line-justification

problems, we use a set called the J-frontier, which consists of all gates whose output value is
known (requirement) but is not implied by its input values.

1
D
D D
sa0 0

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D-Calculus and D-Algorithm (Roth)

Definition 5. A Propagation D-cube is a collapsed truth table entry that can be used to
characterize an arbitrary logic block..

AND gate propagation D-cube D,1,D or D’, 1, D’ or D,D,D or D’,D’,D’

OR gate propagation D-cube D,0,D or D’,0, D’ or D,D,D, or D’,D’,D’

NOR gate propagation D-cube D,0,D’ or D’,0, D

NAND gate propagation D-cube D,1,D’ or D’,1, D

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D-Calculus and D-Algorithm (Roth)

Definition 6. Primitive D-cubes of failure (PDCF) model faults in a logic circuit, and can
model any (1) stuck-at-0 fault, (2) stuck-at-1 fault, (3) bridging fault (short
circuit), or (4) arbitrary change in logic gate function (e.g., from AND to OR.)

AND Sa0 PCDF 11D

OR Sa0 PCDF ? X1D or 1XD

OR Sa1 PCDF ? 00D’

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D-Calculus and D-Algorithm (Roth)

Definition 7. Forward implication results when the inputs to a logic gate are significantly
labeled so that the output can be uniquely determined. Gate is removed from D-frontier List

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D-Calculus and D-Algorithm (Roth)

Definition 8. Backward implication is the unique determination of all inputs of a gate for
given output and possibly some of the inputs.. Gate is removed from J-frontier List

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D-Calculus and D-Algorithm (Roth)

Procedure.

1. Pick a fault from the Fault table for a node

2. Select e PDCF for the fault.
3. D-Drive : Propagate the fault choosing from the D-frontier gates (Forward implication)
4. Back Propagate to get consistent inputs. If inconsistently encountered back track and
chose alternate path.

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D-Calculus and D-Algorithm (Roth)

Step A B C E F H G1 G2 G3 G4 G5 G6
1. Choose a fault. 1 1 X X X X D X X X X X PCDF G1
Sa0 at G1. DF{G3}
2. Forward 1 1 X X X X D 0 D X X X JF{G2}
Implication DF{G5. G6}
3. Forward 1 1 X X X X D 0 D 0 D X JF{G2, G4}
Implication
Choose G5
4. Backward 1 1 X 0 X X D 0 D 0 D X JF{G2}
Implication
5.Backward 1 1 1 0 X X D 0 D 0 D X Done
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D-Calculus and D-Algorithm (Roth)
0
E
0
D
1
D
D
1
0
1
Step A B C E F H G1 G2 G3 G4 G5 G6
1. Choose a fault. 1 1 X X X X D X X X X X PCDF G1
Sa0 at G1. DF{G3}
2. Forward 1 1 X X X X D 0 D X X X JF{G2}
Implication DF{G5. G6}
3. Forward 1 1 X X X X D 0 D 1 D X JF{G2, G4}
Implication
Choose G5
4. Backward 1 1 X 0 X X D 0 D 0 D X JF{G2}
Implication
5.Backward 1 1 1 0 X X D 0 D 1 D X Done
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D-Calculus and D-Algorithm (Roth)

Step 1 2 3 4 5 6 7 8 9 10 11 12
1. Choose a fault. X 1 1 X X D’ X X X X X X PCDF G2
Sa0 at G2. DF{G5,G6}
2. Choose G5. 1 1 1 X X D’ X X D X X X DF{G8}
Forward Implication
3. Forward 1 1 1 X X D’ X 1 D 1 1 D’ JF{G4, G6,G7}
Implication.
4.Backward 1 1 1 0 0 D’ 0 1 D 1 1 D’ JF{G1, G3}
Implication
5.Backward 1 1 1 0 0 D’ 0 1 D D 1 X Contention for G7
Implication
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D-Calculus and D-Algorithm (Roth)

Step 1 2 3 4 5 6 7 8 9 10 11 12
1. Choose a fault. X 1 1 X X D’ X X X X X X PCDF G2
Sa0 at G2. DF{G5,G6}
6. Choose G5 & G6 1 1 1 1 X D’ X X D D X X DF{G8}
7. Forward 1 1 1 1 X D’ X 1 D D 1 D’ JF{G4, G7}
Implication.
8.Backward 1 1 1 1 0 D’ 0 1 D D 1 D’
Implication

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D-Calculus and D-Algorithm (Roth)

Advantage

1. D algorithm is complete ATPG Guarantee to generate a pattern for a testable fault

Disadvantage

1. Internal nodes are also assigned values hence the search space is large
2. Does not help in choosing best D-Frontier and relies on back tracking

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PODEM

1. Only allow assignments to PI only

Doesn’t assign internal nodes
Greatly reduces search tree

2. Assigned PI are then forward implication

No justification needed

3. Flip last PI assignment when two conditions:

A. Fault not activated
B. No propagation path to any output

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PODEM

G4
G5
1
D
G1 sa0
1 D
G3
0 G6
G2
1

1. Choose A=1 B=1 to det D at the desired fault location

2. Use G3 to Propagate. Single Option. C=1
3. Choose G6 easiest path to propagate . Level or SCOAP analysis will give the easiest path.
4.H=1. C=1 Depth First

Minimum number of logic gates between the start of the path and any PO. Objectives were
selected by level to pick the easiest objective to achieve. After objectives were selected,
backtracing determined PI assignments to justify these objectives.
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PODEM

𝑇𝑒𝑠𝑡 𝑉𝑒𝑐𝑡𝑜𝑟 𝑖𝑠 "11𝑋" 𝑎𝑛𝑑 𝑟𝑒𝑠𝑝𝑜𝑛𝑠𝑒 "0𝐷𝑋"

The basic idea of PODEM is to limit the search space to primary inputs without
compromising the completeness. That is done by using the backtrace
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FAN
Test Vector for sa1 at L

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FAN

Headlines. Fujiwara and Shimono developed the notion of headlines, which are points
where the circuit can be partitioned such that a cone of logic driven by PIs can be isolated
from the rest of the circuit by cutting a single line, called the headline. This means that
either a logic 0 or a logic 1 can be justified from the headline back to the circuit PIs.

H and J are headlines

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FAN

PODEM will make six backtraces to justify C=0. The first backtrace sets objectives of
B=1 and A=0 and finally assigns PI1 as 1. This process is laboriously repeated five more
times until we have PI2 =1, PI3 =1, PI4=1 PI5=1 and PI4=1 as internal node are not
assigned any value. This is happening because PODEM backtraces in a depth-first
fashion.
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FAN

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References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 08:
Testing of Sequential Circuits

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Sequential Circuit

Primary Next Output Primary

I/Ps O/Ps
State FFs State
Logic Logic

Clk
pseudo-primary inputs (PPIs) or present state (PS)

Testing of Combination Blocks is similar to that we studied earlier

Difference being that the inputs from FFs are not directly controllable

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Sequential Circuit

Design of sequence detector overlapping (1001)

NS
Clk

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Sequential Circuit Testing

1. The circuit contains internal memory whose state is not known at the beginning of the
test. The test must, therefore, initialize the circuit to a known state.

2. After test inputs are applied, the final state of the internal memories must be inferred
only indirectly from primary outputs. Only in special cases can the internal memory be
made controllable and observable for testing, sometimes at the cost of extra hardware

3. Test for a fault in sequential logic essentially contains

(a) initialization of the internal memory,
(b) a combinational test to activate the fault and bring its effects to the boundary
of the combinational logic,
(c) if the fault has affected one or more memory elements, then observation of the
state of one of the affected elements at a primary output.

Thus, the test of a fault may be a sequence of several vectors that must be applied in the
specified order.

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ATPG for Single-Clock Synchronous Circuits

Time-Frame Expansion Method

➢ Tests generated by a combinational ATPG method.
➢ Very efficient for circuits described at the Boolean gate-level.
➢ Its efficiency degrades significantly with cyclic structure, multiple-clocks, or asynchronous
circuitry.

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ATPG for Single-Clock Synchronous Circuits
Time-Frame Expansion Method
Eg. Serial Adder 1. Test Vector for Sensitisation? 11
2. Value of Cn for Propagation? 1 or 0

3. Initialisation Test Vector for? {00,01,

10,11}

Initialisation may or may

not sensitise

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ATPG for Single-Clock Synchronous Circuits
Time-Frame Expansion Method
Eg. Serial Adder

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ATPG for Single-Clock Synchronous Circuits

Assumptions

➢ Single Synchronized Clock for all FFs

➢ Single Stuck-at Faults in Next Stage and Output Stage Blocks
➢ No faults internal to FFs
➢ No Faults in Clock Path

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Time-Frame Expansion with D Algorithm

1. Which are the Next Stage and Output Stage Blocks

Test vector to detect sa0 at a ? (1,X) puts “D with f2=1 it gets propagated to Z

Test vector for initialization ? (X,1)

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Time-Frame Expansion with D Algorithm

Test vector to detect sa0 at d ? (X,1) puts “D” at d

Next vector? (1,X) propagates “D” to output

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Time-Frame Expansion with D Algorithm

Test vector to detect sa0 at f3 ? (X,1) puts “D” at f3

Next vector? (X,0) propagates “D” to f1

Next vector? (1,X) propagates “D” to Z

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Time-Frame Expansion with D Algorithm

Definitions
1. Sequential Depth of FF
(a) Sequential Depth is one if O/P of FF controlled by Primary I/Ps
(b) Sequential Depth is n if O/P of FF controlled by Primary I/Ps and also by at least one
Sequential Depth n-1 FF

2. Sequential Circuit is Non-Cyclic there are no FFs whose I/P is dependant on its O/P

Cyclic

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Time-Frame Expansion with D Algorithm
Step 1: Replace all FFs with nets and Perform D algorithm

Sa0

a b c F1 F2
T=0 X 0 1 X 1
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Time-Frame Expansion with D Algorithm
Step 2: A sequential FFs of depth n can can be set to required value in max n clock cycles

Sa0

D
a b c F1 F2
T=0 X 0 1 X 1
T=-1 X 1 X 1 X

9/10/2023
T=-2 1 X X X X 14

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Time-Frame Expansion with D Algorithm

Sa0

b=1

a b c d e F1 F2
T=0 X 1 1 1 0 1 1
T=-1 1 1 X X X 1 X
T=-2 1 X X X X X X
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Time-Frame Expansion with D Algorithm

Sa0

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Time-Frame Expansion with D Algorithm

Test vector to detect sa1 at A ? A=0 puts D’ at A, But cannot initialise FF1 to 0

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Time-Frame Expansion with Muth Algorithm

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Time-Frame Expansion with 9-Valued Algorithm

Can 9-Valued Algorithm Be used for Combinational Circuit?

Yes, but not recommended as complexity increases without significant gain
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Time-Frame Expansion with D Algorithm

Sa0

After Initialising FF to 0

Sa0

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Time-Frame Expansion with Muth Algorithm

Sa0

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Time-Frame Expansion for Cyclic Circuits
A modulo-3 counter without initialization input
00->01->10->00

Consider the fault Z s-a-0. For any input, the output will be X/0.

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Time-Frame Expansion for Cyclic Circuits
A modulo-3 counter without initialization input
00->01->10->00

Requires
FF1=1 and
FF2=1 as
initial state

the CLR input will set the circuit in state. Since the state is set on the application of
the clock after CLR becomes 1, this operation is called synchronous initialization

Asynchronous clear and preset signals are also effective.

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Clock Faults and Multiple-Clock Circuits

Our discussion so far has focused on single-clock circuits. All flip-flops were
controlled by one clock, which was a primary input to the circuit. For test generation
this clock was modeled only implicitly. That is why many of our circuit diagrams
show flip-flops without clock signals. It was assumed that one input vector is applied
per clock cycle This approach provides simplicity to test generation. However, there is a loss
of generality.

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Clock Faults and Multiple-Clock Circuits
An explicitly clocked flip-flop with asynchronous clear.

The logic in the shaded region in Figure is used for modeling the function of the
flipflop. Faults inside this logic are usually not modeled.

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Simulation-Based Sequential Circuit ATPG
CONTEST Algorithm

In Phase 1 initialization vectors are generated. The purpose of these vectors is to bring
flipflops in the circuit to known states irrespective of their starting state.

Phase 2 begins with vectors that are either supplied by the designer or generated in Phase 1.
A fault list is generated in the conventional manner. For example, this list may
contain all single stuck faults or a subset of such faults. These faults are simulated
using a fault simulator. If the coverage is adequate, the test generation would stop.
Otherwise, tests are generated with all undetected faults as targets. In the initial
stages of test generation, the fault list is usually long and the objective of this phase
is to generate tests by concurrently targeting all undetected faults.

Phase 2, if the fault coverage has not reached the required level then Phase 3 is
initiated. In this phase, test vectors are generated for single faults targeted one at
a time.

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Simulation-Based Sequential Circuit ATPG
CONTEST Algorithm
Phase 1: Initialization. Here, the cost is defined simply as the number of flipflops that are
in the unknown state. Initially, the cost may be equal to the number of flip-flops in the
circuit. The goal in the initialization phase is to reduce this cost to 0. This cost function is
derived only from good circuit simulation and is not related to the faulty circuit behavior.
If the circuit is hard to initialize, one may relax the criterion for exiting to the next phase
by allowing a small number of flip-flops, say 10%, to remain uninitialized.

0
1
After simulation of a trial vector, the “trial cost” is computed as the number of flip-flops that are in the
unknown state. If the trial cost is lower than the current cost, then the trial vector is saved. If the trial cost
is zero, then the initialization phase is complete
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Simulation-Based Sequential Circuit ATPG
CONTEST Algorithm

Phase 2: Concurrent fault detection. The initialization vectors may already have detected
some faults. Some others may have been activated but not detected. As a result, effects of
active faults will be present at internal nodes of the circuit. a suitable cost function is the
shortest distance to a primary output from any fault effect caused by the fault.

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Simulation-Based Sequential Circuit ATPG
CONTEST Algorithm

Video lectures by Professor James Chien-Mo Li

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Simulation-Based Sequential Circuit ATPG
CONTEST Algorithm

When there are several undetected faults, cost is computed for each fault i for some
input vector and internal state. Similarly, the cost is obtained for a candidate trial
vector. A comparison of and determines whether to accept the candidate vector or
reject it. Since there can be several undetected faults, there are two lists of cost
functions instead of just two numbers. The search for tests should be guided by a
group of faults instead of a single target fault. One can devise simple rules to
determine the acceptance of a vector. For example, if the combined cost of
10% of the lowest-cost undetected faults is found to decrease, then the new vector
may be accepted.

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Simulation-Based Sequential Circuit ATPG
CONTEST Algorithm
Phase 3: Phase 3: Single fault detection. The cost function in this phase is based on a
SCOAP-like testability measure.

Dynamic Controllability

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Simulation-Based Sequential Circuit ATPG

Dynamic Controllability

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Simulation-Based Sequential Circuit ATPG

Dynamic Observability

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Simulation-Based Sequential Circuit ATPG

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References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

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Testability of VLSI

Lecture 09:
Testing of Memory

By Dr. Sanjay Vidhyadharan

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Types of Memory
1.Dynamic Random Access Memory (DRAM) has the highest possible density but a slow
access time of 20 ns. Bits are stored as charge on a single capacitor, but the memory must be
refreshed, typically every 2, 4, or 6 ms, if information is not to be lost. 32 GB RAMS
available.

Synchronous DRAM (SDRAM)

DDR (Double Data Rate) DRAM Pipeling hence faster DDR does not wait for completion
of previous read/write operation to continue other operation.

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Types of Memory

2. Static Random Access Memory (SRAM) has the fastest possible speed, with a 2 ns
access time. Bits are stored in cross-coupled latches, and the memory need not be refreshed.

3. Cache DRAM (CDRAM) combines both SRAM and DRAM on the same chip, in order
to accelerate block transfer between the SRAM cache and the slow DRAM.

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Types of Memory

4. Read-Only Memories (ROMs/EPROMs/EEPROMs) have every bit content

programmed by the presence or absence of a transistor at manufacturing time, and do not
lose information when power is shut off.

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Memory Organization

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Memory Testing

➢ Whole Chip not discarded for a single fault. Fault detecting and correction

➢ Static faults

➢ Cells, Decoder etc

➢ Dynamic Fault

➢ Write time, Access Time and Data retention time

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Fault Models

➢ Stuck-at faults

➢ Transition faults

➢ Coupling faults

➢ Neighborhood pattern sensitive fault

➢ Address decoder fault

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Fault Models
1. Stuck-at faults

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March Test Notation

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March Test Notation
MATS+

M. S. Abadir and J. K. Reghbati, “Functional Testing of Semiconductor Random

Access Memories,” ACM Computing Surveys, vol. 15, no. 3, pp. 175–198, Sept. 1983.
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Fault Models
3. Coupling Faults
A coupling fault (CF) means that a transition in memory bit j causes an unwanted change in
memory bit i. The 2-coupling fault is a coupling fault involving two cells. A write operation
that generates an↑ or in transition in cell j changes the contents of cell i. The 2-coupling
fault is a special case of the k-coupling fault, which has the 2-coupling fault behavior with
respect to cells i and j, except that faulty behavior occurs only when another k – 2 cells are
in a particular state.

3.1 Inversion Coupling Faults:

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Fault Models
3.1 Inversion Coupling Faults:

Not all linked CFins can be detected by march tests

Consider three cells i, j, and k (with address relationships Address(i) < Address(j) <
Address(k).) Cell k is coupled to cell i and to cell j, and both i and j are visited either before or
after k is visited by a march element.
Using the sequence and/or its reverse. In this case:
(i) The two CFins will mask each other for any march element marching ‘up’, and (ii)
Neither will be triggered for an element marching ‘down’. Therefore, the march test fails to
detect the linked CFins.
For all cells that are coupled, each should be read after a series of possible CFins may
have occurred (due to writing into the coupling cells), and the number of coupled cell
transitions must be odd (to prevent the CFins from masking each other.)
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Fault Models
3.2 Idempotent Coupling Faults:

3.3 Dynamic Coupling Faults:

A dynamic coupling fault (CFdyn) occurs between
cells in different words. A read or write operation on one cell forces the contents of
the second cell either to 0 or 1. This is a more general case of the Cfid.

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Fault Models
4. Bridging Faults

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Fault Models
5.

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Fault Models

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Fault Models

6.1 Active NPSF (ANPSF) [645] (also called dynamic), the base cell changes due to a
change in the pattern of the deleted neighborhood. One deleted neighborhood cell has a
transition, while the rest of the neighborhood (including the base cell) has a given pattern.

6.2 Passive NPSF (PNPSF) means that a certain neighborhood pattern prevents the base
cell from changing

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Fault Models

7. Address Decoder Faults

An address decoder fault (AF) represents an address decoding error, in which we assume
that the decoder logic does not become sequential [491, 659]. We also assume that the fault
is the same during both read and write operations. We discuss only bit-oriented memory, in
which each word contains only.
Van de Goor [688] classifies these faults into four cases:
Fault 1: No cell is accessed for a certain address,
Fault 2: No address can access a certain cell,
Fault 3: With a particular address, multiple cells are simultaneously accessed, and
Fault 4: A particular cell can be accessed with multiple addresses.

A march test satisfying Conditions 1 and 2 in Table 9.8 detects all

address decoder faults

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Reduced Functional Fault Modeling

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Reduced Functional Fault Modeling

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Multiple Fault Models
Linkage. Faults may also be linked meaning that a fault may influence the behavior of other
faults. Unlinked faults do not influence the behavior of other faults

Fault Masking Example

Goor’s [688] march test

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Functional RAM Testing with March Tests

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Functional RAM Testing with March Tests

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Functional RAM Testing with March Tests

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Functional RAM Testing with March Tests

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Functional RAM Testing with March Tests
MATS+ detection of cell (2, 1) multiple address decoder faults.
where cell (2, 1) is unaddressable, and address (2,1) maps instead to an access of cell (3, 1).

Gets detected as r0 is
done before wo
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Neighborhood Pattern-Sensitive Faults

Assumptions. We always assume that read operations of memory cells are fault-free in the
NPSF testing algorithms
1.There are two different possible values for the base cell (0 and 1),
2. k – 1 ways of choosing the deleted neighborhood cell which must undergo one of two
possible transitions
3. 2k-2 possibilities for the remaining neighborhood cell
4. The total number of active neighborhood patterns

2 states
of base
states of cell
cell
not under
Two transitions of transition
the selected
One cell selected neighbouring cell
at time for For each of the deleted neighborhood patterns, the two
transition possible transitions and must be verified .

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Neighborhood Pattern-Sensitive Faults

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Neighborhood Pattern-Sensitive Faults

Optimal Write Sequences. It is essential to minimize the number of writes during

NPSF testing, in order to obtain the shortest possible test
A Hamiltonian sequence is used for writing during static neighborhood pattern
sensitive fault (SNPSF) Patterns in a k-bit Hamiltonian sequence differ by only 1 bit from
their preceding pattern, as this minimizes the number of writes needed to generate the
patterns. The Gray code is a Hamiltonian sequence.
PNPSFs and ANPSFs are tested with an Eulerian sequence.
There is an arc between two nodes, if and only if they differ by exactly one bit. An Eulerian
sequence traverses each arc in the graph exactly once, while a Hamiltonian sequence traverses
each node in the graph exactly once.

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Neighborhood Pattern-Sensitive Faults

Testing Neighborhoods Simultaneously. When a cell is written, we change k different

neighborhoods (Type-1 or Type-2.) We wish to test the neighborhoods
simultaneously, using the tiling and two-group methods

Tiling Method. The tiling method totally covers memory with non-overlapping
neighborhoods. Reduces the pattern length from

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Neighborhood Pattern-Sensitive Faults

Testing Neighborhoods Simultaneously. When a cell is written, we change k different

neighborhoods (Type-1 or Type-2.) We wish to test the neighborhoods
simultaneously, using the tiling and two-group methods

Two-Group Method. For the two-group method, a cell is simultaneously a base

cell in one group and a deleted cell in the other group, and vice versa

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Testing RAM Technology and Layout-Related Faults

The problems with the prior memory testing approaches are that DRAMs may be repaired or
may have their address lines deliberately scrambled. As a result, consecutive addresses may not
be adjacent, so the previously described coupling fault tests will not be effective.

1. Geometry optimisation introducing folding;

2. Address decoder optimisation; ell area optimisation by sharing contacts and well
areas;
4. Speed and robustness optimisation based on bitline twisting;
5. Yield optimisation by introducing redundancy
6. Achieving I/O pin compatibility utilising address or data line swap.

A. J. van de Goor and I. Schanstra, "Address and data scrambling: causes and impact on memory tests,"
Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002,
Christchurch, New Zealand, 2002, pp. 128-136, doi: 10.1109/DELTA.2002.994601.

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Testing RAM Technology and Layout-Related Faults

Dekker performed this analysis [193, 194, 195] and found faults caused by actual defects
modeled as broken wires, shorts between wires, missing contacts, extra contacts, and newly-
created parasitic transistors. He mapped these defects into the following functional faults:
1. SAF in a memory cell.
2. A stuck-open fault (SOF) in a memory cell.
3. A TF in a memory cell.
4. A state coupling fault (SCF) between two memory cells.
5. A CFid between two cells
6. A data retention fault (DRF), caused by a broken pull-up device, in which the
cell loses its contents over time

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Testing RAM Technology and Layout-Related Faults

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Cache RAM Chip Testing

Block diagram of 256K × 16 b Cache DRAM.

1. DRAM Functional Test.

2. SRAM Functional Test
3. Data Transfer Test.
(DRAM/SRAM /RB/WB
4. High-Speed Operation Test
5. Concurrent Operation Test
6. Cache Miss Test

Its organization is 256K words × 16 bits of DRAM core, 8 words × 16 bits of read data buffer (RB), 8
words × 16 bits of write data buffer (WB), and 1K words × 16 bits of SRAM.

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Functional ROM Chip Testing

ROM testing differs from RAM testing, in that the correct data that the ROM should contain is
already known. The SAF model used for ROMs is sometimes a restricted SAF model

The preferred ROM testing method is to cycle the ROM through all of its addresses and
compress the output bit stream at the ROM outputs using a linear feedback shift register
(LFSR) in the automatic test equipment (ATE).

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Electrical Parametric Testing

DC Parametric Tests.

1. Voltage Bump Test

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Electrical Parametric Testing

DC Parametric Tests.
2. Leakage Test

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Electrical Parametric Testing

AC Parametric Tests.
1. Address Set-Up Time Sensitivity

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Electrical Parametric Testing

AC Parametric Tests.
2. Access Time Tests

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Electrical Parametric Testing

AC Parametric Tests.
3. Running Time Tests

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Electrical Parametric Testing

AC Parametric Tests.
4. Tests for Sense Amplifier Recovery Fault. Sense amplifiers can become saturated after
reading/writing a long string of identical data values, at which point
they are too slow to read the opposite data value

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Electrical Parametric Testing

AC Parametric Tests.
5. Test for Write Recovery Fault. Write recovery faults occur when a write is followed by a
read/write at a different address. The two types are read-after-write and write-after-read.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal,–Kluwer Academic Publishers
(2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 10:
Delay Testing

By Dr. Sanjay Vidhyadharan

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Delay Fault

1. The input signal consists of two vectors: Delay tests consist of vector-pairs
2. All input transitions occur at the same time. This, is an idealized illustration though it
closely represents the real situation eve in pipelined structures with FFs.
3. Delay is determined by the last transition, or the delay of the longest combinational path
4. Should considering all possible input vector-pairs, “the longest delay combinational path”
of the circuit is known as the critical path. There can be more critical paths than one if
several paths meet the maximum delay criterion.
5. The delay of critical paths determines the smallest clock period at which the circuit can
function correctly
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Delay Fault

Gates are modeled with equal rise and fall lumped delays that are integer multiples of some
small time unit (nanosecond or picosecond.)

Critical path has a delay of 6 units in the fault-free circuit

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Delay Fault

Single faulty path: Test vector 010→ 100 can only detect delay fault of P3. It masks
delay faults of P1 and P2.

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Path-Delay Test
Definition 1 Path-delay fault. The delay defect in the circuit is assumed to cause the
cumulative delay of a combinational path to exceed some specified duration.
The combinational path begins at a primary input or a clocked flip-flop, contains a
connected chain of gates, and ends at a primary output or a clocked flip-flop. Both switching
delays of devices and transport delays of interconnects on the path contribute to the
propagation delay. For each combinational path in a circuit, there are two path-delay faults
corresponding to rising and falling transitions, respectively.

The specified time duration can be the duration of the clock period (or phase), or the
vector period.

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Path-Delay Test
Definition 2 Non-robust path-delay test. A test that guarantees to detect a path-delay fault,
when no other path-delay fault is present, is called a non-robust test for that path. A path-delay
fault for which a non-robust test exists is called a “singly-testable path-delay fault.

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Path-Delay Test
An example of a non-robust test

Since this is a non-robust test, it is not guaranteed to work when other paths are faulty. For
example, if an additional delay fault ↑ A – C is present (either due to increased routing delay
or due to increase in the delay of the AND gate), then the signal C may remain as constant 0.
Top input node of and gate charge to high slowly or fault within and gate

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Path-Delay Test
Definition 3 Robust path-delay test. A robust path-delay test guarantees to produce an
incorrect value at the destination if the delay of the path under test exceeds a specified time
interval (or clock period), irrespective of the delay distribution in the circuit.

Glitches

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Delay Algebra
Five-valued algebra for path-delay tests

S0 and S1 are steady (without glitch) 0 and 1 values for both vectors V1 and V2.

U0 and U1 specify the final value as 0 and 1, respectively, and leave the initial value
as don’t care or X.

In addition, XX is used to denote both vectors in the don’t care state.

F0 and R1 are falling and rising transitions on the on-path signals.
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Test Generation for Combinational Circuits
Generation of a test for a path-delay fault requires placing the appropriate transition at the
origin of the path and justifying the required off-path inputs of all gates on the path. This is
easily accomplished using the five-valued algebra.

E.g. ↓P3
1. Place a transition at the path origin, B = F0.
2. Propagate value F0 to line E, set C = S0/U0, E = F0.
3. G = F0 J = R1.
4. F0 is interpreted as U0 for off-path logic, Q = U0.
5. Propagate value R1 from J to K, set H = S0 K = R1.
6. Justify H = S0, set A = S0.
7. Test is A = S0, B = F0, C = S0; or V1 = 010, V2 = 000
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E.g. ↑P2
1. Place a transition at path origin, B = R1.
2. Propagate R1 to E, set C = S0.
3. R1 is interpreted as U1 for off-path logic, G = U1 J = U0.
4. Q = R1, Propagate R1 to H, set A = S1.
5. H = R1, Propagate R1 to K, must set J = S0 conflict since J = U0 in step 3.
6. Since no step has any alternatives, a robust test is not possible.

The reliability of non-robust tests is questionable

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Test Generation for Combinational Circuits
The presence of robust tests for some paths can improve the reliability of non-robust tests
for other paths. For example,

are robustly testable.

By including the six robust tests we can ensure that if the circuit passes those, there
will be no delayed signal at off-path inputs of the path P2. We can conclude that in the
presence of the other four tests, the non-robust test for ↑P2 is as good as a robust test.
Such a test is called a validatable non-robust (VNR) test
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Test Generation for Combinational Circuits
Untestable path delay fault.
Consider the path-delay fault P2 . A falling transition (F0) is placed at B and is easily
propagated to H by setting appropriate values on A and C. However, a forward implication sets
the off-path input of the output OR gate to U1 (i.e., controlling value in V2.) This path-delay
fault has no test.

A path for which both (rising and falling) path-delay faults (PDFs) are singly (i.e., non-
robustly) testable is called a testable path. A path having one singly testable PDF and one
singly untestable PDF is called a partially testable path. When no non-robust test exists for
both PDFs of a path, that path is called a singly-untestable path. Such a path can be
eliminated by circuit transformations that preserve the logic function.
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Test Generation for Combinational Circuits
An untestable path is (and a partially testable path may be) associated with one or more
redundant single stuck-at faults

K = A(B+C) + B’C’
K= A +BC

In general, a partially testable path may not have a redundant stuck-at fault.
However, there are procedures for modifying the circuit to expose redundant faults that can
be removed. The resulting circuit always has fewer paths, a greater percentage of testable
paths.

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Test Generation for Combinational Circuits
A combinational circuit may have paths whose delays cannot affect the time of signal
change at the output. These paths are called false paths.

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Test Generation for Combinational Circuits
Fault Simulation Algorithm

1. Vertices in Path-status graph PSG correspond to inputs, outputs and gates with multi-fanouts.
Single fanout are not represented in the PSG.

M. A. Gharaybeh, V. D. Agrawal, M. L. Bushnell, and C. G. Parodi, “False-Path

Removal Using Delay Fault Simulation,” Journal of Electronic Testing: Theory and
Applications, vol. 16, no. 5, pp. 463–476, Oct. 2000.

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Test Generation for Combinational Circuits

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Test Generation for Combinational Circuits
The paths of singly-untestable PDFs are not always false paths. For example, a singly-
untestable PDF may be co-sensitized (sensitized simultaneously) with other singly-
untestable PDFs and the timing of the circuit would be affected if all co-sensitized
paths have excess delays. These paths belong to the classes of multiply-testable PDFs
[245] and functionally sensitizable PDFs [155].

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Transition Faults

➢ Transition fault: A simpler delay fault model

➢ A transition fault on a line makes the signal change on that line slow
➢ The two possible faults are slow-to-rise and slow-to-fall types
➢ For detecting a slow-to-rise fault on a line, we take a test for a stuck-at-0 fault on that
line. This test will set the line to 1 in the fault-free circuit and propagate the state of the
line to a primary output. Two test vectors required : V1 sets the line to 0 and V2 sets it
to 1. V2 also creates an observation path to a primary output.

➢ The basic assumption in this test is that the faulty delay of the signal rise has to be
large, since the observation path may be, and often is, a short path. Besides, the effects
of hazards and glitches can interfere with the observation of the output value. As
a result, the tests for transition faults can detect localized (spot) delay defects of
large (gross) delay amounts. Because of sensitization of short paths these tests may
fail to detect distributed defects, where small delay increases in a large number of
gates cause a long path to fail.

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Transition Faults

The advantages of the transition fault model are:

• The number of faults has an upper bound of twice the number of lines.

• Tests are easy to generate. A stuck-at fault test generator can be easily modified to
produce tests for transition faults.
• Circuits that either have, or are modified to have, a high stuck-at fault coverage
usually also have high transition fault testability.

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Delay Test Methodologies
1. Slow-Clock Combinational Test
This procedure is applicable to combinational circuits or to those sequential circuits that
are internally combinational with flip-flops only at PIs and POs.

A two-vector delay test assumes that all signals due to the first vector V1 will have reached
their steady state when V2 is applied. If this assumption is not valid, then the actual circuit
may still have some transient signals when V2 is applied. These transients can interfere with
the testing of the targeted path. To avoid this problem, vectors are applied at a slower than
the rated clock frequency.
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Delay Test Methodologies
2. Enhanced-Scan Test
This method is applicable to scan types of sequential circuits. Its main advantage is that
any arbitrary vector-pair can be applied. So, delay tests can be generated by considering
the combinational logic alone, making the test generation easier. However, a normal scan
circuit should be enhanced by inserting hold latches and an additional HOLD signal. The
design and operation of the enhanced flip-flop, known as scan-hold flip-flop (SHFF),

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Delay Test Methodologies
3. Normal-Scan Sequential Test
Normal full-scan circuits (with no hold latches) can be tested for delay faults, but the vector-
pairs must be especially generated. Here, the first vector V1 is scanned in (usually with a slow
scan clock) and is then replaced in the scan register by either (a) applying a one-bit shift to the
scan register, or (b) propagating V1 through the combinational logic in the normal mode.

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Delay Test Methodologies
4. Variable-Clock /Slow Clock Non-Scan Sequential Test
Testing of a delay fault in a non-scan sequential circuit requires more than two vectors
like in the case of sequential circuit testing

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Delay Test Methodologies
5. Rated-Clock Non-Scan Sequential Test

All vectors, either functional or those generated to cover any types of faults, are applied at
the rated speed. A target delay fault can be activated in several time frames. If robust
detection is desired, one must consider all delay combinations to be potentially possible.
Even fault simulation requires massive computation. Nevertheless, it shows a much reduced
PDF coverage for vectors generated for variable-clock test.

“Static timing analysis.” done with enough slack in commercial tools like Primetime

➢ Timing simulation
➢ Critical path tests
➢ Layout optimization

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References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal,–Kluwer Academic Publishers
(2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 11:
Design for Testability

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Design for Testability

Observability & Controllability

• Observability: ease of observing a node by watching external
output pins of the chip
• Controllability: ease of forcing a node to 0 or 1 by driving input
pins of the chip
• Combinational logic is usually easy to observe and control
• Finite state machines can be very difficult, requiring many cycles
to enter desired state
– Especially if state transition diagram is not known to the test engineer

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Ad Hoc Design for Testability

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Ad Hoc Design for Testability

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Ad Hoc Design for Testability

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Ad Hoc Design for Testability

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Scan Design

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Scan Design
D flip-flop

A single-clock scan flip-flop

TC Test control (Active Low)

SD Scan data

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Scan Design
A two-clock scan flip-flop

Level-sensitive scan
design (LSSD), uses two
non-overlapping clock
signals.

Normal Operation
When MCK is high, data D is latched in the
master latch. When SCK is high, the state of
master latch is copied in the slave latch
Scan mode
MCK is held low and scan data SD is latched in
by using clocks TCK and SCK as master and
slave clocks
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Scan Design

The SD input of one SFF is supplied by another new primary input SCANIN. All SFFs are
chained by connecting the Q output of one SFF to the SD input of the next SFF. The Q
output of the last SFF in the chain is a new primary output SCANOUT. This design has the
advantage of reducing the effort of test generation. The wiring added for scan design shown in
broken lines. Especially for the case of full-scan, where all flip-flops are scanned,
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Scan Design Rules
R-1: Only D-type master-slave flip-flops should be used. This rule prohibits the use
of other types of flip-flops (JK, toggle, etc.) or other forms of asynchronous
logic (unclocked RS latches, combinational feedback elements.)

R-2: At least one primary input pin must be available for test. In general, flip-flops
can be connected as multiple scan registers, each of which will require a scan-in and
a scan-out terminal. If extra pins are not available, then any normal primary input
can be used as scan-in and any primary output pin can be multiplexed as scan-out.

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Scan Design Rules
R-3: All flip-flop clocks must be controllable from primary inputs. This rule is
necessary for flip-flops to function as a scan register. Some violations of this rule, if
they exist, can be removed by a simple work-around.

The two circuits are

functionally identical, and the
modified circuit satisfies the
rule R-3. It can be converted
into scan design as described in
the previous section.

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Tests for Scan Circuits
Testing of scan circuits is done in two phases.

1.The first phase tests the scan register by a shift test. The circuit is set in scan mode by setting
TC = 0. All flip-flops now form a shift register between SCANIN and SCANOUT. A toggle
sequence, 00110011 . . ., of length nsf + 4 where nsf is the total number of flip-flops, is
applied at SCANIN. The toggle sequence is clocked through the shift register using the
normal clock signal. This sequence produces all four transitions, and in each flip-flop and
shifts the outputs to the observable output SCANOUT. It covers most, if not all, single stuck-at
faults in the flip-flops, and verifies the correctness of the shift operation of the scan register.

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Tests for Scan Circuits
In the second phase of testing, single stuck-at faults in the combinational logic are targeted.
A combinational ATPG program is used to generate test vectors assuming that all flip-flop
outputs are completely controllable and all flip-flop inputs are observable.

Scan register Loading test vectors in

FFs and one normal Scan out results
check
operation clock

Several Pipelined Combinational circuits will be tested parallelly

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Tests for Scan Circuits
Example: A modulo-3 counter
When R = 1, the counter is set to its initial state 00. For R = 0 and C = 1, the state advances
as with each clock. The output Z becomes 1 only for the state 10 and remains 0 for all other
states. When R = C = 0, the counter retains its state.

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Tests for Scan Circuits
Example: A modulo-3 counter

A sequential ATPG program generated 35 vectors to cover 36 of 42 faults in the non-scan

circuit. Few faults are not detectable due to cyclic feedback.
The ATPG program produced 12 vectors for the combinational circuit in the dotted-line box,
having four inputs, C, R, P1, and P2, and three outputs, Z, Q1, and Q2
Converted to scan sequences including a six-vector shift register test, these gave a scan test
sequence of 44 vectors.

(12+2)2+12+4=44
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Multiple Scan Registers
To reduce the time of scan test, sometimes flip-flops are arranged in multiple scan registers. Each
scan register requires separate SCANIN and SCANOUT pins. If extra pins are not available,
added fanouts from normal primary input pins can provide SCANIN signals to scan chains. This
is possible because the normal primary inputs and SCANIN are never simultaneously used
Similarly, the SCANOUT signals can be multiplexed with the normal primary output pins under
the control of the test control (TC) signal. In general, multiple scan registers can have varying
lengths. The length of scanin and scanout sequences depends on the longest register.

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Overheads of Scan Design
The use of scan design has two types of penalties. The scan hardware increases
1. the chip size (area overhead) and
2. slows the signals down (performance overhead.)
1. Gate overhead. Suppose a circuit has gates and flip-flops (each FF consisting of 10
gates). Assume that original flip-flops are replaced single-clock scan flip-flop. Then each
flip-flop adds an overhead of four gates (used in the multiplexer.) The total gate overhead is
computed as:

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Overheads of Scan Design
2. Area overhead. Scan design requires a significant amount of routing that can impact the
chip area. The test control signal (TC) is routed to all flip-flops and the output of each flip-flop
is routed to the scan data (SD) input of the next flip-flop in the scan register chain. The impact
of scan routing on the chip area increase can be reduced by: (a) flip-flop placement on the
layout for optimum routing and (b) selecting the flip-flop order in the scan chain

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Overheads of Scan Design

The combined height of a cell row and one adjoining routing channel is

Depending on the cell height (T) that is around 8-10 tracks, this part can
10/22/2023 contribute up to about 10% in a cell-dominant chip. 20

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Overheads of Scan Design
3. Performance overhead. Scan design also has a performance overhead. The multiplexer of
the scan flip-flop adds delay equivalent to two gate-delays in all clocked paths. In addition,
flip-flop outputs have one extra fanout, which increases the capacitive loading of the signal.
In general, scan design can reduce the clock speed by 5 to 10%.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Overheads of Scan Design
3. Performance overhead. The two-clock design does not insert any gate delay in the data
path. This results in reduced performance penalty. However, the routing of the two
system clocks (MCK and SCK) and the test clock (TCK) requires extreme care. Relative
skews between these clock signals should be carefully controlled for the correct operation in
both normal and scan modes.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Design Automation
1. The full-scan design is considered the best DFT discipline. It can be completely
automated using commercially available design tools

combinational circuit
netlist is generated
by removing flip-flops
and clocks from the
audited netlist

A flow-chart of automated scan design.

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Design Automation
The full-scan design: Physical Design and Timing Verification of Scan

1.Very small delay in scan path. Because there is no logic gate in the scan path, signal
propagation between two consecutive flip-flops of the scan registers may be very quick. A
comparatively larger delay (skew) of the clock signal at the second flip-flop can produce a
race condition.

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Design Automation
The full-scan design: Physical Design and Timing Verification of Scan
2. Large delay in scan path. Because the functional routing gets precedence over
scan routing in the physical design, some parts of the scan path can be slow.
The timing of the scan path should be analyzed to determine a proper clock
frequency used for the scan operation. Sometimes, the scan clock is run slower
than the rated clock of the chip for similar reasons.

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Design Automation
The full-scan design: Physical Design and Timing Verification of Scan

3. Dynamic multiplexers. Scan multiplexers can be economically implemented with

dynamic logic (transmission gates.) However, a potential skew between the TC (test control)
and signals can create a temporary short circuit between the two data inputs of the
multiplexer. If the the two input signals are generated by flip-flops that are in different
states, such a short can change the state of one of them. A static design of a multiplexer
requires more transistors, but does not create a short due to the skew. It should be preferred.
Alternatively, the multiplexer should be integrated within the flip-flop cell and
carefully analyzed for any signal delay problems.

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Design Automation
The full-scan design: Physical Design and Timing Verification of Scan

4. Power dissipation during scan. Scan operation produces many changes at

the inputs of the combinational logic. These can cause significantly higher
power dissipation than the power rating of the device. Both average and peak
power consumption should be controlled. Average power that is responsible for
heating of the chip may be reduced by slowing down the scan clock. Increased
peak power can cause a drop in the supply voltage and create noise problems
in the chip. Its reduction may require redesign of test vectors.

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Design Automation
Partial-Scan Design

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Design Automation
Partial-Scan Design

A sequential ATPG
If we scan FF5 and FF7, program can achieve a
then vertices 5 and 7 will fault coverage in excess
be deleted and the s-graph of 95% when about 25
becomes acyclic with a to 50% of the flip-flops
sequential depth of 2. are scanned.

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Variations of Scan
Scan-Hold Flip-Flop (SHFF.)

In the normal mode, TC = HOLD = 1. In the scan mode, TC = 1 and HOLD = 0. The state
inputs of combinational logic driven by the hold latch remain frozen at their pre-scan values.
1. Isolates the scan and non-scan portions of a circuit.
2. Delay testing requires the application of vector-pairs to a combinational logic problem. The
normal scan structure (with SFFs) places severe restrictions on the vector-pairs that can be
produced. The use of the hold latch converts the delay testing problem completely into a
combinational logic problem.
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Variations of Scan
Scan-Hold Flip-Flop (SHFF.)

1. Set HOLD = 0 and TC = 0, and scan the state variable bits of into the scan register using the clock CK.
2. Set TC = 1.
3. Set HOLD = 1 and apply the primary input portion of Thus the entire vector appears at the inputs of the
combinational logic.
4. Change HOLD to 0.
5. Repeat Steps 1, 2, and 3 for This produces a transition at the
inputs of the combinational logic.
6. Change HOLD to 0, and capture the output of the combinational logic in FF by applying the clock CK.
7. Set TC = 0 and apply clocks to scan out the contents of flip-flops. This completes the application of
one vector-pair delay test.

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Variations of Scan
Random-Access Scan (RAS.)
In the normal mode (TC = 1), all flip-
flops receive data from the
combinational logic under the control of
the clock CK.
In the scan mode, this scheme allows
reading or writing of any selected flip-
flop. The flip-flop address, which may
contain log2nff bits when there are flip-
flops in the RAM, is serially loaded into
an address scan register (ASR) using an
address clock ACK. The address decoder
now produces the select signal SEL = 1
for the addressed flip-flop. The SEL
signals to all other flip-flops remain 0.
The SCANOUT signals of all flip-flops
are tied together to the SCANOUT pin.
An advantage of this method is that any
flip-flop can be observed even when the
circuit is in the normal mode (TC = 1.)
For scanning data into a flip-flop, the
10/22/2023 scan mode (TC = 0) is used. 32

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References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal,–Kluwer Academic Publishers
(2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 12
Built-in Self-Test

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Built-in Self-Test

Gordon and Nadig described the economic impact of signature

analysis and BIST on the first systems that used BIST: two
Hewlett-Packard digital voltmeters, one of them called the HP
3455A. Development time and costs rose roughly 1%. There was a
1% increase in parts cost due to added jumpers and extra ROM
space required in the electronics for signature analysis, but total
factory costs dropped, because of a 5% decrease in other materials
costs.

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Built-in Self-Test
1. There is an extremely high and still increasing logic-to-pin ratio on the chip.
This increasingly makes it harder to accurately observe signals on the device,
which is essential for testing.

2. VLSI devices are increasingly dense and faster with sub-micron feature sizes.

3. There are increasingly long test-pattern generation and test application times.

4. Prohibitive amounts of test data must be stored in the automatic test equipment (ATE.)

5. There is increasing difficulty in performing at-speed (rated clock) testing using

external ATE. For clock rates approaching 1 GHz, at-speed testing with an
ATE is very expensive due to pin inductance and high tester pin costs.

6. Designers are unfamiliar with the gate-level structure of their designs, since
logic is now automatically synthesized from the VHDL or Verilog hardware
description languages. This compounds the problem of testability insertion.

7. There is a lack of skilled test engineers.

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Built-in Self-Test
Complexity. One unfortunate property of large VLSI circuits is that testing cannot
be easily partitioned. Even though each part is fully testable and has a test set that gives 100%
stuck fault coverage, the cascaded connection of the two parts will often have untestable
and redundant hardware and much lower stuck-fault coverage. For design and test
development effort, BIST provides a way to hierarchically decompose the electronic system-
under-test, so this allows sub-assemblies to be first run through a BIST cycle, and if there are
no faults, then boards in the system are run through a BIST cycle.

Quality. Typical quality requirements are 98% single stuck-fault coverage or 100%
interconnect fault coverage. In huge systems, this is attainable only through design for
testability (DFT), and BIST is the preferred form of DFT.

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Built-in Self-Test
Test Generation Problems. It is difficult to carry a test stimulus involving hundreds of chip
inputs through many layers of circuitry to the chip-under-test, and then convey the test result
back through the many circuit layers to an observable point. BIST localizes testing, which
eliminates these problems.

Test Application Problems. In-circuit testing (ICT) used a bed of-nails fixture
customized for the PCB-under-test. The bed-of-nails tester applied
stimuli to the solder balls on the back of the PCB where the component leads were
soldered to the PCB. Power was applied only to the component under test – all others
in the PCB were left unpowered. It was effective for chip diagnosis and board wiring
tests. However, ICT is not effective unless the PCB is removed from the system,
so it is not helpful in system-level diagnosis. Also, surface-mount technology (SMT)
components are often mounted densely on both sides of the board, and the PCB
wire pitch is also too small for accurate probing of the back of the board by the bed of-nails
tester. Therefore, ICT is no longer a solution. BIST, however, solves these
problems by eliminating expensive ATE.

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Built-in Self-Test
1. Chip/Board Area Cost vs. Tester Cost:

There is a slight cost increase due to BIST in design and test development, because of the
added time required to design and add pattern generators, response compacters, and
testability hardware. However, is that this is less costly than test development with ATPG.

2. Chip/Board Area Cost vs. System Downtime Cost

Without BIST, maintenance test requires the presence of an expensive ATE at the site of the
failing system, and this is a significant cost. With BIST, there is no need for an ATE, so this
reduces system test cost. For boards and systems, BIST drastically reduces the diagnosis and
repair cost, by quickly determining and indicating which sub-assembly or component is
faulty, without the extensive labor and equipment normally required.

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BIST Hierarchy

CUT – Circuit-Under-Test

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BIST Implementation

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BIST Pattern Generation
1. ROM : Expensive in chip area. (Test vectors from ATPG)

2. Linear feedback shift register (LFSR) : Uses very little hardware and is currently the preferred
BIST pattern generation method. (Random Test pattern generation. Coverage may not be not 100%)

3. Binary Counters : A binary counter can generate an exhaustive test sequence, but this can use too
much test time if the number of inputs is huge. For example, with 64 inputs and the test-pattern generator
clocked at 100 MHz, this takes 51,240,955.8 hours of test time to generate all patterns. Also, the binary
counter requires more hardware than the typical LFSR pattern generator. (exhaustive testing)

4. Modified Counters: Modified counters have also been successful as test-pattern

generators, but they also require long test sequences.

5. LFSR and ROM: LFSR as the primary test mode, and then generate test-patterns with an ATPG
program for the faults that are missed by the LFSR sequence.

6. Cellular Automaton: In this approach, each pattern generator cell has a few
logic gates, a flip-flop, and connections only to neighboring gates. The cell is
replicated to produce the cellular automaton.

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BIST Pattern Generation
Exhaustive Pattern Generation
Total number of test vectors required ? Is it 28 = 256 ?

1.Partition a large circuit into fanin cones 25 + 25 = 64

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BIST Pattern Generation
Exhaustive Pattern Generation
2. Hardware partitioning (physical segmentation) in which we add extra circuit logic in order
to divide the CUT into smaller subcircuits, each directly controllable and observable. Each of
these is tested exhaustively.

3. Sensitized path segmentation, in which the circuit is partitioned so that sensitizing paths
are set up from PIs to the partition inputs, and then from the partition outputs to the POs. Each
partition is tested individually while the remaining partitions are simulated, so that non
controlling signals are set in the CUT to sensitize and propagate signals in the partition-under-
test.

4. Partial hardware partitioning , combines hardware partitioning for observing signals in

the partition-under-test, and sensitized path segmentation to control inputs to the partition-
under-test
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BIST Pattern Generation
Pseudo-Exhaustive Pattern Generation ( 8 vector testing)
4 X 1 Mux

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BIST Pattern Generation
Pseudo-Exhaustive Pattern Generation ( 20 vector testing)

4 X 1 Mux

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BIST Pattern Generation
Random-pattern testing and fault coverages

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BIST Pattern Generation
Linear-feedback shift-register (LFSR)

Not necessary all 8 possible combinations are generated

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Pseudo-Random Pattern Generation
Linear-feedback shift-register (LFSR)

These patterns have all of the desirable properties of random numbers, but are algorithmically
generated by the hardware pattern generator and are therefore repeatable, which is essential
for BIST. We no longer cover all input combinations, but long test-pattern sequences may
still be necessary to attain sufficient fault coverage.
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Pseudo-Random Pattern Generation

Circuit Initialization
It is very important in random logic BIST to initialize all flip-flops in the circuit when BIST is
used with partial scan.In the real hardware, different chips will randomly initialize their flip-
flops to different values. Initialization problems can be discovered by setting all flip-flops
initially to the X state, running the BIST cycle, and simulating the system in a 3-valued logic
simulator. If the MISR or other response compacter finishes the test session with bits in the X
state, then initialization is not correct. All such uninitializable flip-flops must then be
initialized by adding master set or reset lines to them.
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BIST Response Compaction
1.Compaction – A method of drastically reducing the number of bits in the original circuit
response during testing in which some information is lost. E.g. (Parity checking, Ones
counting, where we count the number of ones in the output responses
from the circuit.

2. Compression – A method of reducing the number of bits in the original circuit response
during testing in which no information is lost, so the original output sequence can be fully
regenerated from the compressed sequence. Compression schemes, at present, are impractical
for BIST response analysis, because they inadequately reduce the huge volume
of data, so we use only compaction schemes.

3. Signature – A statistical property of a circuit, usually a number computed for a circuit from
its responses during testing, with the property that faults in the circuit usually cause the
signature to deviate from that of the good machine.

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BIST Logic Circuits
Single Bit signature register (MISR)

Transition Count Response Compaction

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BIST Logic Circuits
Multiple-input signature register (MISR)

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BILBO
A BILBO is a bank of D flip-flops in the CUT that has test hardware added to make it behave
in one of four modes:
• As ordinary D flip-flops.
• As a linear feedback shift register (LFSR) hardware pattern generator.
• As an LFSR configured to compact a circuit response.
• As a scan chain

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BILBO

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BILBO
Example BILBO in serial scan mode

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BILBO
Example BILBO in LFSR mode.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BILBO
Example BILBO in normal D flip-flop mode.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BILBO
Example BILBO in MISR mode.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Test Point Insertion
When random-logic BIST is used in a circuit, often not all of the faults are detected, either
because of aliasing or because the test-pattern set from the hardware pattern generator is not
rich enough to excite all faults.

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Memory BIST
Most memory BIST schemes exploit the parallelism within the memory device to achieve
a massive reduction in test time (and therefore cost.) This is done by a test mode where
more than one memory cell is accessed with each address, usually by accessing the entire
row of cells on a word line for a single read or write operation.

However, the parallel mechanism makes it difficult to test for memory coupling faults
between cells in the same row, so it may not be appropriate.

Random, or pseudo-random memory BIST is not generally used , because the march tests
achieve higher fault coverages with shorter pattern sequences than random or pseudo-
random memory tests.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Memory BIST

Concurrent BIST – A memory test mechanism where the memory can be tested
concurrently with normal system operation.

Non-Concurrent BIST – A memory test mechanism that requires interruption

of the normal system function in order to perform the testing. The original
memory contents are lost.

Transparent Testing – A memory test mechanism that requires interruption

of the normal system function for testing. The original memory contents are
preserved in the memory after testing is finished.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Memory BIST
Memory BIST requires an address generator or stepper (often an LFSR) and a data
generator. An LFSR is better for march test BIST than a binary counter, because it uses
substantially less area, and can easily be made self-testable . Furthermore, the LFSR can be
adjusted to provide the all-zero pattern and the forward and exact reverse

LFSRs that count up/down in inverse order.

(a) LFSR generates the sequence when initialized to 1.
(b) LFSR generates the sequence

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Memory BIST
The mutual comparator is useful in memory BIST when the memory system has multiple
arrays. We test two or more arrays (in this case 4) simultaneously, by applying the same test
commands and addresses to all 4 arrays. The mutual comparator asserts the Error signal
when one of through disagrees with the other data coming out of the memory arrays. The
comparator eliminates the need to generate the good machine response, and implicitly
assumes that only a minority of the memory array outputs are incorrect at any given time.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Memory BIST
March Test SRAM BIST

10/29/2023 Parallel memory BIST 32

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal,–Kluwer Academic Publishers
(2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 13
Analog and Mixed-Signal Testing

By Dr. Sanjay Vidhyadharan

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Analog Testing Difficulties
1. Modeling Problems. The major difference between analog structural test
and analog functional test is the fault derivation and modeling procedure.

Functional test often assumes that the components are faulty and generates the
fault list using component deviations and catastrophic faults. The circuit parameter values
vary widely, even in good circuits. Deterministic models are inefficient for analog circuits.
Therefore, signals are specified by a nominal value, along with an acceptable range of values
around the nominal value.

Example: Minimum overall gain, Minimum BW

Structural test uses manufacturing defect statistics, and the fault list may be either
catastrophic or parametric.

Example: Shorted resistance, Error in resistance value, unintended bridge resistance

Defects cannot be directly mapped to faults.

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Analog Testing Difficulties
2. Simulation Error. Expected analog circuit signal values (in fault free circuit) are
computed by simulation, whose accuracy is limited by the numerical accuracy of the
simulation algorithm, the simulation assumptions, and by the accuracy of the models of the
parasitic analog devices. Also, process variations cause even good circuits to exhibit a range
of different behaviors.

3. Tester Measurement Error. Measurement errors at the analog circuit tester come from
analog offsets, the effect of the load of the measurement probe on the analog circuit behavior,
and the impedance of the analog probe. Also, random noise is a problem, so analog testers
are limited in bandwidth and measurement accuracy

4. For mixed-signal chips, transporting internal analog signals to output pins may alter
the signal and the circuit functionality. Capacitive coupling between high-frequency
digital signals and analog signals causes additional analog circuit noise. Analog tests
must create a difference in an analog output between the good and bad machines that
lies outside the measurement error of the test fixture and the ATE. Otherwise,
the fault effect is masked by measurement error.

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Analog Testing Difficulties
5. Test Accessibility Problems. Circuit complexity and the inaccessibility of internal
components restrict the use of conventional analog ATE.

6. Information Flow. It is difficult to test circuits by individually testing subcircuits.

Consider the case of two cascaded single-input, single-output analog circuits, C1
and C2 with analog voltage transfer functions H1 and H2. and may behave
unacceptably when tested individually, due to manufacturing imperfections that
distort their transfer functions. However, when cascaded, it could happen that the
distortion in H1 is cancelled by the distortion in H2, which might be, in some sense,
the inverse of the distortion in H1. Therefore, the cascaded combination of C1 and
C2 may actually be acceptable. Conversely, individually acceptable analog circuits,
when cascaded, may produce an unacceptable circuit.

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Analog Fault Models
1. Catastrophic or Hard faults:

An analog component becomes open or shorted

Stuck at VDD
Stuck at VSS

2. Parametric or soft faults

An analog R, L, C, or transistor trans-conductance value changes sufficiently that

it moves outside its tolerance box and causes unacceptable performance
degradation of the analog circuit.

Single parametric faults are interesting in multi-chip module interconnects, as

they will be termination resistances or important components such as precision off-chip
inductors used in RF circuits.

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Analog Fault Models
Linear analog ICs are designed so that the analog performance depends on ratios of
components, so multiple parametric faults are most interesting in such chips. Checking

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Analog Fault Models
Linear analog ICs are designed so that the analog performance depends on ratios of
components, so multiple parametric faults are most interesting in such chips.

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Levels of Abstraction
For analog testing, the transistor level of abstraction provides detailed models and
structural interconnections for analog devices. At this level, the SPICE netlist, complete
with transistor models, provides a structural view. The system of non-linear partial
differential equations describing the netlist provides a behavioral view.

However, analog circuit testing can be done at a higher level of abstraction,

the functional level, in which we model resistors, capacitors, inductors, and ideal
OPAMPs, which have infinite gain and are considered to be fault-free. The benefits
of this higher level of abstraction are modeling convenience and computational efficiency,
and the liability is that OPAMPs may have faults, which should be tested for

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Types of Analog Testing
1. Specifications based Testing.

Each class of analog circuits has its own separate set of specifications. (Op amp, ADC, DAC,
Filters,)
There already exist accepted and specific functional tests for each class of analog circuits.
There is no universal set of performance specifications.
Also, there are no general design techniques for all analog circuits.
Analog circuit tests can be classified into these three categories:
• Design characterization, to determine whether the design meets specifications.
• Diagnostics, which determine the cause of a device failure when it fails a test.
• Production tests used for large volumes of linear or mixed-signal circuits.
Specification-based tests are generated directly from the circuit specifications, without
reference to an analog fault model. This approach is easily adapted to wide varieties of
circuits. However, with large numbers of specifications, test application has become most
expensive, and its cost must be reduced. The test set can be reduced by locating dependencies
between specifications and eliminating unnecessary testing.

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Types of Analog Testing
2. Structural fault-model based Testing

Structural fault-model based Testing will target a specific set of modeled faults. This
allows quantification of a set of analog tests in terms of their fault coverage, so test
sets can be graded. The models also reduce the test set size, since test waveforms that
detect faults already covered by other waveforms can be deleted. However, advocates
of structural tests have been unable to establish a link between the fault coverage and
satisfaction of the design specifications. This makes designers reluctant to accept
structural analog testing.

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Analog Fault Simulation
At present, no viable analog circuit synthesis tools exist, so analog design is
accomplished manually by experienced analog designers, who design circuits using
rules of thumb. For these designers, analog fault simulation is extremely useful for
what-if analysis, where the designer asks the question, “What would happen if
the resistance of resistor were out of specification by 3.5%?” Answering this question
requires analog fault simulation, which is far more computationally intensive than
ordinary analog circuit simulation. It is important to take advantage of the structure
of the circuit equations to concurrently simulate many analog faults.

• DC fault simulation of non-linear circuits

• AC fault simulation of linear circuits
• Transient or time-domain fault simulation.

We first apply DC tests to analog circuits, and only if the circuit passes these do
we apply AC tests, which are more difficult to generate and more costly to apply. Finally,
only if the circuit passes AC testing do we apply transient or time-domain tests.

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DC Fault Simulation

DC testing of analog circuits is attractive, because it requires less expensive

testers and less testing time. DC fault simulation is useful to analyze how well
a DC test can detect a given fault list. It is done by solving a set of non-linear
equations using PSPICE or similar analog simulators, which converge only after
many iterations. Simulation of catastrophic faults often fails to converge or causes
the system matrix to be singular. Several techniques reduce fault simulation CPU
time while improving convergence.

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DC Fault Simulation
Complementary Pivot Method
1. They model the circuit linearity by ideal diodes. B piecewise linear (PWL) I – V curve,
usually a 2 or 3-segment approximation to the diode I – V curve.

2. The transistor faults are modeled using switches, and these models are solved by an
operations research method call complementarity pivoting. This method does not have the
problem of Newton-Raphson iteration, which suffers from the extreme non-linearity coming
from analog circuit and fault modeling.

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Four Kind of simulations per device including fault free 13

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DC Fault Simulation
Newton-Raphson iteration solves equations iteratively, starting from an initial point and
iterating until the difference between and converges

For Solving f(x) =0 Start assuming initial solution as X0.

Iterate till error value within limits

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DC Fault Simulation
ONE-STEP RELAXATION VIA HOUSEHOLDER'S FORMULA

In one-step relaxation, the Newton-Raphson algorithm is operated for only one

step using the good circuit solution as the starting point.

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Fault Simulation

Legato Reliability Solution for Analog Defects

•Quickly identify potential sources of device manufacturing defects

•Multiple fault injection methods to optimize the simulation resolution and
performance
•Calculate the test program’s defect coverage based on simulation
•Choose the minimum set of tests to provide maximum fault coverage
•Supports different defect models (open, short, or bridge)
•Select defects based on criteria such as device type, parameter value, terminals,
etc.
•Correct-by-construction fault identification
•Defect detection based on the production test limits (range, >, etc.)
•Customizable measurement test based on preprocessing, calibration, etc.

11/5/2023 16

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Simulation

PrimeSim Custom Fault

Redefining Analog Fault Simulation for Functional Safety and Test Coverage
Analysis

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Simulation
Monte-Carlo Simulation
Monte-Carlo simulation has been extensively used in analog circuit and fault
simulation. We perform the simulation for randomly-generated small variations in
circuit component values. This is done because the actual IC manufacturing process
will cause good circuits to deviate by such values. However, Monte-Carlo simulation is computationally
expensive, unless the circuit is small with few statistical parameters.

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TPG Using Sensitivities
First-order sensitivity represents the relation between circuit elements and output parameters

We deduce component deviations by measuring various output parameters, and through

sensitivity analysis and tolerance computation. They identify tests for catastrophic
and soft (parametric) faults, for both single and multiple fault models. This ATPG
method is intended for production testing applications.

Differential sensitivity shows the effect of small variations in elements, and is defined as:

Incremental sensitivity shows the effect of large element variations, and is defined as:

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

TPG Using Sensitivities
Bipartite graph of this incremental
sensitivity matrix

Incremental sensitivity matrix

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

TPG Using Sensitivities
Test Method
1. Perform sensitivity analysis.

2. Build the circuit bipartite graph.

3. Compute tolerances (relative deviations) of every circuit element. The relative

deviation of fault-free elements comes from circuit data sheets. The tolerance
of a faulty element is computed as a (min, max) pair.

4. Construct the bipartite optimization graph.

5. Select parameters (or performances) to be measured during testing using the simplex
optimization method.

6. Perform testability analysis of the circuit by computing the analog fault coverage. For given
tolerance values, analog fault coverage is the ratio of detected faults over all possible faults.

7. Improve the circuit testability with design for testability (DFT) hardware. They add new
POs to increase observability of untestable elements.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

TPG Using Signal Flow Graphs
Ramadoss and Bushnell proposed structural analog circuit testing, where
they generate test waveforms that verify which component values or ratios of component
values are within specifications. This method shortens tester time per circuit,
by reducing the number of measurements.

SFG inversion can calculate the parameter tolerances that the circuit components must meet (during manufacturing), in
order to ensure that the analog output waveforms remain within specifications. This new method avoids specifying
analog components to tighter parametric tolerances than is necessary, and this reduces cost.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Analog Testing

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Analog Testing
Specification Oriented Test

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Analog Testing
Waveform Oriented Test
Compare waveform to the simulated ones

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

DSP-Based Mixed-Signal Test

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Scan-in/Scan-out
A chain of capacitors and voltage-follower buffers form an analog shift register.
• The test input signal can be scanned in from input pins to the internal nodes and
the test results can be scanned out from the internal nodes to output pins

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BIST for Analog Circuits
Oscillation-based test architecture.

A first well-known example is the generic oscillation test where the CUT is
reconfigured to oscillate by connecting it into a positive feedback loop, as shown in
Fig. The oscillation frequency and magnitude are information-rich signatures that
can be used to gain insight about the functionality of the CUT and to detect
abnormal behavior

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BIST for Analog Circuits
Oscillation-based test architecture.

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BIST for Analog Circuits
Loop-back test for RF transceivers.

A second example is the loop-back test for RF transceivers where the test signals
are generated in the baseband and the transmitter’s output is switched to the
receiver’s input through an attenuator to analyze the test response also in the
baseband

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

BIST for Analog Circuits
BIST employing an on-chip test stimulus generator and an on-chip test response
analyzer

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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal,–Kluwer Academic Publishers
(2000).

2. Video lectures by Professor James Chien-Mo Li

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Testability of VLSI

Lecture 14
Fault Tolerant VLSI Design

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Error Detection

1. Error needs to be detected first to rectify (tolerate) the error.

2. Even if the detected error is not rectified warning is to be generated, as a measure of

safety.

3. The key to error detection is redundancy. The three classes of redundancy

❑ Physical (sometimes referred to as “spatial”)
❑ Temporal, and
❑ Information

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Physical Redundancy
Dual Modular redundancy (DMR) with a comparator

Excellent error detection

All errors except for errors due to design bugs, errors in the comparator, and unlikely
combinations of simultaneous

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Physical Redundancy
Triple modular redundancy (TMR)

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Physical Redundancy
Triple modular redundancy (TMR)

Boeing 777’s triple TMR

[1] Fault Tolerant Computer Architecture by Daniel J Sorin

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Temporal Redundancy

Temporal redundancy requires a unit to perform an operation twice one after the other,
and then compare the results.

Total time is doubled unless pipe-lining structure

Unlike with physical redundancy, there is no extra hardware or power

cost (once again ignoring the comparator).

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Information Redundancy
Add redundant bits to a datum to detect when it has been affected by an error.
Odd or Even Parity Check

Single bit error detected Single bit error and

but double error is not double error is also
detected detected
7

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Information Redundancy
Classification of Code:
Example “Single-error correcting (SEC) and double-error detecting (DED)” SECDED : HD4
HD3: Can either correct single errors or detect single or double errors, but it cannot do both.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Information Redundancy

2r >= m+r+1
m is number of bits in original data
r is number of redundant bits to be added
n=m+r final number of bits in the coded data string

Example m = 4
r=1 : 2 >= 4 + 1 +1 22 21 20
r=2 : 4 >= 4 + 2 +1 m4 m3 m2 P3 m1 P2 P1
r=3 : 8 >= 4 + 3 +1

[1] Fault Tolerant Computer Architecture by Daniel J Sorin

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Information Redundancy
Example: 0011 (Even Parity) Even Parity
P1 : 0,1,1,0
7 6 5 4 3 2 1 P2 : 1,1,0,0
0 0 1 P3 1 P2 P1 P3 : 1,1,0,0
0 0 1 P3 1 P2 P1 Assuming an erroneous data
1 0 1 1 1 1 0
0 0 1 1 1 1 0

23 21 20 P1(20) P2(21) P3(23) Error Code (P3,P2,P1)

(1,1,1) -> 7
0 0 1 1
Assuming an erroneous data
0 1 0 2
0 0 1 1 1 1 1
0 1 1 3 3
1 0 0 4 Error Code (P3,P2,P1)
1 0 1 5 5 (0,0,1) -> 1

1 1 0 6 6 Example
1 1 1 7 7 7 Write and read from memory
10

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Error Detection in Microprocessor Cores
Functional Units

General Techniques. To detect errors in a functional unit, we could simply treat the unit
as a black box and use physical or temporal redundancy

Another general approach to functional unit error detection is to use arithmetic codes.

Example
A+ B=C
10A+ 10B= 10C, If we get 10C it is error free
Error causes the adder to produce a result that is not a multiple of 10

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Error Detection in Microprocessor Cores
Functional Units
Re-execution with Shifted Operands (RESO) : Adder
Input operands are shifted before the redundant computation.

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Error Detection in Microprocessor Cores
Functional Units
Multipliers
A B=C→[( A mod M)(B mod M)]mod M= C mod M.

With an appropriate choice of M, the modulus operation can be performed with little hardware

6 X 12 = 72
6 Mod5 X 12 Mod5 = 72 Mod5
1X2 =2

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Error Detection in Microprocessor Cores
Tightly Lockstepped Redundant Cores

Physical redundancy to replicate a core (DMR or TMR).

Results compared after every instruction or perhaps less frequently.
The frequency of comparison determines the maximum error detection latency

IBM System/390 is a discontinued mainframe

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Error Detection in Microprocessor Cores
Redundant Multithreading Without Lockstepping

Simultaneously multithreaded (SMT) cores such as the Intel Pentium 4 provided an

opportunity for low-cost redundancy. An SMT core with T thread contexts can execute T
software threads at the same time. If an SMT core has fewer than T useful threads to run, then
using otherwise idle thread contexts to run redundant threads provides cheap error detection.

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Error Detection in Microprocessor Cores
Dynamic Verifcation of Invariants
Rather than replicate a piece of hardware or a piece of software, another approach to error
detection is dynamic verification. At runtime, added hardware checks whether certain
invariants are being satisfied. These invariants are true for all error-free executions and thus
dynamically verifying them detects errors. The key to dynamic verification is identifying the
invariants to check.
Control Logic Checking: For a given instruction, some of the control signals are always the
same. To detect errors in these control signals, the authors add logic to compute a fixed-
length signature of these control signals, and the core compares this signature to a prestored
signature for that instruction.
Data Flow Checking:

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Error Detection in Microprocessor Cores

Watchdog Processors. Most of the invariant checkers we have discussed so far have been
tightly integrated into the core. A watchdog processor is a simple coprocessor that watches
the behavior of the main processor and detects violations of invariants. A typical watchdog
shares the memory bus with the main processor. The invariants checked by
the watchdog.

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Error Detection in Microprocessor Cores
Using Software to Detect Hardware Errors.
SWAT used mostly simple hardware checks with a little additional software

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Error Detection in Caches and Memory

In most computers, the levels of the memory hierarchy below the L1 caches, including
the L2 cache and memory, are protected with ECC. The L1 cache is either protected
with EDC as in the Pentium 4, UltraSPARC IV , and Power4 or with ECC (as in the AMD
K8 and Alpha 21264.

The choice of error codes represents an engineering tradeoff. Using EDC on an L1 cache,
instead of ECC, leads to a smaller and faster L1 cache. However, with only EDC on the L1,
the L1 must be write-through so that the L2 has a valid copy of the data if the L1 detects
an error. The writethrough L1 consumes more L2 bandwidth and power compared to a
write-back L1

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Error Detection in Caches and Memory

Detecting Errors in Addressing

Consider the case where a core accesses a memory with address B, and the memory
erroneously provides it with the correct data value at address C. Even with EDC, this error
will go undetected because the data value at address C is error-free.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Self-Repair
MULTIPROCESSORS
1. Core Replacement : Faulty Cores replaced with redundant core

2. Using scheduler to hide faulty functional units

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Self-Repair
MULTIPROCESSORS
3. Sharing resources across cores

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Fault Tolerant Adders

Design of Fault Tolerant Adders: A Review Ghashmi H. Bin Talib1 · Aiman H. El-Maleh1 · Sadiq M. Sait
23

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Fault Tolerant Adders

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Fault Tolerant Adders

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Fault Tolerant Adders

P. Kumar, R.K. Sharma / Engineering Science and Technology, an International Journal 19 (2016) 1465–1472

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Fault Tolerant Adders with Reversible Gates

Reversible Gates

When B is zero, the gate acts as a copying gate

or a buffer where both the output lines contain
the input A. When B is one, the complement of
A is obtained at the output Q.

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Fault Tolerant Adders with Reversible Gates

Design of Fault Tolerant Adders: A Review Ghashmi H. Bin Talib1 · Aiman H. El-Maleh1 · Sadiq M. Sait
Arabian Journal for Science and Engineering https://doi.org/10.1007/s13369-018-3556-9
28

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References

1. Fault Tolerant Computer Architecture by Daniel J Sorin

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Thankyou

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