Unit 5: Sequential Logic

Design
Prepared by, Dr S C Tamane
 UNIT V
• Sequential Logic Design:
– Introduction
– Registers
– Applications of Shift registers
– Ripple or asynchronous counters
– Synchronous counters
– Synchronous sequential circuits design
 Books
• Text Books:
1. R.P. Jain, “Modern Digital Electronics”, Tata McGraw Hill
Publication, 4th Edition, 2010.
2. M. M. Mano, “Digital Logic and Computer Design”,
Prentice Hall of India Publication, 4th Edition, 2006.

• Reference Books:
1. D. P. Leach, A. P. Malvino, G. Saha, “Digital Principles
and Applications”, Tata McGraw Hill Publication, 8th
Edition, 1993.
2. Comer, “Digital Logic & State Machine Design”, Oxford
 Introduction
• The FLIP-FLOP is a basic element of sequential
logic system. Using FLIP-FLOPs and
combinational logic circuits, any sequential
logic circuit can be designed.
• The most important sequential circuits that
are widely used in digital systems are
registers and counters.
 Registers
• A FLIP-FLOP can store 1 bit of digital information.
It is also referred to as a 1 bit register.
• An array of FLIP-FLOPs is required to store binary
information, the number of FLIP-FLOPs
required being equal to the number of bits in the
binary word and is referred to as a register.
• Registers find applications in a variety of digital
systems including microprocessors.
• For example, Intel's 8085 microprocessor chip
contains seven 8-bit registers and five 1-bit
registers, referred to as flags.
 Registers
• A data can be entered in serial (one-bit at a time) or in
parallel form (all the bits simultaneously) and can be
retrieved in the serial or parallel form.
• Data in serial form is also referred to as temporal code
and in parallel form as a special code.
• A 4-bit data 1010 in serial form is shown in fig. a and
parallel form in fig.b.
• For serial input/output, only one line is required for
data input and one line for data output, whereas the
number of lines required is equal to the number of bits
for parallel input/output.
Registers
 Registers
• Registers are classified depending upon the way in
which data are entered and retrieved.
• There are 4 possible modes of operation:
– Serial-in, serial-out (SISO)
– Serial-in, parallel-out (SIPO)
– Parallel-in, serial-out (PISO)
– Parallel-in, parallel-out (PIPO)
• Registers can be designed using discrete FLIP-FLOPs (S-
R or J-K as D-Type) and are also available as MSI
devices.
• The registers available in 54/74 TTL and CMOS logic
families are given in table.
Registers
 Shift Register
• Registers in which data are entered or/and taken out in
serial form are referred as shift registers, since bits are
shifted in the FLIP-FLOPs with the occurrence of clock
pulses either in the right direction (right-shift
register) or in the left direction (left-shift register).
• In the bi-directional shift register, data can be shifted
from left to right as well as in the reverse direction,
using the mode control.
• A register is referred to as a universal register if it can
be operated in all the four possible modes also as a bi-
directional register.
 Shift Register
• A 5-bit shift register using 5 master slave S-R
(or J-K) FLIP-FLOPs is shown in fig.
• This circuit can be used in any of the four
modes.
• Ex. 10110, for any other 5-bit data the
operation will be similar as earlier.
Shift Register
 Serial Input
• Serial Input:
• The data word in the serial form (fig 8.1 a) is
applied at the serial input after clearing the
FLIP-FLOPs using the clear line.
• The preset enable is to be held at 0 so that Pr
for every FLIP-FLOP is 1.
• The input and output waveforms are
illustrated in the fig 8.3.
Serial Input
Serial Input
Serial Input
Serial Input
Serial Input
Serial Input
Serial Input
Serial Input
 Serial Input
• The process of entering the digital word starts with the data input
corresponding to the LSB (0) at the serial input and first clock pulse.
• At the falling edge (T1) of the first clock pulse the output of FF4(Q4) will be
0 and the outputs of all other FLIP-FLOPs are 0 since their inputs are 0.
• The input corresponding to the next bit is applies and the falling edge (T2)
of the second clock pulse, the FLIP-FLOP outputs will be
• Q4=1
• Q3=Q2=Q1=Q0=0
• Similarly, the input corresponding to each bit is applied till the MSB and
the bits go on shifting from left to right at the falling edge of each clock
pulse a s illustrated in fig. . at the end of the fifth clock pulse, the output of
FLIP-FLOPs are
• Q3=0, Q2=1, Q1=1, Q0=0
• Which is the same as the number to be stored. The process of entering the
data is also referred to as writing into the register.
 Serial Input
• The data stored can be retrieved in two ways: serial-out and
parallel-out. The data in the serial form is obtained at Q 0 when clock
pulses required will be same as the number of bits (5 in this case).
• In the parallel form, the data is available at Q 4Q3Q2Q1Q0 and clock is
not required for reading.
• In the case of serial output, after the nth clock pulse, for an n bit
word, each FLIP-FLOP output is 0. this means that once the data is
retrieved the register is empty.
• On the other hand, in the case of parallel output, the contents of
the register can be read any number of times until new data is
stored in the register.
• The clock rate may be different for the input data and the output
data in case of a serial-in, serial-out shift register. Hence this
method can be used for changing the spacing in time of a binary
code which is referred to as buffering.
 Parallel Input
• Data can be entered in parallel form making use of the preset
inputs.
• After clearing the FLIP-FLOPs, if the data line are connected to
the parallel inputs (Di4, Di3, Di2, Di1, and Di0) and a 1 applied at
the preset input, the data are written into the register. This is
referred to as asynchronous loading.
• The stored word may be read in the serial form at Q0 by
applying five clock pulses or in the parallel form at Q outputs.
• The data also be entered in parallel form by using D Type FLIP-
FLOPs connected.
• In this, the data is loaded when a clock pulse is applied and
hence, it is referred to as synchronous loading.
 Bi-directional Register
• There are applications in which shifting data to the right
and/or to the left is required.
• For example, a binary number can be divided by two by
shifting it one stage to the right.
• In this process the LSB is lost causing an error of 0.5 if the
number is odd.
• Similarly, a number stored in a shift register can be multiplied
by divided by two by shifting it one stage to the left, provided
a 1 is not shifted out of the most significant stage.
• A 4-bit bidirectional shift register is shown in the fig.
Bi-directional Register
 Bi-directional Register
• When the mode control M=1, all the A AND gates are enabled
and the data at DR is shifted to the right when clock pulses are
applied.
• On the other hand, when M=0, the A gates are inhibited, and
B gates are enabled allowing the data at DL to be shifted to
the left. M should be changed only when CK=0, otherwise the
data stored in the register may be altered.
 Applications of Shift Registers
• Serial to parallel converter
• Parallel to serial converter
• Ring counter
• Twisted ring counter
• Sequence generator
 Applications of Shift Registers
• Introduction to Shift Registers, what is shift register? Types of shift
registers.
– https://www.youtube.com/watch?v=bAQfPQqKCHs
• Shift register: Serial in serial out register (right-left)
– https://www.youtube.com/watch?v=r4bfEqZNSyo
– https://www.youtube.com/watch?v=unorn9n-UpE
• Shift register: Serial in parallel out register, PIPO, PISO
– https://www.youtube.com/watch?v=JbtqyvLu67c
– https://www.youtube.com/watch?v=HGFGQ3D3iJ8
– https://www.youtube.com/watch?v=7LmBcGiiYwk
• Bidirectional Shift register
– https://www.youtube.com/watch?v=zoEeQgQkPLA
• Universal Shift register
– https://www.youtube.com/watch?v=AEGzpMlOsvc
 Applications of Shift Registers
• Practice Problems
– https://www.youtube.com/watch?v=bMHJ1qldiaE
– https://www.youtube.com/watch?v=XXmW7nY4EjY
• Counter
– https://www.youtube.com/watch?v=iaIu5SYmWVM
• Ring Counter
– https://www.youtube.com/watch?v=yOW-JsJL1Ks
• Twisted Ring Counter
– https://www.youtube.com/watch?v=X4mx7J1ckyU
• Sequence Generator
– https://www.youtube.com/watch?v=WG_J96id57A
 Asynchronous Counters
• Ripple Or Asynchronous Counters
– https://www.youtube.com/watch?v=s1DSZEaCX_g
• Modulus of the counter
– https://www.youtube.com/watch?v=l20xHDJPHBM
• 3 bit & 4 bit Asynchronous Down Counter
– https://www.youtube.com/watch?v=noUcCs2zNaI
• 3 bit Asynchronous Up Counter
– https://www.youtube.com/watch?v=s1DSZEaCX_g
• Synchronous Counters
– https://www.youtube.com/watch?v=5vkWccb7uO4
 Synchronous Sequential Circuits
Models
• The block diagram of the sequential circuit is shown in following fig. 7.1
• It consists of combinational circuits which
– accept digital signals from external inputs
– from outputs of memory elements
– generates signals for external outputs and for inputs to memory elements
referenced to a excitation.

Exci tation
Next State Memory Output
Logic Elements Logic
External
Inputs External
Outputs
Clock
 Synchronous Sequential Circuits
Models
• Depending upon the way the external outputs are
obtained from the circuit, there are two different
models of sequential circuits.
• These are Mealy model and Moore model.

Exci tation
Next State Memory Output
Logic Elements Logic
External
Inputs External
Outputs
Clock
 Mealy Model
• In Mealy model, the next state is a function of the present state and the present
inputs.
• Its output is also a function of the present state and the present inputs.
• Fig. 7.1 represents Mealy Model.
• The next state and the output of a Mealy model are uniquely defined by:
Next State = F1 (Present State, Inputs)
Outputs = F2 (Present State, Inputs)

Exci tation
Next State Memory Output
Logic Elements Logic
External
Inputs External
Outputs
Clock
 Moore Model
• Moore model is shown in fig. 8.38.
• The next state is a function of the present state and the present inputs.
• Its output is a function of only present state and are independent of
inputs.
• The Moore model is defined as:
Next State = F1 (Present State, Inputs)
Outputs = F2 (Present State)
 State Diagram
• It is a directed graph, consisting of vertices (or nodes) and directed
arcs between the nodes.
• Every state of the circuit is represented by a node in the graph.
• A node is represented by a circle with the name of the state written
inside the circle.
• The directed arcs represent the state transitions.
• With the circuit in any one state, at the occurrence of a clock pulse,
there will be a state transition to the next state and there will be an
output, both in accordance with the requirements of the circuit.
• This state transition is represented by a directed line emanating
from the node corresponding to the present state and terminating
on the node corresponding to the next state.
• The labels are put on the directed arcs specifying the inputs and
outputs separated by a slash (/).
 State Diagram
• Consider a portion of a state diagram shown in the fig.
8.40a.
• When the circuit is in state A, an input 1 causes the
circuit to make a transition to the next state B and
gives an output 0.
• A and B represent the present state and next state
resp., connected by an arc from A to B labelled (1/0).
 State Diagram
• For a circuit with single input, when the circuit is in any
state, the input can be 0 or 1.
• For each possibility of the input, there will be a directed
arc.
• Thus two arcs emanate from each node, one each for a 0
and for a 1 input.
• For an n input machine, 2n arcs will emanate from each
node. This is shown in fig 8.40b.
• In some sequential circuits, the
outputs are taken from the
outputs of the Flip-flops directly.
• The directed arcs will have only
inputs written adjacent to the
arcs.
 State Diagram
• In some cases a state may be a terminal state: a sink vertex
or a source vertex.
• A vertex is known as sink vertex if there are no outgoing
arcs which emanate from it and terminate in other vertices.
Fig.a. Vertex D
• A vertex is known as source vertex if there are no arcs
which emanate from other vertices terminating in it. Fig.b.
Vertex A.
Example 8.16 Draw the state diagram of a D type Flip Flop shown
in the fig. 8.42.

•Input: D
•States: Q=0 and Q=1
•Clock: CK

•2 states: 2 nodes
•If current state 0, D=0, after the
clock pulse Output: State 0 (self arc
at node 0)
•If current state 0, D=1, after the
clock pulse Output: State 1 (arc from
0 to 1)
•If current state 1, D=0, after the
clock pulse Output: State 0 (arc from
1 to 0)
• If current state 1, D=1, after the
clock pulse Output: State 1 (self arc
at node 1)
Example 8.17 Draw the state diagram of a J-K Flip Flop.

•Input: J and K

•States: Q=0 and Q=1

•Clock: CK

•There are two inputs (J and K),

therefore, there are 22=4 possible
input conditions.
•So, four directed arcs emanate from
each state.
 State Table
• It is a tabular form of describing the operation of
a synchronous circuit.
• Row: state of the circuit
– No. of rows: no. of states of the circuit
• Column: combination of external inputs
– No. of columns: no. of combinations of inputs (2 for 1
input, 4 for 2 inputs, so on)
• Entries: the state transitions (next state) and the
output associated with these transitions
• It can be easily constructed from a state diagram
Example 8.18 Construct state table for the state diagram of
following fig.

•3 States: A, B, C, so state table

contains 3 rows
•Input: X, (one column for each value
of X=0, X=1)
•Output: Y
•Each entry: next state, output

•Ex. When the circuit is in state A

•External Input: 0, after a clock Present State
Next State, Output
pulse, state A is still 0: First row First NS, Y
Column PS X=0 X=1
•External Input: 1, after a clock A A, 0 B, 0
pulse, state B and output is 0: First B C, 1 A, 0
row Second Column C A, 0 C, 1
•….
•….
State Table
 State Equivalence and Minimization
• Two states are said to be equivalent if, for
each input condition, they give exactly the
same output and go to the same next state.
• When two states are found to be equivalent,
one of them is eliminated without altering the
input-output relations.
• This process is referred to as state reduction.
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

State Table
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b d c 0 0
c g d 1 1
Find equivalent states
d e f 1 0
e f a 0 1
f g f 1 0
g f a 0 1
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

State Table
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b d c 0 0
c g d 1 1
d e f 1 0
e f a 0 1
f g f 1 0
g f a 0 1  eliminate row g
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

State Table
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b d c 0 0
c g d 1 1  Replace g by e
d e f 1 0
e f a 0 1
f g f 1 0  Replace g by e
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

State Table
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b d c 0 0
c e d 1 1
Find equivalent states
d e f 1 0
e f a 0 1
f e f 1 0
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

State Table
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b d c 0 0
c e d 1 1
d e f 1 0  Remove row d
e f a 0 1
f e f 1 0
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

State Table
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b d c 0 0
c e d 1 1  Replace d with f
e f a 0 1
f e f 1 0
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

State Table
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b f c 0 0
c e f 1 1
e f a 0 1
f e f 1 0
Example 8.22 For the state table 8.17, obtain reduced state table
with minimum number of states.

Present Next state Output

state X=0 X=1 X=0 X=1
a c b 0 0
Effect of eliminating
b (d)f c 0 0 equivalent states
c (g)e (d)f 1 1
d e f 1 0
e f a 0 1
f (g)e f 1 0
g f a 0 1

Present Next state Output

state X=0 X=1 X=0 X=1 Reduced state table
a c b 0 0
b f c 0 0
c e f 1 1
e f a 0 1
f e f 1 0
Example 8.23 Design a minimal clocked sequential circuit for the
reduced state table in above problem.
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
Reduced state table
b f c 0 0
c e f 1 1
e f a 0 1
f e f 1 0
Solution:
• The reduced state table was obtained, using state equivalence and
minimization concepts.
• Next step: to assign binary values to the states
• 5 states: no. of FLIP FLOPs required = 3: FF2, FF1, FF0,
• Outputs of FFs: Q2, Q1, Q0 resp.
• Therefore every state will be a 3 bit number with Q2: MSB and Q0: LSB.
• Assume D FLIP FLOPs.
• From application of the rules of state assignment, we find that
• The next states are same for the states c and f for X=0 and X=1,
therefore, the states c and f should be assigned adjacent codes.
• From the states b and e, the next state is f for X=0, therefore, the states
b and e should be assigned adjacent codes.
• State assignment map can then be constructed.
• Assume that a=000 as the initial state.
• The assignment map is shown in fig. 8.50.
• The states assigned are:
a=000, b=011, c=010
e=111, f=110
a=000, b=011, c=010 Present Next state Output
e=111, f=110 state X=0 X=1 X=0 X=1
• The state transition and a c b 0 0
output table is b f c 0 0
constructed next. c e f 1 1
• From the state a (000)
e f a 0 1
the next state is c=010,
f e f 1 0
when X=0, output is
Y=0. See table.
Example 8.24 For the reduced state table given below, design the circuit
assuming the state assignment given below: compare the hardware
requirement of this state assignment with the state assignment done in
example 8.23.
a=000, b=001, c=010, e=011, f=100

Present Next state Output

state X=0 X=1 X=0 X=1
a c b 0 0
b f c 0 0
c e f 1 1
e f a 0 1
f e f 1 0
 a=000, b=001, c=010, e=011, f=100
Present Next state Output
state X=0 X=1 X=0 X=1
a c b 0 0
b f c 0 0
c e f 1 1
e f a 0 1
f e f 1 0