Unit 2.

Combinational
Logic Design
Prepared by, Dr Sharvari C Tamane
UNIT II
 Combinational Logic Design:
 Introduction,
 Standard Representation of Logic functions,
 Karnaugh Map Representation of Logic functions,
 Simplification of Logic functions using K Map,
 Minimization of logic functions,
 Don’t-care Conditions,
 Design Examples,
 Five and Six Variable K Maps,
 Quine – McClusky Minimization Technique
Books
 Text Books:
1. R.P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Publication, 4th Edition, 2010.
2. M. M. Mano, “Digital Logic and Computer Design”, Prentice Hall of India Publication, 4 th
Edition, 2006.

 Reference Books:
1. D. P. Leach, A. P. Malvino, G. Saha, “Digital Principles and Applications”, Tata McGraw Hill
Publication, 8th Edition, 1993.
2. Comer, “Digital Logic & State Machine Design”, Oxford Universities Press, 3rd Edition, 2014

 E-Sources:
 NPTEL videos
Boolean Algebra
• An English Mathematician George Boole developed rules for
manipulations of binary variables, known as Boolean Algebra.
• Binary variables: A, B, X, Y,…….
• The variable can have values as: 0 or 1
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
Boolean Algebraic Theorems
• Theorems 1.1 to 1.8 involve a single variable only.
• Each of these theorems can be proved by considering every possible
value of the variable.
• For ex.
• If A=0 then 0+0=A
• If A=1 then 1+0=1=A
• Theorems 1.9 to 1.20 involve more than one variable and can be
proved by making truth table.
• For ex.
• Theorem 1.10 can be proved by making the truth table given in the following
table:
Boolean Algebraic Theorems
Boolean Algebraic Theorems
• Theorems 1.21 and 1.22 are known as De Morgan’s theorems.
Boolean Algebraic Theorems
• The NAND operation of three variables:

• The NOR operation of three variables gives:

Boolean Algebraic Theorems
• The above result can be easily extended to any number of variables.
• A logic problem can be specified in terms of a set of statements.
• This set of statements can be represented in terms of an equation
called the logic equation or in terms of a truth table.
• A digital circuit using the gates can be designed to realize a logic
equation.
• It is possible to simplify (minimize) a logic equation.
• This will need less number of gates and/or less number of inputs for
the gates.
Combinational Logic Design
• Introduction:
• Digital circuits are divided into two broad categories:
• Combinational circuits
• Sequential circuits
• In Combinational circuits, the outputs at any instant of time depend
upon the inputs present at that instant of time.
• In sequential circuits, the outputs at any instant of time depend
upon the present inputs as well as past inputs/outputs.
• There are elements used to store past information. Memory.
Combinational Logic Design
• The design requirements of Combinational circuits may be specified
in one of the following ways:
• A set of statements
• Boolean expression
• Truth table
• The following methods can be used to simplify the Boolean
functions:
• Algebraic method
• Karnaugh-map technique
• Quine-McClusky method
• Variable entered mapping technique
Standard Representations for Logic Functions
• Logic functions are expressed in terms of logical variables.
• The values assumed by the logic functions as well as the logic variables
are in the binary form.
• Any arbitrary logic function can be expressed in the following forms:
• Sum-of-Products form (SOP)
• Product-of-Sums form (POS)
• These methods are used for designing the circuits.
Standard Representations for Logic Functions
Standard Representations for Logic Functions
Standard Representations for Logic Functions
Standard Representations for Logic Functions
Standard Representations for Logic Functions
Logic Functions
• Solution:
• In equation 5.1, there are 3 input logic variables A,B and C, and Y is the output.
• The variable C appears as C in one term and as C bar in the other term.
• A variable in uncomplemented or complemented form is known as a literal.
• A circuit using gates can simply be designed by looking at the expression and finding out
the basic gates which can be used to realize the various terms and then connect these
gates appropriately.
• The first term (A) has only one literal and the second term (BC) has two literals B and C.
• The second term is recognized as an AND operation and can be realized by using 2-input
AND gate.
• The combination of these two terms is realized by using a 2-input OR gate.
• The complete realization of first two terms is shown in the fig a (next slide).
a) Design a
circuit using
gates to
realize this
function
Logic Functions
• Solution:
• The third term (B) is again literal term and the fourth term C bar A has two
literals.
• The combination of these two terms is similar to the combination of the first two
terms and is realized in a similar way.
• This realization is shown in figure b.
• Now, the complete realization is obtained by using a 2 input AND gate with Y1
and Y2 as the inputs and the output of this gate will be required output Y.
• This realization is given in figure c.
• This design requires three 2-nput AND gates and two 2 input OR gates.
a) Design a
circuit using
gates to
realize this
function
Logic Functions
• Solution:
• Now, the complete realization is obtained by using a 2 input AND gate with Y1
and Y2 as the inputs and the output of this gate will be required output Y.
• This realization is given in figure c.
• This design requires three 2-nput AND gates and two 2 input OR gates.
a) Design a
circuit using
gates to
realize this
function
• The representation of eq. 5.3 is known as SOP form.
• This can be realized using AND-OR configuration as shown in fig (on next
slide).
• This realization is known as two level realization.
• The first level consists of AND Gates and the second level consist of OR gate.
Y
• By De-morgan’s theorem, equation 5.3 can be written as:

or
where
• By De-morgan’s theorem, equation 5.3 can be written as:

or
where
• By De-morgan’s theorem, equation 5.3 can be written as:

or
where
• By De-morgan’s theorem, equation 5.3 can be written as:

or
where
• By De-morgan’s theorem, equation 5.3 can be written as:

or
where
• By De-morgan’s theorem, equation 5.3 can be written as:

or
where
• By De-morgan’s theorem, equation 5.3 can be written as:

or
where

• The above equation can be realized using NAND gates.

• This is shown in fig. 5.2 b (on next slide)
• This is also a two level realization and in this only NAND gates are used.
• So if we express the equation in the SOP form we can design the circuit
using only one type of Gates (NAND).
Y
Y
a) b) d)
3 – 2 i/p 3 – 2 i/p AND 3 – 2 i/p OR 3 – 2 i/p
AND 1 – 3 i/p OR 1 – 3 i/p AND NAND

2 – 2 i/p 3 – 2 i/p NAND 3 – 2 i/p NOR 3 – 2 i/p

OR 1 – 3 i/p NAND 1 – 3 i/p NOR NOR
Standard Representations for Logic Functions

• In the SOP form and POS form of above equations, all the individual
terms do not involve all the three literals.
• If each term in SOP and POS forms contain all the three literals then these
are known as canonical SOP and POS resp.
• Each individual term in canonical SOP form is called as minterm and in
canonical POS form as maxterm.
• SOP form can be converted to canonical SOP by ANDing the terms in the
expression with terms formed by ORing the variable and its complement
which are not present in that term.
• POS form can be converted to canonical POS by ORing the terms in the
expression with terms formed by ANDing the variable and its
complement which are not present in that term.
•Table gives the
minterms and
maxterms for a
4 variable
logical function
where the
number of
minterms as
well as
maxterms is 24 =
16.
•In general, for
an n variable
logical function
there are 2n
minterms and
maxterms.
Standard Representations for Logic Functions
• Each minterm is represented by mi where the i is the decimal
equivalent of the natural binary number corresponding to minterm
with normal variables taken as 1’s and the complemented variables
taken as 0’s
• Similar to minterms, each maxterm is represented by Mi where i is
the decimal equivalent of the natural binary number corresponding
to maxterm with un-complemented variables taken as 0’s and the
complemented variables taken as 1’s
 Standard Representations for Logic Functions
• Using these notations following • Following POS can be written as:
SOP can be written as:
Karnaugh Map Representation of Logic Functions
• In an n-variable K map there are 2n cells.
• Each cells corresponds to one of the combinations of n variables
• For each row of the truth table, for each minterm and for each maxterm
there is one specific cell in the K-map.
• Variables: A, B, C, D
• Binary numbers formed are taken as: AB, ABC, ABCD for 2, 3, 4 variables
resp.
• In each map the variables and all possible values of the variables are
indicated (the first bit corresponds to the first variable and the second bit
corresponds to the second variable) to identify the cells
• Gray code has been used for the identification of cells.
Karnaugh Map Representation of Logic Functions
• Following figure shows the minterm/maxterm corresponding to each cell
and the term is written inside the cell for clear understanding:
Karnaugh Map Representation of Logic Functions
• Following figure shows the minterm/maxterm corresponding to each cell
and the term is written inside the cell for clear understanding:
Karnaugh Map Representation of Logic Functions
• Following figure shows the minterm/maxterm corresponding to each cell
and the term is written inside the cell for clear understanding:
(d)

(e)

(f)
(d)

(e)

(f)
(d)

(e)

(f)
2 Variables K Map A
B 0 1
0 0 2
1 1 3

AB 00 01 11 10
3 Variables K Map C
0 0 2 6 4
1 1 3 7 5

AB
CD 00 01 11 10
4 Variables K Map
00 0 4 12 8
01 1 5 13 9
11 3 7 15 11
10 2 6 14 10
 Representation of Truth Table on K-Map
• Consider the following truth table of 3 variable logic function:
• The output Y is logic 1 corresponding to the rows
Inputs Output 1,2,4,7
Row No. • Corresponding to this the equation in terms of
A B C Y
canonical SOP is:
0 0 0 0 0
1 0 0 1 1
• Above equation represents the complete truth table in
2 0 1 0 1 canonical SOP form
3 0 1 1 0 • The output Y is logic 0 corresponding to the rows 0,3,5,6
4 1 0 0 1 • Corresponding to this the equation in terms of
5 1 0 1 0 canonical POS is:
6 1 1 0 0
7 1 1 1 1 • Above equation also represents the complete truth
table in canonical POS form
 Representation of Truth Table on K-Map

Inputs Output
• This can be represented in 3 variable K-map as
Row No. follows:
A B C Y
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1
Example 5.4: Prepare the truth table for K-map of
following figure:
Solution: 0’s are not written in the K-map. Inputs Output
Row No.
We need to enter either 0’s or 1’s only in the K-map A B C D Y
If only 1’s are entered the empty cells are 0’s and 0 0 0 0 0 1
vice versa. 1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1
Representation of Canonical SOP Form on K-map

• Example 5.6: Write the logic equation in the

canonical SOP form for the K-map shown:
Representation of Canonical POS Form on K-map

• Example 5.8: Write the logic equation in the

canonical POS form for the K-map shown:
Representation of Canonical POS Form on K-map

• Example 5.8: Write the logic equation in the

canonical POS form for the K-map shown:
Simplification of Logic Functions Using K-Map
• Simplification of logic functions with K-map is based on
the principle of combining terms in adjacent cells.
• 2 cells are said to be adjacent if they differ in only one
variable.
• Ex. In the 2 variable K-maps, the top two cells are
adjacent and the bottom two cells are adjacent.
• Also the left two cells and the right two cells are
adjacent.
• In adjacent cells one of the literals is same where as the
other literal appears in uncomplemented form in one
and in the complemented form in the other cell.
Simplification of Logic Functions Using K-Map
• Adjacent cells in the 3 variable and 4 variable K-maps are given in
following table:
Simplification of Logic Functions Using K-Map
• Adjacent cells in the 3 variable and 4 variable K-maps are given in
following table:
Simplification of Logic Functions Using K-Map
• The simplification of logical function is achieved by grouping
adjacent 1’s or 0’s in groups of 2 i, where i= 1,2,….n
• Where n number of variables
• The process of simplification involves grouping of minterms and
identifying prime implicants (PI) and essential prime implicants (EPI)
• A prime implicant is a group of minterms that cannot be combined
with any other minterm or groups
• An essential prime implicant is a prime implicant in which one or
more minterms are unique i.e. it contains at least one minterm
which is not contained in any other prime implicant
Grouping Two Adjacent Ones
• If there are two adjacent
ones on the map, these
can be grouped together
and the resulting term will
have one less literal than
the original two terms
• It can be verified for each
of the groupings of two
ones as given in the
following table:
Example 5.9: Simplify the K-map of figure 5.9.
Example 5.9: Simplify the K-map of figure 5.9.
Example 5.9: Simplify the K-map of figure 5.9.
Example 5.9: Simplify the K-map of figure 5.9.
Example 5.9: Simplify the K-map of figure 5.9.

Above equation can be easily obtained from the k-map by using the following procedure:
Step1:
a. Identify adjacent ones, then see the values of the variables associated with these cells
b. Only one variable will be different and it gets eliminated
c. Other variables will appear in ANDed form in the term
d. It will be in the un-complemented form if it is 1 and in the complemented form if it is 0.
Step2:
a. Determine the term corresponding to each group of adjacent ones. These terms are ORed to get
the simplified equation in SOP form.
 Grouping Four Adjacent Ones
• Four cells form a group of four adjacent ones if two of the literals associated with
the minterms/maxterms are not same and the other literals are same.
• Following table gives all possible groups of 4 adjacent ones for each cell in a 3
variable map.
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
In the k-map of above figure, there are two groups of 4 adjacent ones.
One corresponding to cells 0,1,8,9 and the other ones corresponding to 3,7,15,11
The minterms corresponding to each group are combined
The first term can be written as:
Grouping Eight Adjacent Ones
• Eight cells form a group of eight adjacent ones if
three of the literals associated with the
minterms/maxterms are not same and the other
literals are same.
• 3 variable K-map: 1 possibility where output=1
• Following table gives all possible groups of eight
adjacent ones in a 4 variable k-map.
• When 8 adjacent ones are combined the resulting
equation will have only one term with the number
of literals 3 less than the number of literals in the
original minterms.
Grouping Eight Adjacent Ones
Grouping 2, 4 and 8 Adjacent Zeros
• Instead of making the groups of ones, we can also make groups of zeros. The
procedure for this is as follows:
1. Group of two adjacent zeros result in a term with one literal less than the
number of variables. The literal which is not same in the two maxterms
gets eliminated.
2. Group of four adjacent zeros result in a term with two literals less than the
number of variables. The two literals which are not same in all the four
maxterms gets eliminated.
3. Group of eight adjacent zeros result in a term with three literals less than
the number of variables. The three literals which are not same in all the
eight maxterms gets eliminated.
• We have considered groups of 2, 4 and 8 adjacent ones and zeros. The same
logic can be extended to 16, 32 and 64 adjacent ones and zeros which occur in
K-maps with more than 4 variables.
 AB
CD 01 11 10
00
0 4 12 8
00 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD
00 01 11 10
0 4 12 8
00

1 5 13 9
01

3 7 15 11

11

2 6 14 10
10
 AB
CD
00 01 11 10
0 4 12 8
00 1 1 1

1 5 13 9
01 1 1 1

3 7 15 11

11 1 1 1

2 6 14 10
10 1 1
 AB
CD
00 01 11 10
0 4 12 8
00 1 1 1

1 5 13 9
01 1 1 1

3 7 15 11

11 1 1 1

2 6 14 10
10 1 1
 AB
CD
00 01 11 10
0 4 12 8
00 1 1 1

1 5 13 9
01 1 1 1

3 7 15 11

11 1 1 1

2 6 14 10
10 1 1
 ABCD
0011
0111
AB
CD
00 01 11 10 1000
0 4 12 8
1 1 1
1001
00
1100
1 5 13 9 1101
01 1 1 1
0000
3 7 15 11
1 1 1
0001
11
0010
2 6 14 10 0011
10 1 1 1000
1001
1010
1011
Minimization of Logic Functions not specified
in Minterms/Maxterms
• If the function is specified in one of the two canonical forms, its K-map can
be prepared and the function can be minimised.
• But if the functions are not specified in canonical forms then the equations
can be converted into canonical forms using some techniques. For ex.
• Enter ones for minterms and zeros for maxterms.
• Enter a pair of ones/zeros for each of the terms with one variable less than the total
number of variables.
• Enter four adjacent ones/zeros for terms with two variables less than the total
number of variables.
• Repeat for other terms in the similar way.
• Once the K map is prepared the minimisation procedure is same as seen
earlier.
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01

3 7 15 11
11

2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
1
3 7 15 11
11

2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
1
3 7 15 11
11

2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
1
3 7 15 11
11
1
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
1
3 7 15 11
11
1
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00
1
1 5 13 9
01
1 1
3 7 15 11
11
1
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00
1
1 5 13 9
01
1 1
3 7 15 11
11
1
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00
1
1 5 13 9
01
1 1
3 7 15 11
11
1
2 6 14 10
10 1
 AB
CD 01 11 10
00
0 4 12 8
00
1
1 5 13 9
01
1 1
3 7 15 11
11
1
2 6 14 10
10 1
 AB
CD 01 11 10
00
0 4 12 8
00
1
1 5 13 9
01
1 1
3 7 15 11
11
1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00
1
1 5 13 9
01
1 1
3 7 15 11
11
1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00
1 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00
1 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00
1 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00
1 1 1
1 5 13 9
01
1 1 1
3 7 15 11
11
1 1 1
2 6 14 10
10 1 1
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01

3 7 15 11
11

2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01

3 7 15 11
11
0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01

3 7 15 11
11
0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
0 0
3 7 15 11
11
0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
0 0
3 7 15 11
11
0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
0 0
3 7 15 11
11
0 0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00

1 5 13 9
01
0 0
3 7 15 11
11
0 0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00
0 0
1 5 13 9
01
0 0 0
3 7 15 11
11
0 0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00
0 0
1 5 13 9
01
0 0 0
3 7 15 11
11
0 0
2 6 14 10
10
 AB
CD 01 11 10
00
0 4 12 8
00
0 0
1 5 13 9
01
0 0 0
3 7 15 11
11
0 0 0 0
2 6 14 10
10 0 0
 AB
CD 01 11 10
00
0 4 12 8
00
0 0
1 5 13 9
01
0 0 0
3 7 15 11
11
0 0 0 0
2 6 14 10
10 0 0
 AB
CD 01 11 10
00
0 4 12 8
00
0 0
1 5 13 9
01
0 0 0
3 7 15 11
11
0 0 0 0
2 6 14 10
10 0 0
• We enter 1’s and 0’s in the map corresponding to input variables that
make the function equal to 1 or 0 resp.
• The maps are simplified using either 1’s or 0’s.
• Therefore, we make the entries in the map for either 1’s or 0’s.
• The cells which do not contain 1 are assumed to contain 0 and vice
versa.
• This is not always true since there are cases in which certain
combinations of input variables do not occur.
• Also for some functions the outputs corresponding to certain
combinations of input variables do not matter.
• In such cases the designer has a flexibility and it is left to him whether
to assume a 0 or 1 as output for each of these combinations.
• This condition is known as don’t-care condition and can be
represented on the K-map as a X mark in the corresponding cell.
• The X mark in a cell may be assumed to be a 1 or a 0 depending upon
which one leads to a simple expression.
(A+
 Five and Six Variable K-Maps
• A five variable K-
map is shown in
the fig.
• Consider the two
four variable maps
superimposed on
one another.
• The adjacencies
between the four
variable maps are
visualized as
groupings in a two
variable map.
 Five and Six Variable K-Maps

• A six variable K-map is

shown below:
• A six variable k-map has 4
four variables maps.
Design Examples
• Arithmetic Circuits:
• Half Adder: A logic circuit for the addition of two one bit numbers is referred to as an half adder.
• Inputs: A and B
• Outputs: S sum, C Carry The logical expression for S and C outputs is as
follows: _ _
• Truth Table for Half Adder: S = AB + AB = A  B
C = AB
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Design Examples
• Arithmetic Circuits:
• Full Adder: An half adder has only 2 inputs and there is no provision to add a carry.
• The third input terminal is added to add An, Bn, Cn-1 where, An and Bn are the nth order bits of the
numbers A and B resp. and Cn-1 is the carry generated from the addition of (n-1)th order bits.
• This circuit is referred as Full Adder
• Truth Table for Full Adder:
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Design Examples
• Arithmetic Circuits:
• Half Subtractor: A logic circuit for the subtraction of B (subtrahend) from A (minuend) where A and B are
1-bit numbers is referred to as a half subtractor.
• Inputs: A and B
The logical expression for D and C outputs is as
• Outputs: D Difference, C Borrow
follows: _ _
• Truth Table for Half Subtractor: D = AB + AB = A  B
_
Inputs Outputs C = AB
A B D C
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Design Examples
• Arithmetic Circuits:
• Full Subtractor: This needs full subtractor circuit for performing multibit subtraction wherein a
borrow from the previous bit position may also be there.
• Inputs: An, Bn, Cn-1. Outputs: Dn, Cn
• Truth Table for Full Subtractor:
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Quine-McCluskey Minimization Technique
• A logic minimization technique has the following characteristics:
• It should have the capability of handling large number of variables
• It should not depend on the ability of a human user for recognizing prime implicants
• It should ensure minimized expression
• It should be suitable for computer solution
• The Quine Mc-Cluskey minimization technique satisfies the above requirements
and hence used for the design of logic circuits.

• The K-map technique is not suitable for handling the design of complex digital
systems because of the following disadvantages:
• Minimization of logic functions involving more than six variables is unwieldy
• Recognition of prime implicants that may form part of the simplified function relies on the
ability of the human user making it difficult to be sure whether the best selection has been
made.
Quine-McCluskey Minimization Technique
• The Quine Mc-Cluskey method consists of two parts:
• To find by an exhaustive search all the prime implicants
that may form part of the simplified function.
• To identify essential prime implicants obtained from part
1 and choose among the remaining prime implicants
those that give an expression with the least number of
literals
• This method is also known as tabular method.