Teaching Assistants:

Introduction to Digital Systems Design Anahita Shojaei Jose Pinilla

with FPGAs

Lecture 1 - Digital systems overview and introduction to VHDL

Instructors:
Daniel Holanda Noronha, [email protected] Amin Ghasemazar Mohamed Omran
Cristian Grecu, [email protected]

Vancouver Summer Program

2019
2

What we will talk about today

● Course Overview
○ Motivation
○ Topics
○ Labs/Exam
● Digital systems Course Overview - What is this class about?
○ Overview
● VHDL
○ What is VHDL?
○ Basic concepts and syntax

3 4
Course Overview - What is this class about? Course Overview - What is this class about?
Analog Circuit
This class is about designing digital circuits! Signals can have any value

Digital Circuit
Signals can be either 0 or 1

Digital hardware: Electronics that operate on digital signals

Introduction 5 6

Course Overview - Motivation Course Overview - Motivation

1971 - Intel 4004 4-bit microprocessor 1977 - Zilog Z80A 8-bit microprocessor

740 kHz (0.74 MHz) 4 MHz

46 instructions 158 instruction types
2,250 transistors 8,500 transistors

7 CoBra Z80 computer - 1986, Romania 8

Course Overview - Motivation Course Overview - Motivation

1977 – Intel 8086 16-bit microprocessor 2000 – Intel P4 32-bit microprocessor

4.77 MHz to 10 MHz 1.4 GHz to ~4 GHz (4,000 MHz)

29,000 transistors 125,000,000 transistors

Intel:
80286 - 16 bit data bus, 1982
4 GHz is a very high frequency +
80386 - 32 bit data bus, 1985 Energy is proportional to f² →
80486 - 32 bit data bus, 1989 Energy consumption is very high!
AMD Am5x86 - 1995 Solution: More than one core!
Cyrix Cx5x86 - 1995

9 10

Course Overview - Motivation Course Overview - Motivation

2006 – Sony, Toshiba, IBM – Cell processor

8 processing elements
4 GHz
234,000,000 transistors

11 12
Course Overview - Motivation Course Overview - Motivation

2016 – Apple A10 – Mobile processor

4 cores
2.34 GHz
3,300,000,000 transistors

Many components that need faster connection

Solution: Integrate them in a SoC

13 14

Course Overview - Motivation Course Overview - Motivation

● Applications
2016 - Snapdragon 820 mobile
(System on Chip)

Many different components in a single die

15 16
Course Overview - Topics Course Overview - Topics

● Combinational Design
○ Do it all in one clock cycle! ● Who might be interested in this course?
● Sequential design ○ Those of you interested in chip design
○ You can do more if you do things in sequence ○ Those of you interested in control electronics (robots, industrial processes)
■ Ex: Count how many times X was 1 in 10 cycles ○ Those of you interested in communication systems
● Arithmetic circuits ○ Those of you interested in biomedical electronics
○ Adders, multipliers and more ○ Those of you interested in software design (CAD/EDA)
● Datapath design ● Basic prerequisites
○ Path that the input data follows in a processor to become an output ○ Boolean Logic
● Timing strategies ○ Basic Programming
○ Making it run fast and avoiding glitches ○ Interest in Digital Design
● A lot of VHDL

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Course Overview - Labs/Exam Course Overview - Labs/Exam

● Labs ● Labs
○ A significant part of the course is represented by LAB assignments
Preparation Action
○ Use Altera DE0 Board
○ Groups of 2
○ During the lab you will implement your design
○ At the end of the lab the TA will grade your design and your knowledge
○ Total of 4 labs (5th lab is used to repeat something that you didn't like)
○ Need a non-zero grade in at least 2 labs!
○ Read the lab assignment before coming to the lab (time is short)
○ Lab are in MCLD 348/358

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Course Overview - Labs/Exam Course Overview - Labs/Exam

● Lab policy ● Where can I find the class material?

○ Only medical situations are a valid reason for missing the Lab ○ Available on Piazza (www.piazza.com)
○ FPGA boards will be with the students for the entire course ○ Slides distributed before class
○ Try to finish at least 30 min before the session ends (so the TA has time to ○ "Facts Sheet" and "Lab Info" handout
grade you) ● Where can I ask questions about the course?
○ No foods or drinks in the Lab ○ Piazza is a great place to put your questions
● Schedule ● What about the final exam?
○ It will be on August 9th from 9:00-12:00
○ Multiple choice exam (which doesn't mean that it is easy)

21 22

Course Overview - Labs/Exam What we will talk about today

● Textbook (not required) ● Course Overview

○ Fundamentals of Digital Logic with VHDL ○ Motivation
■ Combinational logic (chapters 2, 6) ○ Topics
■ Sequential logic (chapters 7, 8) ○ Labs/Exam
■ Arithmetic circuits (chapter 5) ● Digital systems
■ Datapath & system design (chapter 10) ○ Overview
■ VHDL in (almost) all lectures ● VHDL
○ What is VHDL?
○ Basic concepts and syntax

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 Digital Systems - Overview

Digital systems - Overview

Most of the systems can be viewed as a control/datapath combination

25 Introduction 26

Digital Systems - Overview Digital Systems - Overview

OR AND

● Combinational Circuits
○ A combinational logic block (CLB) is defined as having its output(s)
0 0 1
depending only of its current inputs at any given time. 1 0 0
○ Can be implemented using logic gates, look-up tables (LUTs), or other 1
1
0
1
0
0
means. 0 1
NOR NAND 1
0
1 0
1
1 1 1 1
0 1 1 0 1
0 1 1
0 0 0
XOR XNOR INVERTER Inputs: X=0 Y=1 Z=1
Output: F = ?

Examples? 0 1 1
1 0 0
1 0
27 0 1 28
Digital Systems - Overview Digital Systems - Overview

● What are some of the ways to specify a circuit?

○ 1 - In words:
● What is the truth table of the following circuit? ■ Ex: the output of the block is ‘1’ when at least
one of the inputs is ‘1’
■ May be ambiguous
○ 2 - Truth table
○ 3 - Boolean expression
■ Ex: Z = (A AND B) OR C
○ 4 - Schematic of the circuit

○ 5 - HDL (Hardware description languages)

■ Verilog, VHDL, etc
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Digital Systems - Overview Digital Systems - Overview

● What are the abstraction levels that exist? ● What are the abstraction levels that exist?
■ Behaviour: ■ RTL-level (Register transfer level):
● Description of what the circuit does ● Specify what each functional block will be made of, in terms of
● Ex: You can write a description of the processor without having to multiplexors, ALUs, state machines
design it internally ● Specify connections between components
● You can simulate the processor and confirm that interacts ● How does this help?
correctly with other components (I/O, memory) ○ You get one step closer to the hardware implementation
● You can share the behavioral description with other design teams You can simulate and verify that the design behaves as in
(chipset, compiler) the behavioural specifications (meets your expectations)
● For all these, you do not need to design the processor at ○ Can roughly estimate the size of the design (in terms of
gate/transistor level! #transistors, Si area)
● Problem: Some times might not be possible to convert this to a ○ RTL-level can be synthesized by CAD tools (converted to a
logic circuit (synthesize it) logic circuit)

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Digital Systems - Overview Digital Systems - Overview

● What are the abstraction levels that exist?

● What are the abstraction levels that exist?
■ Layout
■ Logic - Gate-level design
● How the cells are mapped to the circuit?
● Specify the design as a collection of basic gates (AND, OR, NOT)
● Where are they located?
interconnected together (most of the time done automatically by
● How are they physically connected to each other?
CAD tools)
● This is what you need to create a chip
● There are cases where you want to do the gate-level design
ourselves – CAD tools are not perfect!
○ For example, you want to do some smart state assignment
for your FSM (finite state machine), or to implement a faster
block than its synthesis-generated counterpart.

33 34

Digital Systems - Overview What we will talk about today

● What are the abstraction levels that exist?

■ Behaviour: Description of what the circuit does
■ RTL: Using big blocks made out of simple logic (FFs and muxes) ● Course Overview
■ Logic: Simple AND, OR, gates ○ Motivation
■ Layout: How the cells are mapped to the circuit (placed and routed) ○ Topics
○ Labs/Exam
● Digital systems
○ Overview
● VHDL
○ What is VHDL?
○ Basic concepts and syntax

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 VHDL - What is VHDL?

● What does it stand for:

○ VHSIC Hardware Description Language
■ Very High Speed Integrated Circuits
● What it is:
○ A formal language for describing hardware (mostly digital, possible analog)
– standardized by IEEE
VHDL - What is VHDL? ● The key word is description
● What it is not
○ VHDL is not a programming language!!!
● What’s the difference?
○ Program = sequence of computer instructions (operations are executed
one after another)
○ Hardware = concurrent (everything happens in parallel, at the same time)

37 38

VHDL - What is VHDL? VHDL - What is VHDL?

● But… why do we really need VHDL? Why can't I just use gates?
○ Answer: Because we need abstraction in order to be productive!
■ The process of finding an efficient set of logic gates to perform a given ● How can we specify a circuit using VHDL?
function is labor intensive and error prone ○ In VHDL, we can specify hardware in two ways:
■ Structurally
■ In the 1990s, designers discovered that they were far more productive ● RTL
if they worked at a higher level of abstraction ● Logic
● Goal: allowing a computer-aided design (CAD) tool to produce ■ Behaviorally
○ Can’t do this with schematics!
the optimized gates from a higher level.
○ More importantly, we can combine structural and behavioural
● Two main languages representations in the same design (and this happens almost all the time)
○ VHDL and Verilog

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VHDL - What is VHDL? VHDL - What is VHDL?

● Simulation and Synthesis ● Simulation and Synthesis

○ The two major purposes of HDLs are logic simulation and synthesis. ○ Simulation bugs:
○ Simulation: ■ Human errors in hardware designs are called bugs
■ inputs are applied to a module ● Testing a system in the laboratory is time-consuming
■ outputs are generated ● Discovering the cause of errors in the lab can be extremely
■ Used to verify that the module operates correctly difficult, because only signals routed to the chip pins can be
■ Why can't we always use simulation? (think of machine learning) observed
● Correcting errors after the system is built can be devastatingly
expensive
○ Intel’s infamous FDIV (floating point division) bug in the
Pentium processor forced the company to recall chips after
they had shipped, at a total cost of $475 million.

41 42

VHDL - What is VHDL? VHDL - Basic concepts and syntax

● Simulation and Synthesis

● What is a module?
○ What is synthesis?
○ Answer: A block of hardware with inputs and outputs
■ Is the generation of a gate-level description from a hardware
■ AND gate
description language
■ a multiplexer
■ a priority circuit
■ … are all examples of hardware modules

43 44
 VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax

● Important parts of a module in VHDL ● Simple example: XOR gate

○ Library use clause
■ Digital signals should be declared to be STD_LOGIC type library ieee;
■ STD_LOGIC signals can have a value of '0' or '1', as well as floating and use ieee.std_logic_1164.all;
undefined values (more on that later)
■ STD_LOGIC type is defined in the IEEE.STD_LOGIC_1164 library, which entity XOR_GATE is
is why the library must be used port (a, b: in STD_LOGIC;
○ Entity declaration z: out STD_LOGIC);
■ Lists the module name and its inputs and outputs. end XOR_GATE;
○ Architecture body
■ Defines what the module does architecture XOR_BEHAV of XOR_GATE is
begin
z<=a xor b;
end XOR_BEHAV;
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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax

● Bigger example: ● Port: Signals that go in and out of the module entity BIG_CIRCUIT is
port ( a, b, c : in STD_LOGIC;
○ Possible port modes: z : out STD_LOGIC);
library ieee; ■ In: you can read from it, but not write end BIG_CIRCUIT;
use ieee.std_logic_1164.all; ■ out: you can write, but you can't read from it
■ Inout: you can both read and write from it
entity BIG_CIRCUIT is ■ Buffer: out that you can read from inside of
port ( a, b, c : in STD_LOGIC; your design
z : out STD_LOGIC); ■ Linkage: used in analog simulation and to
end BIG_CIRCUIT; hook-up power/ground ports (don't worry
about this for this course)
architecture BIG_BEHAV of BIG_CIRCUIT is
begin
z <= (not a and b) or (b and not c);
end BIG_BEHAV; Note: Don't use inout mode all the time. This might be bad for synthesis tool
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 VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax

● Using comments
● Architecture:
○ Each entity may have more than one architecture OK code... Great code!
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity MY_ENTITY is
port ( a, b : in STD_LOGIC; entity BIG_CIRCUIT is -- Entity with 3 inputs and 1 output
z : out STD_LOGIC); port ( a, b, c : in STD_LOGIC; entity BIG_CIRCUIT is
end MY_ENTITY; z : out STD_LOGIC); port ( a, b, c : in STD_LOGIC;
end BIG_CIRCUIT; z : out STD_LOGIC);
end BIG_CIRCUIT;
architecture BIG_BEHAV of BIG_CIRCUIT is
architecture ARCH_OR of my_entity is architecture ARCH_AND of MY_ENTITY is begin -- architecture for assignment 4(a)
begin begin z <= (not a and b) or (b and not c); architecture BIG_BEHAV of BIG_CIRCUIT is
z <= a or b; z <= a and b; end BIG_BEHAV; begin
end ARCH_OR; end ARCH_AND; z <= (not a and b) or (b and not c);
end BIG_BEHAV;

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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax

● Multiple output ports? No problem!

● VHDL is not case-sensitive
○ y1 and Y1 are the same signal in VHDL library ieee;
○ Other tools that may read your file might be case sensitive! use ieee.std_logic_1164.all;
■ This can lead to nasty bugs if you name things in a bad way
entity MY_ENTITY is
○ Good practice: pretend that it is case sensitive! port (A, B,C,D : in STD_LOGIC;
X,Y,Z : out STD_LOGIC);
end MY_ENTITY;

architecture MY_ARCH of MY_ENTITY is

begin
X <= A and B and C;
Y <= C and not D; Note:
Z <= A xor B xor D; all outputs are assigned
end MY_ARCH; simultaneously
(concurrently)
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 VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax

● Signals: Internal wires that are not inputs or outputs ● Dealing with busses (vectors)
○ VHDL uses STD_LOGIC_VECTOR to indicate busses of STD_LOGIC
○ Little-endian order
library ieee; ■ the least significant bit has the smallest bit number
use ieee.std_logic_1164.all;
■ Ex: STD_LOGIC_VECTOR(3 downto 0) represents a 4-bit bus.
entity MY_ENTITY is ■ The bits, from most significant to least significant, are:
port ( a, b: in STD_LOGIC; ● a(3), a(2), a(1), and a(0)
z: out STD_LOGIC);
end MY_ENTITY; ○ Big-endian order
■ Ex: STD_LOGIC_VECTOR(0 to 3)
architecture MY_ARCH of MY_ENTITY is ■ The bits, from most significant to least significant, are:
signal s1, s2: STD_LOGIC;
begin ● a(0), a(1), a(2), and a(3)
s1<=not a and b;
s2<=not b and a;
z<=s1 or s2;
end MY_ARCH;
53 54

VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax

● Dealing with busses (vectors) ● Useful things we can do with busses

○ Endianness matters only for operators, such as addition, where the sum of ○ Initialize a STD_LOGIC_VECTOR signal (array of bits) in a single statement
one column carries over into the next.
○ Either ordering is acceptable, as long as it is used consistently ■ x <= “10101010”;
○ We will consistently use the little-endian order ○ Copy the logic values on a bus onto another bus:
■ second_bus <= first_bus; (both must have the same type and # of
elements)

55 56
 VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax

● Useful things we can do with busses 1010 1010 1111 -- mainbus

● Useful things we can do with busses
○ Access the wires of a bus individually: 1010 -- opcode ○ Concatenate vectors:
■ signal parity: STD_LOGIC; ■ Example: if the following two signals are defined
signal data: STD_LOGIC_VECTOR(15 downto 0); signal s1: STD_LOGIC_VECTOR(3 downto 0);
… signal s2: STD_LOGIC_VECTOR(7 downto 0);
parity <= data(15); Then the following assignments are legal:
○ Access “slices” of bit_vector signals: ○ s2 <= “0000” & “1111”;
signal mainbus: STD_LOGIC_VECTOR(15 downto 0); ○ s2 <= “0000” & s1;
signal opcode: STD_LOGIC_VECTOR (3 downto 0); ○ s2 <= ‘1’ & “0000000”;
………. ○ s2 <= ‘1’ & ‘0’ & ‘1’ & ‘0’ & ‘1’ & ‘0’ & ‘1’ & ‘0’;
opcode <= mainbus(15 downto 12); ○ s2 <= ‘0’ & s1 & “111”;

Note: you can only concatenate one-dimensional arrays!

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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
● Dealing with busses (vectors)
● Dealing with busses (vectors)
library ieee;
use ieee.std_logic_1164.all;

library ieee; entity MY_ENTITY is

use ieee.std_logic_1164.all; port ( a,b: in STD_LOGIC_VECTOR(3 downto 0);
y1,y2,y3,y4,
entity MY_ENTITY is y5: out STD_LOGIC_VECTOR(3 downto 0) );
port ( a: in STD_LOGIC_VECTOR(3 downto 0); end MY_ENTITY;
y: out STD_LOGIC_VECTOR(3 downto 0) );
end MY_ENTITY; architecture MY_ARCH of MY_ENTITY is
begin
architecture MY_ARCH of MY_ENTITY is y1 <= a and b;
begin y2 <= a or b;
y<=not a y3 <= a xor b;
end MY_ARCH; y4 <= a nand b;
y5 <= a nor b;
end MY_ARCH;
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